From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
kvm@vger.kernel.org
Cc: Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Zenghui Yu <yuzenghui@huawei.com>,
Bjorn Andersson <andersson@kernel.org>,
Christoffer Dall <christoffer.dall@arm.com>,
Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com>,
Chase Conklin <chase.conklin@arm.com>,
Eric Auger <eauger@redhat.com>
Subject: [PATCH v2 10/12] KVM: arm64: nv: Sanitise CNTHCTL_EL2
Date: Tue, 17 Dec 2024 14:23:18 +0000 [thread overview]
Message-ID: <20241217142321.763801-11-maz@kernel.org> (raw)
In-Reply-To: <20241217142321.763801-1-maz@kernel.org>
Inject some sanity in CNTHCTL_EL2, ensuring that we don't handle
more than we advertise to the guest.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/include/asm/kvm_host.h | 2 +-
arch/arm64/kvm/nested.c | 15 +++++++++++++++
include/clocksource/arm_arch_timer.h | 2 ++
3 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index e18e9244d17a4..cf571d41faa89 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -490,7 +490,6 @@ enum vcpu_sysreg {
VBAR_EL2, /* Vector Base Address Register (EL2) */
RVBAR_EL2, /* Reset Vector Base Address Register */
CONTEXTIDR_EL2, /* Context ID Register (EL2) */
- CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */
SP_EL2, /* EL2 Stack Pointer */
CNTHP_CTL_EL2,
CNTHP_CVAL_EL2,
@@ -501,6 +500,7 @@ enum vcpu_sysreg {
MARKER(__SANITISED_REG_START__),
TCR2_EL2, /* Extended Translation Control Register (EL2) */
MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */
+ CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */
/* Any VNCR-capable reg goes after this point */
MARKER(__VNCR_START__),
diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c
index 9b36218b48def..9113c6025d6f3 100644
--- a/arch/arm64/kvm/nested.c
+++ b/arch/arm64/kvm/nested.c
@@ -1271,6 +1271,21 @@ int kvm_init_nv_sysregs(struct kvm *kvm)
res0 |= MDCR_EL2_EnSTEPOP;
set_sysreg_masks(kvm, MDCR_EL2, res0, res1);
+ /* CNTHCTL_EL2 */
+ res0 = GENMASK(63, 20);
+ res1 = 0;
+ if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, RME, IMP))
+ res0 |= CNTHCTL_CNTPMASK | CNTHCTL_CNTVMASK;
+ if (!kvm_has_feat(kvm, ID_AA64MMFR0_EL1, ECV, CNTPOFF)) {
+ res0 |= CNTHCTL_ECV;
+ if (!kvm_has_feat(kvm, ID_AA64MMFR0_EL1, ECV, IMP))
+ res0 |= (CNTHCTL_EL1TVT | CNTHCTL_EL1TVCT |
+ CNTHCTL_EL1NVPCT | CNTHCTL_EL1NVVCT);
+ }
+ if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, VH, IMP))
+ res0 |= GENMASK(11, 8);
+ set_sysreg_masks(kvm, CNTHCTL_EL2, res0, res1);
+
return 0;
}
diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm_arch_timer.h
index c62811fb41309..ce6521ad04d12 100644
--- a/include/clocksource/arm_arch_timer.h
+++ b/include/clocksource/arm_arch_timer.h
@@ -26,6 +26,8 @@
#define CNTHCTL_EL1TVCT (1 << 14)
#define CNTHCTL_EL1NVPCT (1 << 15)
#define CNTHCTL_EL1NVVCT (1 << 16)
+#define CNTHCTL_CNTVMASK (1 << 18)
+#define CNTHCTL_CNTPMASK (1 << 19)
enum arch_timer_reg {
ARCH_TIMER_REG_CTRL,
--
2.39.2
next prev parent reply other threads:[~2024-12-17 14:33 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-17 14:23 [PATCH v2 00/12] KVM: arm64: Add NV timer support Marc Zyngier
2024-12-17 14:23 ` [PATCH v2 01/12] KVM: arm64: nv: Add handling of EL2-specific timer registers Marc Zyngier
2024-12-21 1:38 ` Oliver Upton
2024-12-21 9:57 ` Marc Zyngier
2024-12-21 21:58 ` Oliver Upton
2024-12-17 14:23 ` [PATCH v2 02/12] KVM: arm64: nv: Sync nested timer state with FEAT_NV2 Marc Zyngier
2025-01-06 2:19 ` Wei-Lin Chang
2025-01-26 15:25 ` Volodymyr Babchuk
2025-01-27 17:15 ` Marc Zyngier
2025-01-28 11:29 ` Volodymyr Babchuk
2025-01-28 12:17 ` Marc Zyngier
2025-01-28 13:56 ` Volodymyr Babchuk
2024-12-17 14:23 ` [PATCH v2 03/12] KVM: arm64: nv: Publish emulated timer interrupt state in the in-memory state Marc Zyngier
2024-12-17 14:23 ` [PATCH v2 04/12] KVM: arm64: nv: Use FEAT_ECV to trap access to EL0 timers Marc Zyngier
2024-12-17 14:23 ` [PATCH v2 05/12] KVM: arm64: nv: Accelerate EL0 timer read accesses when FEAT_ECV in use Marc Zyngier
2024-12-17 14:23 ` [PATCH v2 06/12] KVM: arm64: nv: Accelerate EL0 counter accesses from hypervisor context Marc Zyngier
2024-12-17 14:23 ` [PATCH v2 07/12] KVM: arm64: Handle counter access early in non-HYP context Marc Zyngier
2024-12-17 14:23 ` [PATCH v2 08/12] KVM: arm64: nv: Add trap routing for CNTHCTL_EL2.EL1{NVPCT,NVVCT,TVT,TVCT} Marc Zyngier
2024-12-17 14:23 ` [PATCH v2 09/12] KVM: arm64: nv: Propagate CNTHCTL_EL2.EL1NV{P,V}CT bits Marc Zyngier
2025-01-06 2:33 ` Wei-Lin Chang
2025-01-17 15:19 ` Marc Zyngier
2025-01-21 6:04 ` Wei-Lin Chang
2024-12-17 14:23 ` Marc Zyngier [this message]
2024-12-17 14:23 ` [PATCH v2 11/12] KVM: arm64: Work around x1e's CNTVOFF_EL2 bogosity Marc Zyngier
2024-12-17 14:23 ` [PATCH v2 12/12] KVM: arm64: nv: Document EL2 timer API Marc Zyngier
2025-01-02 19:15 ` [PATCH v2 00/12] KVM: arm64: Add NV timer support Oliver Upton
2025-01-02 19:25 ` Marc Zyngier
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