From: Conor Dooley <conor@kernel.org>
To: Kever Yang <kever.yang@rock-chips.com>
Cc: heiko@sntech.de, linux-rockchip@lists.infradead.org,
devicetree@vger.kernel.org, Conor Dooley <conor+dt@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
linux-kernel@vger.kernel.org,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Elaine Zhang <zhangqing@rock-chips.com>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 01/38] dt-bindings: clock: add rk3562 cru bindings
Date: Sun, 22 Dec 2024 14:51:20 +0000 [thread overview]
Message-ID: <20241222-grandpa-vessel-66e9ca9cde75@spud> (raw)
In-Reply-To: <20241220103825.3509421-2-kever.yang@rock-chips.com>
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On Fri, Dec 20, 2024 at 06:37:47PM +0800, Kever Yang wrote:
> Document the device tree bindings of the rockchip rk3562 SoC
> clock and reset unit.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> .../bindings/clock/rockchip,rk3562-cru.yaml | 62 +++++++++++++++++++
> 1 file changed, 62 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml
> new file mode 100644
> index 000000000000..aa8dedf2bfce
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml
> @@ -0,0 +1,62 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/rockchip,rk3562-cru.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip rk3562 Clock and Reset Control Module
> +
> +maintainers:
> + - Elaine Zhang <zhangqing@rock-chips.com>
> + - Heiko Stuebner <heiko@sntech.de>
> +
> +description:
> + The RK3562 clock controller generates the clock and also implements a reset
> + controller for SoC peripherals. For example it provides SCLK_UART2 and
> + PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART
> + module.
> +
> +properties:
> + compatible:
> + const: rockchip,rk3562-cru
> +
> + reg:
> + maxItems: 1
> +
> + "#clock-cells":
> + const: 1
> +
> + "#reset-cells":
> + const: 1
> +
> + clocks:
> + maxItems: 2
> +
> + clock-names:
> + items:
> + - const: xin24m
> + - const: xin32k
> +
> + rockchip,grf:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle to the syscon managing the "general register files" (GRF),
> + if missing pll rates are not changeable, due to the missing pll
> + lock status.
Two questions:
- Why would it ever be missing? Seems like you should make it required.
- Why is it not possible to look the grf up by compatible rather than
phandle?
Cheers,
Conor.
> +
> +required:
> + - compatible
> + - reg
> + - "#clock-cells"
> + - "#reset-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + clock-controller@ff100000 {
> + compatible = "rockchip,rk3562-cru";
> + reg = <0xff100000 0x40000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> --
> 2.25.1
>
>
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next prev parent reply other threads:[~2024-12-22 14:52 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20241220103825.3509421-1-kever.yang@rock-chips.com>
2024-12-20 10:37 ` [PATCH 01/38] dt-bindings: clock: add rk3562 cru bindings Kever Yang
2024-12-22 14:51 ` Conor Dooley [this message]
2024-12-24 8:36 ` Kever Yang
2024-12-20 10:37 ` [PATCH 03/38] clk: rockchip: Add clock controller for the RK3562 Kever Yang
2024-12-20 10:37 ` [PATCH 04/38] dt-bindings: pinctrl: Add rk3562 pinctrl support Kever Yang
2024-12-22 14:48 ` Conor Dooley
2024-12-22 16:02 ` Heiko Stübner
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