[PATCH RESEND 15/22] clk: sunxi-ng: sun8i-de2: add pll-com clock support

Parthiban Nallathambi
2024-12-27T13:20:26Z

add optional pll-com support which is available in some platforms
like A100/A133, which is used by the display clock. There is no
documentation reference or details in DE 2.0 specification.

But these changes are needed to get the display clock to work and
this is inherited from the vendor BSP.

Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index f2aa71206bc2..3e28c32050e0 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -241,7 +241,7 @@ static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = {

static int sunxi_de2_clk_probe(struct platform_device *pdev)
{
- struct clk *bus_clk, *mod_clk;
+ struct clk *bus_clk, *mod_clk, *pll_clk;
struct reset_control *rstc;
void __iomem *reg;
const struct sunxi_ccu_desc *ccu_desc;
@@ -265,6 +265,11 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev)
return dev_err_probe(&pdev->dev, PTR_ERR(mod_clk),
"Couldn't get mod clk\n");

+ pll_clk = devm_clk_get_optional(&pdev->dev, "pll-com");
+ if (IS_ERR(pll_clk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(pll_clk),
+ "Couldn't get pll clk\n");
+
rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
if (IS_ERR(rstc))
return dev_err_probe(&pdev->dev, PTR_ERR(rstc),
@@ -283,12 +288,20 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev)
goto err_disable_bus_clk;
}

+ if (pll_clk) {
+ ret = clk_prepare_enable(pll_clk);
+ if (ret) {
+ dev_err(&pdev->dev, "Couldn't enable pll clk: %d\n", ret);
+ goto err_disable_mod_clk;
+ }
+ }
+
/* The reset control needs to be asserted for the controls to work */
ret = reset_control_deassert(rstc);
if (ret) {
dev_err(&pdev->dev,
"Couldn't deassert reset control: %d\n", ret);
- goto err_disable_mod_clk;
+ goto err_disable_pll_clk;
}

ret = devm_sunxi_ccu_probe(&pdev->dev, reg, ccu_desc);
@@ -299,6 +312,8 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev)

err_assert_reset:
reset_control_assert(rstc);
+err_disable_pll_clk:
+ clk_disable_unprepare(pll_clk);
err_disable_mod_clk:
clk_disable_unprepare(mod_clk);
err_disable_bus_clk:

--
2.39.5