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charset=us-ascii Content-Disposition: inline In-Reply-To: <20241220072240.1003352-8-anshuman.khandual@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250102_075800_291477_181E61AA X-CRM114-Status: GOOD ( 13.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Dec 20, 2024 at 12:52:40PM +0530, Anshuman Khandual wrote: > FEAT_PMUv3p9 registers such as PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 > access from EL1 requires appropriate EL2 fine grained trap configuration > via FEAT_FGT2 based trap control registers HDFGRTR2_EL2 and HDFGWTR2_EL2. > Otherwise such register accesses will result in traps into EL2. > > Add a new helper __init_el2_fgt2() which initializes FEAT_FGT2 based fine > grained trap control registers HDFGRTR2_EL2 and HDFGWTR2_EL2 (setting the > bits nPMICNTR_EL0, nPMICFILTR_EL0 and nPMUACR_EL1) to enable access into > PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 registers. > > Also update booting.rst with SCR_EL3.FGTEn2 requirement for all FEAT_FGT2 > based registers to be accessible in EL2. > > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Mark Rutland > Cc: Rob Herring > Cc: Jonathan Corbet > Cc: Marc Zyngier > Cc: Oliver Upton > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-doc@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > Cc: kvmarm@lists.linux.dev > Signed-off-by: Anshuman Khandual > --- > Documentation/arch/arm64/booting.rst | 18 ++++++++++++++++++ > arch/arm64/include/asm/el2_setup.h | 25 +++++++++++++++++++++++++ > 2 files changed, 43 insertions(+) Tested-by: Rob Herring (Arm) Reviewed-by: Rob Herring (Arm)