From: Bjorn Helgaas <helgaas@kernel.org>
To: Jianjun Wang <jianjun.wang@mediatek.com>
Cc: "Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Matthias Brugger" <matthias.bgg@gmail.com>,
"AngeloGioacchino Del Regno"
<angelogioacchino.delregno@collabora.com>,
"Ryder Lee" <ryder.lee@mediatek.com>,
linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
"Xavier Chang" <Xavier.Chang@mediatek.com>
Subject: Re: [PATCH 2/5] PCI: mediatek-gen3: Add MT8196 support
Date: Fri, 3 Jan 2025 13:02:45 -0600 [thread overview]
Message-ID: <20250103190245.GA4190015@bhelgaas> (raw)
In-Reply-To: <20250103060035.30688-3-jianjun.wang@mediatek.com>
On Fri, Jan 03, 2025 at 02:00:12PM +0800, Jianjun Wang wrote:
> The MT8196 is an ARM platform SoC that has the same PCIe IP as the
> MT8195.
> However, it requires additional settings in the pextpcfg registers.
> Introduce pextpcfg in PCIe driver for these settings.
Add blank lines between paragraphs.
> + * The values of some registers are different in RC and EP mode. Therefore,
> + * call soc->pre_init after the mode change in case it depends on these registers.
Wrap this to fit in 80 columns like the rest of the file.
> + /* Adjust SYS_CLK_RDY_TIME ot 10us to avoid glitch */
s/ot/to/
Is this an erratum? Is there any spec or erratum citation you can
include in the comment?
> + val = readl_relaxed(pcie->base + PCIE_RESOURCE_CTRL_REG);
> + val &= ~PCIE_SYS_CLK_RDY_TIME_MASK;
> + val |= PCIE_SYS_CLK_RDY_TIME_TO_10US;
> + writel_relaxed(val, pcie->base + PCIE_RESOURCE_CTRL_REG);
next prev parent reply other threads:[~2025-01-03 19:05 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-03 6:00 [PATCH 0/5] PCI: mediatek-gen3: Add MT8196 support Jianjun Wang
2025-01-03 6:00 ` [PATCH 1/5] dt-bindings: " Jianjun Wang
2025-01-03 9:10 ` Krzysztof Kozlowski
2025-01-06 9:26 ` Jianjun Wang (王建军)
2025-01-06 12:27 ` Krzysztof Kozlowski
2025-01-07 8:43 ` Jianjun Wang (王建军)
2025-01-07 9:02 ` Chen-Yu Tsai
2025-01-08 6:53 ` Jianjun Wang (王建军)
2025-01-08 7:16 ` Krzysztof Kozlowski
2025-01-08 7:30 ` Jianjun Wang (王建军)
2025-01-03 9:26 ` AngeloGioacchino Del Regno
2025-01-06 9:19 ` Jianjun Wang (王建军)
2025-01-07 13:04 ` AngeloGioacchino Del Regno
2025-01-08 7:24 ` Jianjun Wang (王建军)
2025-01-03 6:00 ` [PATCH 2/5] " Jianjun Wang
2025-01-03 19:02 ` Bjorn Helgaas [this message]
2025-01-07 1:51 ` Jianjun Wang (王建军)
2025-01-03 6:00 ` [PATCH 3/5] PCI: mediatek-gen3: Disable ASPM L0s Jianjun Wang
2025-01-03 9:16 ` AngeloGioacchino Del Regno
2025-01-07 2:18 ` Jianjun Wang (王建军)
2025-01-07 11:44 ` AngeloGioacchino Del Regno
2025-01-07 23:07 ` Bjorn Helgaas
2025-01-03 19:15 ` Bjorn Helgaas
2025-01-07 2:44 ` Jianjun Wang (王建军)
2025-01-07 23:06 ` Bjorn Helgaas
2025-01-06 16:09 ` Manivannan Sadhasivam
2025-01-03 6:00 ` [PATCH 4/5] PCI: mediatek-gen3: Don't reply AXI slave error Jianjun Wang
2025-01-03 9:29 ` AngeloGioacchino Del Regno
2025-01-06 9:27 ` Jianjun Wang (王建军)
2025-01-03 19:19 ` Bjorn Helgaas
2025-01-06 9:31 ` Jianjun Wang (王建军)
2025-01-06 16:16 ` Manivannan Sadhasivam
2025-01-07 3:21 ` Jianjun Wang (王建军)
2025-01-03 6:00 ` [PATCH 5/5] PCI: mediatek-gen3: Keep PCIe power and clocks if suspend-to-idle Jianjun Wang
2025-01-03 9:14 ` AngeloGioacchino Del Regno
2025-01-03 19:13 ` Bjorn Helgaas
2025-01-06 16:23 ` Manivannan Sadhasivam
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