From: Kory Maincent <kory.maincent@bootlin.com>
To: Oleksij Rempel <o.rempel@pengutronix.de>
Cc: "Maxime Chevallier" <maxime.chevallier@bootlin.com>,
davem@davemloft.net, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org, thomas.petazzoni@bootlin.com,
"Andrew Lunn" <andrew@lunn.ch>,
"Jakub Kicinski" <kuba@kernel.org>,
"Eric Dumazet" <edumazet@google.com>,
"Paolo Abeni" <pabeni@redhat.com>,
"Russell King" <linux@armlinux.org.uk>,
linux-arm-kernel@lists.infradead.org,
"Christophe Leroy" <christophe.leroy@csgroup.eu>,
"Herve Codina" <herve.codina@bootlin.com>,
"Florian Fainelli" <f.fainelli@gmail.com>,
"Heiner Kallweit" <hkallweit1@gmail.com>,
"Vladimir Oltean" <vladimir.oltean@nxp.com>,
"Marek Behún" <kabel@kernel.org>,
"Nicolò Veronese" <nicveronese@gmail.com>,
"Simon Horman" <horms@kernel.org>,
mwojtas@chromium.org, "Antoine Tenart" <atenart@kernel.org>
Subject: Re: [PATCH net-next RFC 0/5] net: phy: Introduce a port representation
Date: Sat, 4 Jan 2025 23:23:59 +0100 [thread overview]
Message-ID: <20250104232359.2c7a7090@kmaincent-XPS-13-7390> (raw)
In-Reply-To: <Z2hgbdeTXjqWKa14@pengutronix.de>
On Sun, 22 Dec 2024 19:54:37 +0100
Oleksij Rempel <o.rempel@pengutronix.de> wrote:
> transformer {
> model = "ABC123"; /* Transformer model number */
> manufacturer = "TransformerCo"; /* Manufacturer name */
>
> pairs {
> pair@0 {
> name = "A"; /* Pair A */
> pins = <1 2>; /* Connector pins */
> phy-mapping = <PHY_TX0_P PHY_TX0_N>; /* PHY pin mapping */
> center-tap = "CT0"; /* Central tap identifier */
> /* if pse-positive and pse-negative are present -
> polarity is configurable */ pse-positive = <PSE_OUT0_0>; /* PSE-controlled
> positive pin -> CT0 */ pse-negative = <PSE_OUT0_1>; /* PSE-controlled
> negative pin -> CT0 */ };
> pair@1 {
> name = "B"; /* Pair B */
> pins = <3 6>; /* Connector pins */
> phy-mapping = <PHY_RX0_P PHY_RX0_N>;
> center-tap = "CT1"; /* Central tap identifier */
> pse-positive = <PSE_OUT1_0>;
> pse-negative = <PSE_OUT1_1>;
> };
> pair@2 {
> name = "C"; /* Pair C */
> pins = <4 5>; /* Connector pins */
> phy-mapping = <PHY_TXRX1_P PHY_TXRX1_N>; /* PHY
> connection only */ center-tap = "CT2"; /* Central tap identifier */
> pse-positive = <PSE_OUT2_0>;
> pse-negative = <PSE_OUT2_1>;
> };
> pair@3 {
> name = "D"; /* Pair D */
> pins = <7 8>; /* Connector pins */
> phy-mapping = <PHY_TXRX2_P PHY_TXRX2_N>; /* PHY
> connection only */ center-tap = "CT3"; /* Central tap identifier */
> pse-positive = <PSE_OUT3_0>;
> pse-negative = <PSE_OUT3_1>;
> };
> };
> };
>
> pse = <&pse1>; /* Reference to the attached PSE controller */
The PSE pairset and polarity are already described in the PSE bindings.
https://elixir.bootlin.com/linux/v6.12.6/source/Documentation/devicetree/bindings/net/pse-pd/pse-controller.yaml
I am not sure it is a good idea to have PSE information at two different places.
> leds {
> ethernet-leds {
> link = <ð_led0>; /* Link status LED */
> activity = <ð_led1>; /* Activity LED */
> speed = <ð_led2>; /* Speed indication LED */
> };
>
> poe-leds {
> power = <&poe_led0>; /* PoE power status LED */
> fault = <&poe_led1>; /* PoE fault indication LED */
> budget = <&poe_led2>; /* PoE budget usage LED */
> };
> };
Maybe the PoE leds should also land in our pse-pis binding.
> In case of PoDL, we will have something like this:
>
> pair@0 {
> name = "A"; /* Single pair for 10BaseT1L */
> pins = <1 2>; /* Connector pins */
> phy-mapping = <PHY_TXRX0_P PHY_TXRX0_N>; /* PHY pin mapping */
> podl-mapping = <PODL_OUT0_P PODL_OUT0_N>; /* PoDL mapping: Positive and
> negative outputs */ };
We should do the same for PoDL. Put all information in the same place, the PSE
bindings.
Regards,
--
Köry Maincent, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
next prev parent reply other threads:[~2025-01-04 22:25 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-20 20:14 [PATCH net-next RFC 0/5] net: phy: Introduce a port representation Maxime Chevallier
2024-12-20 20:15 ` [PATCH net-next RFC 1/5] net: ethtool: common: Make BaseT a 4-lanes mode Maxime Chevallier
2024-12-20 20:15 ` [PATCH net-next RFC 2/5] net: ethtool: Introduce ETHTOOL_LINK_MEDIUM_* values Maxime Chevallier
2024-12-20 20:15 ` [PATCH net-next RFC 3/5] net: ethtool: Export the link_mode_params definitions Maxime Chevallier
2024-12-20 20:15 ` [PATCH net-next RFC 4/5] net: phy: Introduce PHY ports representation Maxime Chevallier
2024-12-20 20:15 ` [PATCH net-next RFC 5/5] net: phy: dp83822: Add support for phy_port representation Maxime Chevallier
2024-12-22 15:59 ` [PATCH net-next RFC 0/5] net: phy: Introduce a port representation Oleksij Rempel
2024-12-22 18:54 ` Oleksij Rempel
2025-01-02 10:48 ` Russell King (Oracle)
2025-01-02 17:03 ` Oleksij Rempel
2025-01-07 13:26 ` Kory Maincent
2025-01-07 14:02 ` Oleksij Rempel
2025-01-07 14:43 ` Kory Maincent
2025-01-07 14:53 ` Oleksij Rempel
2025-01-07 15:14 ` Russell King (Oracle)
2025-01-07 15:54 ` Oleksij Rempel
2025-01-07 15:12 ` Russell King (Oracle)
2025-01-07 16:13 ` Andrew Lunn
2025-01-07 16:15 ` Maxime Chevallier
2025-01-07 16:22 ` Andrew Lunn
2025-01-07 16:41 ` Oleksij Rempel
2025-01-07 16:49 ` Oleksij Rempel
2025-01-08 7:25 ` Maxime Chevallier
2025-01-08 8:12 ` Oleksij Rempel
2025-01-04 22:23 ` Kory Maincent [this message]
2025-01-06 18:17 ` Oleksij Rempel
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