[PATCH v2 00/13] sunxi: A100/A133 second stage support

[PATCH v2 00/13] sunxi: A100/A133 second stage support

[Cody Eksal]

Hello again!

This is V2 of this series [5], with some changes that were requested and
others that were made after testing on more devices. Thank you for all of
your feedback! A changelog is available below.

==================
Back in 2020, two Allwinner employees, Yangtao Li and Shuosheng Huang, each
submitted a patch series for the A100 series of SoCs; [1] intended to add
support for the watchdog, ARM PMU, DMA, USB, and (e)MMC controller, and [2]
implemented DVFS support. Some patches from the first series landed, but
the rest were seemingly abandoned.

Although references to the A100 have been removed by Allwinner, it is
believed that the A133 and A133 Plus, which are still available, are simply
better binned variants of the A100; no other differences have been noted
thus far, and the drivers for the A100 work on the A133 without any
additional modifications. There has been a resurgence of interest in the
A133; patches to allow mainline U-Boot to run on these devices are
currently in progress.

I have rebased the patches that failed to land, applying the feedback
provided by maintainers at the time. Some DT binding patches were added, as
there were a few cases where compatibles were used without being
documented. Minor reworks were necessary to apply certain patches, as the
drivers they modified have matured over time.

Patches 1 and 2 add PMU and watchdog nodes to the device tree. This is
followed by patches 3-7, which implement support for the USB host and OTG
peripherals. Patches 8-10 add MMC nodes, rounding out what originally
made up the first patch series; support for these already exists from
earlier patches, though patch 7 fixes an issue with the clock definitions
preventing the MMC controller from initializing. Patches 11-13 finish the
job of the second original series and this series, implementing OPP and
enabling DVFS on these SoCs.

This series is also available on GitHub [3].

A sincere thanks to Andre for encouraging me to submit these patches,
Parthiban for testing this tree on his board, and to the linux-sunxi
community and its resources for pointing me to these abandoned series in
the first place [4].

[1] https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=380887&archive=both&state=*
[2] https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=396055&archive=both&state=*
[3] https://github.com/BrokenR3C0RD/linux-a100/compare/c2ee9f59..allwinner-a100
[4] https://linux-sunxi.org/Linux_mainlining_effort#Work_In_Progress
[5] https://lore.kernel.org/all/20241024170540.2721307-1-masterr3c0rd@epochal.quest/

Changelog - V2:
 - Change name of opp table to match bindings and pass CHECK_DTBS
 - Drop "phy: sun4i-usb: add support for A100 USB PHY" in favor of
   falling back to "allwinner,sun20i-d1-usb-phy".
 - Add "allwinner,sun50i-a100" to the cpufreq-dt-platform blacklist
 - Update dt-bindings changes to keep intended ordering of compatibles
 - Update regs that were too small in the usbphy bindings
 - Add patch to remove CLK_SET_RATE_NO_REPARENT from the MMC drivers.
 - Fix error in the description of "arm64: dts: allwinner: a100: add usb
   related nodes"
 - Add acks and reviews from Andre and Rob


Cody Eksal (5):
  dt-bindings: phy: sun50i-a64: add a100 compatible
  dt-bindings: usb: Add A100 compatible string
  dt-bindings: usb: sunxi-musb: Add A100 compatible string
  clk: sunxi-ng: a100: enable MMC clock reparenting
  dt-bindings: opp: h6: Add A100 operating points

Shuosheng Huang (2):
  cpufreq: sun50i: add a100 cpufreq support
  arm64: dts: allwinner: a100: Add CPU Operating Performance Points
    table

Yangtao Li (6):
  arm64: dts: allwinner: A100: Add PMU mode
  arm64: dts: allwinner: a100: add watchdog node
  arm64: dts: allwinner: a100: add usb related nodes
  arm64: allwinner: A100: enable EHCI, OHCI and USB PHY nodes in Perf1
  arm64: allwinner: a100: Add MMC related nodes
  arm64: dts: allwinner: a100: perf1: Add eMMC and MMC node

 .../allwinner,sun50i-h6-operating-points.yaml |   1 +
 .../phy/allwinner,sun50i-a64-usb-phy.yaml     |  10 +-
 .../usb/allwinner,sun4i-a10-musb.yaml         |   1 +
 .../devicetree/bindings/usb/generic-ehci.yaml |   1 +
 .../devicetree/bindings/usb/generic-ohci.yaml |   1 +
 .../allwinner/sun50i-a100-allwinner-perf1.dts |  60 ++++++
 .../dts/allwinner/sun50i-a100-cpu-opp.dtsi    |  90 ++++++++
 .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 193 +++++++++++++++++-
 drivers/clk/sunxi-ng/ccu-sun50i-a100.c        |   6 +-
 drivers/cpufreq/cpufreq-dt-platdev.c          |   1 +
 drivers/cpufreq/sun50i-cpufreq-nvmem.c        |  28 +++
 11 files changed, 383 insertions(+), 9 deletions(-)
 create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi


base-commit: 0fc810ae3ae110f9e2fcccce80fc8c8d62f97907
-- 
2.47.0

[PATCH v2 01/13] arm64: dts: allwinner: A100: Add PMU mode

[Cody Eksal]

From: Yangtao Li <frank@allwinnertech.com>

Add the Performance Monitoring Unit (PMU) device tree node to the A100
.dtsi, which tells DT users which interrupts are triggered by PMU overflow
events on each core.

Signed-off-by: Yangtao Li <frank@allwinnertech.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index a3dccf193765..1eca7c220ede 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -25,21 +25,21 @@ cpu0: cpu@0 {
 			enable-method = "psci";
 		};
 
-		cpu@1 {
+		cpu1: cpu@1 {
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			reg = <0x1>;
 			enable-method = "psci";
 		};
 
-		cpu@2 {
+		cpu2: cpu@2 {
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			reg = <0x2>;
 			enable-method = "psci";
 		};
 
-		cpu@3 {
+		cpu3: cpu@3 {
 			compatible = "arm,cortex-a53";
 			device_type = "cpu";
 			reg = <0x3>;
@@ -47,6 +47,15 @@ cpu@3 {
 		};
 	};
 
+	pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
 	psci {
 		compatible = "arm,psci-1.0";
 		method = "smc";
-- 
2.47.0

[PATCH v2 02/13] arm64: dts: allwinner: a100: add watchdog node

[Cody Eksal]

From: Yangtao Li <frank@allwinnertech.com>

Declare A100's watchdog in the device-tree.

Signed-off-by: Yangtao Li <frank@allwinnertech.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index 1eca7c220ede..adb11b26045f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -144,6 +144,14 @@ ths_calibration: calib@14 {
 			};
 		};
 
+		watchdog@30090a0 {
+			compatible = "allwinner,sun50i-a100-wdt",
+				     "allwinner,sun6i-a31-wdt";
+			reg = <0x030090a0 0x20>;
+			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&dcxo24M>;
+		};
+
 		pio: pinctrl@300b000 {
 			compatible = "allwinner,sun50i-a100-pinctrl";
 			reg = <0x0300b000 0x400>;
-- 
2.47.0

[PATCH v2 03/13] dt-bindings: phy: sun50i-a64: add a100 compatible

[Cody Eksal]

The USB PHY found in the A100 is similar to that found in the D1. Add a
compatible for the A100.

Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
---
Changes in V2:
 - Update binding to allow using the D1 as a compatible.

 .../bindings/phy/allwinner,sun50i-a64-usb-phy.yaml     | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml
index f557feca9763..21209126ed00 100644
--- a/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml
@@ -15,9 +15,13 @@ properties:
     const: 1
 
   compatible:
-    enum:
-      - allwinner,sun20i-d1-usb-phy
-      - allwinner,sun50i-a64-usb-phy
+    oneOf:
+      - enum:
+          - allwinner,sun20i-d1-usb-phy
+          - allwinner,sun50i-a64-usb-phy
+      - items:
+          - const: allwinner,sun50i-a100-usb-phy
+          - const: allwinner,sun20i-d1-usb-phy
 
   reg:
     items:
-- 
2.47.0

[PATCH v2 05/13] dt-bindings: usb: sunxi-musb: Add A100 compatible string

[Cody Eksal]

The A100 MUSB peripheral has 10 endpoints, and thus is compatible with
the A33 version.

Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
Changes in V2:
 - Fix ordering of compatibles

 .../devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml        | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
index f972ce976e86..bb5010dcefe1 100644
--- a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
+++ b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
@@ -23,6 +23,7 @@ properties:
           - enum:
               - allwinner,sun8i-a83t-musb
               - allwinner,sun20i-d1-musb
+              - allwinner,sun50i-a100-musb
               - allwinner,sun50i-h6-musb
           - const: allwinner,sun8i-a33-musb
       - items:
-- 
2.47.0

[PATCH v2 06/13] arm64: dts: allwinner: a100: add usb related nodes

[Cody Eksal]

From: Yangtao Li <frank@allwinnertech.com>

The Allwinner A100 has two HCI USB controllers, a OTG controller and a
USB PHY. The PHY is compatible with that used by the D1, while the OTG
controller is compatible with the A33. Add nodes for these to the base
DTSI.

Signed-off-by: Yangtao Li <frank@allwinnertech.com>
[masterr3c0rd@epochal.quest: fallback to a33-musb and d1-usb-phy, edited message]
Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
Changes in V2:
 - Fix sizes of reg definitions in usbphy
 - Move #phy-cells to the end of usbphy
 - Order nodes by MMIO address
 - Remove dr_mode

 .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 91 +++++++++++++++++++
 1 file changed, 91 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index adb11b26045f..f6162a107641 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -302,6 +302,97 @@ ths: thermal-sensor@5070400 {
 			#thermal-sensor-cells = <1>;
 		};
 
+		usb_otg: usb@5100000 {
+			compatible = "allwinner,sun50i-a100-musb",
+				     "allwinner,sun8i-a33-musb";
+			reg = <0x05100000 0x0400>;
+			clocks = <&ccu CLK_BUS_OTG>;
+			resets = <&ccu RST_BUS_OTG>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "mc";
+			phys = <&usbphy 0>;
+			phy-names = "usb";
+			extcon = <&usbphy 0>;
+			status = "disabled";
+		};
+
+		usbphy: phy@5100400 {
+			compatible = "allwinner,sun50i-a100-usb-phy",
+				     "allwinner,sun20i-d1-usb-phy";
+			reg = <0x05100400 0x100>,
+			      <0x05101800 0x100>,
+			      <0x05200800 0x100>;
+			reg-names = "phy_ctrl",
+				    "pmu0",
+				    "pmu1";
+			clocks = <&ccu CLK_USB_PHY0>,
+				 <&ccu CLK_USB_PHY1>;
+			clock-names = "usb0_phy",
+				      "usb1_phy";
+			resets = <&ccu RST_USB_PHY0>,
+				 <&ccu RST_USB_PHY1>;
+			reset-names = "usb0_reset",
+				      "usb1_reset";
+			status = "disabled";
+			#phy-cells = <1>;
+		};
+
+		ehci0: usb@5101000 {
+			compatible = "allwinner,sun50i-a100-ehci",
+				     "generic-ehci";
+			reg = <0x05101000 0x100>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI0>,
+				 <&ccu CLK_BUS_EHCI0>,
+				 <&ccu CLK_USB_OHCI0>;
+			resets = <&ccu RST_BUS_OHCI0>,
+				 <&ccu RST_BUS_EHCI0>;
+			phys = <&usbphy 0>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ohci0: usb@5101400 {
+			compatible = "allwinner,sun50i-a100-ohci",
+				     "generic-ohci";
+			reg = <0x05101400 0x100>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI0>,
+				 <&ccu CLK_USB_OHCI0>;
+			resets = <&ccu RST_BUS_OHCI0>;
+			phys = <&usbphy 0>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ehci1: usb@5200000 {
+			compatible = "allwinner,sun50i-a100-ehci",
+				     "generic-ehci";
+			reg = <0x05200000 0x100>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI1>,
+				 <&ccu CLK_BUS_EHCI1>,
+				 <&ccu CLK_USB_OHCI1>;
+			resets = <&ccu RST_BUS_OHCI1>,
+				 <&ccu RST_BUS_EHCI1>;
+			phys = <&usbphy 1>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ohci1: usb@5200400 {
+			compatible = "allwinner,sun50i-a100-ohci",
+				     "generic-ohci";
+			reg = <0x05200400 0x100>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI1>,
+				 <&ccu CLK_USB_OHCI1>;
+			resets = <&ccu RST_BUS_OHCI1>;
+			phys = <&usbphy 1>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
 		r_ccu: clock@7010000 {
 			compatible = "allwinner,sun50i-a100-r-ccu";
 			reg = <0x07010000 0x300>;
-- 
2.47.0

[PATCH v2 07/13] arm64: allwinner: A100: enable EHCI, OHCI and USB PHY nodes in Perf1

[Cody Eksal]

From: Yangtao Li <frank@allwinnertech.com>

Add USB support on A100 perf1 board, which include two USB2.0 port.

Signed-off-by: Yangtao Li <frank@allwinnertech.com>
Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
Changes in V2:
 - Add dr_mode here, instead of in the .dtsi

 .../allwinner/sun50i-a100-allwinner-perf1.dts | 39 +++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
index f5c5c1464482..2f8c7ee60283 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
@@ -7,6 +7,8 @@
 
 #include "sun50i-a100.dtsi"
 
+#include <dt-bindings/gpio/gpio.h>
+
 /{
 	model = "Allwinner A100 Perf1";
 	compatible = "allwinner,a100-perf1", "allwinner,sun50i-a100";
@@ -18,6 +20,36 @@ aliases {
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	reg_usb1_vbus: usb1-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb1-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
+		enable-active-high;
+	};
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&ohci0 {
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
 };
 
 &pio {
@@ -178,3 +210,10 @@ &uart0 {
 	pinctrl-0 = <&uart0_pb_pins>;
 	status = "okay";
 };
+
+&usbphy {
+	usb0_id_det-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
+	usb0_vbus-supply = <&reg_drivevbus>;
+	usb1_vbus-supply = <&reg_usb1_vbus>;
+	status = "okay";
+};
-- 
2.47.0

[PATCH v2 08/13] clk: sunxi-ng: a100: enable MMC clock reparenting

[Cody Eksal]

During testing, it was noted that MMC would fail to initialize, with
"mmc: fatal err update clk timeout" being printed in the log. It was
found that CLK_SET_RATE_NO_REPARENT was set on the MMC controllers, and
that removing this allows MMC to initialize. Therefore, remove
CLK_SET_RATE_NO_REPARENT from mmc0/1/2.

Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
 drivers/clk/sunxi-ng/ccu-sun50i-a100.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a100.c b/drivers/clk/sunxi-ng/ccu-sun50i-a100.c
index bbaa82978716..a59e420b195d 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a100.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a100.c
@@ -436,7 +436,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830,
 					  24, 2,	/* mux */
 					  BIT(31),	/* gate */
 					  2,		/* post-div */
-					  CLK_SET_RATE_NO_REPARENT);
+					  0);
 
 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834,
 					  0, 4,		/* M */
@@ -444,7 +444,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834,
 					  24, 2,	/* mux */
 					  BIT(31),	/* gate */
 					  2,		/* post-div */
-					  CLK_SET_RATE_NO_REPARENT);
+					  0);
 
 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838,
 					  0, 4,		/* M */
@@ -452,7 +452,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838,
 					  24, 2,	/* mux */
 					  BIT(31),	/* gate */
 					  2,		/* post-div */
-					  CLK_SET_RATE_NO_REPARENT);
+					  0);
 
 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0);
 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0);
-- 
2.47.0

[PATCH v2 09/13] arm64: allwinner: a100: Add MMC related nodes

[Cody Eksal]

From: Yangtao Li <frank@allwinnertech.com>

The A100 has 3 MMC controllers, one of them being especially targeted to
eMMC. Let's add nodes on dts.

Signed-off-by: Yangtao Li <frank@allwinnertech.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
 .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 71 +++++++++++++++++++
 1 file changed, 71 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index f6162a107641..29ac7716c7a5 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -169,12 +169,83 @@ pio: pinctrl@300b000 {
 			interrupt-controller;
 			#interrupt-cells = <3>;
 
+			mmc0_pins: mmc0-pins {
+				pins = "PF0", "PF1", "PF2", "PF3",
+				       "PF4", "PF5";
+				function = "mmc0";
+				drive-strength = <30>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/
+			mmc1_pins: mmc1-pins {
+				pins = "PG0", "PG1", "PG2", "PG3",
+				       "PG4", "PG5";
+				function = "mmc1";
+				drive-strength = <30>;
+				bias-pull-up;
+			};
+
+			mmc2_pins: mmc2-pins {
+				pins = "PC0", "PC1", "PC5", "PC6",
+				       "PC8", "PC9", "PC10", "PC11",
+				       "PC13", "PC14", "PC15", "PC16";
+				function = "mmc2";
+				drive-strength = <30>;
+				bias-pull-up;
+			};
+
 			uart0_pb_pins: uart0-pb-pins {
 				pins = "PB9", "PB10";
 				function = "uart0";
 			};
 		};
 
+		mmc0: mmc@4020000 {
+			compatible = "allwinner,sun50i-a100-mmc";
+			reg = <0x04020000 0x1000>;
+			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC0>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc0_pins>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc1: mmc@4021000 {
+			compatible = "allwinner,sun50i-a100-mmc";
+			reg = <0x04021000 0x1000>;
+			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC1>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc1_pins>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc2: mmc@4022000 {
+			compatible = "allwinner,sun50i-a100-emmc";
+			reg = <0x04022000 0x1000>;
+			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+			clock-names = "ahb", "mmc";
+			resets = <&ccu RST_BUS_MMC2>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc2_pins>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		uart0: serial@5000000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x05000000 0x400>;
-- 
2.47.0

[PATCH v2 10/13] arm64: dts: allwinner: a100: perf1: Add eMMC and MMC node

[Cody Eksal]

From: Yangtao Li <frank@allwinnertech.com>

A100 perf1 hava MicroSD slot and on-board eMMC module, add support for them.

Signed-off-by: Yangtao Li <frank@allwinnertech.com>
Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
 .../allwinner/sun50i-a100-allwinner-perf1.dts    | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
index 2f8c7ee60283..d418fc272b3c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
@@ -39,6 +39,22 @@ &ehci1 {
 	status = "okay";
 };
 
+&mmc0 {
+	vmmc-supply = <&reg_dcdc1>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+	bus-width = <4>;
+	status = "okay";
+};
+
+&mmc2 {
+	vmmc-supply = <&reg_dcdc1>;
+	vqmmc-supply = <&reg_aldo1>;
+	cap-mmc-hw-reset;
+	non-removable;
+	bus-width = <8>;
+	status = "okay";
+};
+
 &ohci0 {
 	status = "okay";
 };
-- 
2.47.0

[PATCH v2 11/13] dt-bindings: opp: h6: Add A100 operating points

[Cody Eksal]

The A100, similar to the H6 and H616, use an NVMEM value to determine
speed binnings. The method used is similar to that of the H6. However,
the information is stored at a slightly different bit offset.

Add a new compatible for the A100.

Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
Changes in V2:
 - Fix ordering of compatibles

 .../bindings/opp/allwinner,sun50i-h6-operating-points.yaml       | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
index ec5e424bb3c8..75ab552f6ecd 100644
--- a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
+++ b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
@@ -22,6 +22,7 @@ allOf:
 properties:
   compatible:
     enum:
+      - allwinner,sun50i-a100-operating-points
       - allwinner,sun50i-h6-operating-points
       - allwinner,sun50i-h616-operating-points
 
-- 
2.47.0

[PATCH v2 12/13] cpufreq: sun50i: add a100 cpufreq support

[Cody Eksal]

From: Shuosheng Huang <huangshuosheng@allwinnertech.com>

Let's add cpufreq nvmem based for allwinner a100 soc. It's similar to h6,
let us use efuse_xlate to extract the differentiated part.

Signed-off-by: Shuosheng Huang <huangshuosheng@allwinnertech.com>
[masterr3c0rd@epochal.quest: add A100 to opp_match_list]
Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
Changes in V2:
 - Add the A100 to the cpufreq-dt-platdev blacklist.

 drivers/cpufreq/cpufreq-dt-platdev.c   |  1 +
 drivers/cpufreq/sun50i-cpufreq-nvmem.c | 28 ++++++++++++++++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 18942bfe9c95..2a3e8bd317c9 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -103,6 +103,7 @@ static const struct of_device_id allowlist[] __initconst = {
  * platforms using "operating-points-v2" property.
  */
 static const struct of_device_id blocklist[] __initconst = {
+	{ .compatible = "allwinner,sun50i-a100" },
 	{ .compatible = "allwinner,sun50i-h6", },
 	{ .compatible = "allwinner,sun50i-h616", },
 	{ .compatible = "allwinner,sun50i-h618", },
diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
index 293921acec93..3a29c026d364 100644
--- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
+++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
@@ -22,6 +22,9 @@
 #define NVMEM_MASK	0x7
 #define NVMEM_SHIFT	5
 
+#define SUN50I_A100_NVMEM_MASK	0xf
+#define SUN50I_A100_NVMEM_SHIFT	12
+
 static struct platform_device *cpufreq_dt_pdev, *sun50i_cpufreq_pdev;
 
 struct sunxi_cpufreq_data {
@@ -45,6 +48,23 @@ static u32 sun50i_h6_efuse_xlate(u32 speedbin)
 		return 0;
 }
 
+static u32 sun50i_a100_efuse_xlate(u32 speedbin)
+{
+	u32 efuse_value;
+
+	efuse_value = (speedbin >> SUN50I_A100_NVMEM_SHIFT) &
+		      SUN50I_A100_NVMEM_MASK;
+
+	switch (efuse_value) {
+	case 0b100:
+		return 2;
+	case 0b010:
+		return 1;
+	default:
+		return 0;
+	}
+}
+
 static int get_soc_id_revision(void)
 {
 #ifdef CONFIG_HAVE_ARM_SMCCC_DISCOVERY
@@ -108,6 +128,10 @@ static struct sunxi_cpufreq_data sun50i_h6_cpufreq_data = {
 	.efuse_xlate = sun50i_h6_efuse_xlate,
 };
 
+static struct sunxi_cpufreq_data sun50i_a100_cpufreq_data = {
+	.efuse_xlate = sun50i_a100_efuse_xlate,
+};
+
 static struct sunxi_cpufreq_data sun50i_h616_cpufreq_data = {
 	.efuse_xlate = sun50i_h616_efuse_xlate,
 };
@@ -116,6 +140,9 @@ static const struct of_device_id cpu_opp_match_list[] = {
 	{ .compatible = "allwinner,sun50i-h6-operating-points",
 	  .data = &sun50i_h6_cpufreq_data,
 	},
+	{ .compatible = "allwinner,sun50i-a100-operating-points",
+	  .data = &sun50i_a100_cpufreq_data,
+	},
 	{ .compatible = "allwinner,sun50i-h616-operating-points",
 	  .data = &sun50i_h616_cpufreq_data,
 	},
@@ -291,6 +318,7 @@ static struct platform_driver sun50i_cpufreq_driver = {
 
 static const struct of_device_id sun50i_cpufreq_match_list[] = {
 	{ .compatible = "allwinner,sun50i-h6" },
+	{ .compatible = "allwinner,sun50i-a100" },
 	{ .compatible = "allwinner,sun50i-h616" },
 	{ .compatible = "allwinner,sun50i-h618" },
 	{ .compatible = "allwinner,sun50i-h700" },
-- 
2.47.0

[PATCH v2 13/13] arm64: dts: allwinner: a100: Add CPU Operating Performance Points table

[Cody Eksal]

From: Shuosheng Huang <huangshuosheng@allwinnertech.com>

Add an Operating Performance Points table for the CPU cores to
enable Dynamic Voltage & Frequency Scaling on the A100.

Signed-off-by: Shuosheng Huang <huangshuosheng@allwinnertech.com>
[masterr3c0rd@epochal.quest: fix typos in -cpu-opp, use compatible]
Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
---
Changes in V2:
 - Rename cpu-opp-table to opp-table-cpu
 - Use single cell version of opp-microvolt-speedX

 .../allwinner/sun50i-a100-allwinner-perf1.dts |  5 ++
 .../dts/allwinner/sun50i-a100-cpu-opp.dtsi    | 90 +++++++++++++++++++
 .../arm64/boot/dts/allwinner/sun50i-a100.dtsi |  8 ++
 3 files changed, 103 insertions(+)
 create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
index d418fc272b3c..1fb629df9f1d 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include "sun50i-a100.dtsi"
+#include "sun50i-a100-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
@@ -68,6 +69,10 @@ &usb_otg {
 	status = "okay";
 };
 
+&cpu0 {
+	cpu-supply = <&reg_dcdc2>;
+};
+
 &pio {
 	vcc-pb-supply = <&reg_dcdc1>;
 	vcc-pc-supply = <&reg_eldo1>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
new file mode 100644
index 000000000000..c6a2efa037dc
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-cpu-opp.dtsi
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
+// Copyright (c) 2020 ShuoSheng Huang <huangshuosheng@allwinnertech.com>
+
+/ {
+	cpu_opp_table: opp-table-cpu {
+		compatible = "allwinner,sun50i-a100-operating-points";
+		nvmem-cells = <&cpu_speed_grade>;
+		opp-shared;
+
+		opp-408000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <408000000>;
+
+			opp-microvolt-speed0 = <900000>;
+			opp-microvolt-speed1 = <900000>;
+			opp-microvolt-speed2 = <900000>;
+		};
+
+		opp-600000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <600000000>;
+
+			opp-microvolt-speed0 = <900000>;
+			opp-microvolt-speed1 = <900000>;
+			opp-microvolt-speed2 = <900000>;
+		};
+
+		opp-816000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <816000000>;
+
+			opp-microvolt-speed0 = <940000>;
+			opp-microvolt-speed1 = <900000>;
+			opp-microvolt-speed2 = <900000>;
+		};
+
+		opp-1080000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <1080000000>;
+
+			opp-microvolt-speed0 = <1020000>;
+			opp-microvolt-speed1 = <980000>;
+			opp-microvolt-speed2 = <950000>;
+		};
+
+		opp-1200000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <1200000000>;
+
+			opp-microvolt-speed0 = <1100000>;
+			opp-microvolt-speed1 = <1020000>;
+			opp-microvolt-speed2 = <1000000>;
+		};
+
+		opp-1320000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <1320000000>;
+
+			opp-microvolt-speed0 = <1160000>;
+			opp-microvolt-speed1 = <1060000>;
+			opp-microvolt-speed2 = <1030000>;
+		};
+
+		opp-1464000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <1464000000>;
+
+			opp-microvolt-speed0 = <1180000>;
+			opp-microvolt-speed1 = <1180000>;
+			opp-microvolt-speed2 = <1130000>;
+		};
+	};
+};
+
+&cpu0 {
+	operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu1 {
+	operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu2 {
+	operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu3 {
+	operating-points-v2 = <&cpu_opp_table>;
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index 29ac7716c7a5..6a76858b654a 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -23,6 +23,7 @@ cpu0: cpu@0 {
 			device_type = "cpu";
 			reg = <0x0>;
 			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
 		};
 
 		cpu1: cpu@1 {
@@ -30,6 +31,7 @@ cpu1: cpu@1 {
 			device_type = "cpu";
 			reg = <0x1>;
 			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
 		};
 
 		cpu2: cpu@2 {
@@ -37,6 +39,7 @@ cpu2: cpu@2 {
 			device_type = "cpu";
 			reg = <0x2>;
 			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
 		};
 
 		cpu3: cpu@3 {
@@ -44,6 +47,7 @@ cpu3: cpu@3 {
 			device_type = "cpu";
 			reg = <0x3>;
 			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
 		};
 	};
 
@@ -142,6 +146,10 @@ efuse@3006000 {
 			ths_calibration: calib@14 {
 				reg = <0x14 8>;
 			};
+
+			cpu_speed_grade: cpu-speed-grade@1c {
+				reg = <0x1c 0x2>;
+			};
 		};
 
 		watchdog@30090a0 {
-- 
2.47.0

Re: [PATCH v2 11/13] dt-bindings: opp: h6: Add A100 operating points

[Krzysztof Kozlowski]

On Thu, Oct 31, 2024 at 04:02:24AM -0300, Cody Eksal wrote:
> The A100, similar to the H6 and H616, use an NVMEM value to determine
> speed binnings. The method used is similar to that of the H6. However,
> the information is stored at a slightly different bit offset.
> 
> Add a new compatible for the A100.
> 
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
> ---
> Changes in V2:
>  - Fix ordering of compatibles

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v2 05/13] dt-bindings: usb: sunxi-musb: Add A100 compatible string

[Krzysztof Kozlowski]

On Thu, Oct 31, 2024 at 04:02:18AM -0300, Cody Eksal wrote:
> The A100 MUSB peripheral has 10 endpoints, and thus is compatible with
> the A33 version.
> 
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v2 03/13] dt-bindings: phy: sun50i-a64: add a100 compatible

[Andre Przywara]

On Thu, 31 Oct 2024 04:02:16 -0300
Cody Eksal <masterr3c0rd@epochal.quest> wrote:

> The USB PHY found in the A100 is similar to that found in the D1. Add a
> compatible for the A100.
> 
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

> Acked-by: Rob Herring (Arm) <robh@kernel.org>

Careful with that: you made quite some changes compared to v1, which Rob
ACKed, so I wouldn't carry over his tag here.

Cheers,
Andre

> ---
> Changes in V2:
>  - Update binding to allow using the D1 as a compatible.
> 
>  .../bindings/phy/allwinner,sun50i-a64-usb-phy.yaml     | 10 +++++++---
>  1 file changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml
> index f557feca9763..21209126ed00 100644
> --- a/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml
> @@ -15,9 +15,13 @@ properties:
>      const: 1
>  
>    compatible:
> -    enum:
> -      - allwinner,sun20i-d1-usb-phy
> -      - allwinner,sun50i-a64-usb-phy
> +    oneOf:
> +      - enum:
> +          - allwinner,sun20i-d1-usb-phy
> +          - allwinner,sun50i-a64-usb-phy
> +      - items:
> +          - const: allwinner,sun50i-a100-usb-phy
> +          - const: allwinner,sun20i-d1-usb-phy
>  
>    reg:
>      items:

Re: [PATCH v2 06/13] arm64: dts: allwinner: a100: add usb related nodes

[Andre Przywara]

On Thu, 31 Oct 2024 04:02:19 -0300
Cody Eksal <masterr3c0rd@epochal.quest> wrote:

> From: Yangtao Li <frank@allwinnertech.com>
> 
> The Allwinner A100 has two HCI USB controllers, a OTG controller and a
> USB PHY. The PHY is compatible with that used by the D1, while the OTG
> controller is compatible with the A33. Add nodes for these to the base
> DTSI.
> 
> Signed-off-by: Yangtao Li <frank@allwinnertech.com>
> [masterr3c0rd@epochal.quest: fallback to a33-musb and d1-usb-phy, edited message]
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>

Thanks for the changes, looks good to me now.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
> Changes in V2:
>  - Fix sizes of reg definitions in usbphy
>  - Move #phy-cells to the end of usbphy
>  - Order nodes by MMIO address
>  - Remove dr_mode
> 
>  .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 91 +++++++++++++++++++
>  1 file changed, 91 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> index adb11b26045f..f6162a107641 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> @@ -302,6 +302,97 @@ ths: thermal-sensor@5070400 {
>  			#thermal-sensor-cells = <1>;
>  		};
>  
> +		usb_otg: usb@5100000 {
> +			compatible = "allwinner,sun50i-a100-musb",
> +				     "allwinner,sun8i-a33-musb";
> +			reg = <0x05100000 0x0400>;
> +			clocks = <&ccu CLK_BUS_OTG>;
> +			resets = <&ccu RST_BUS_OTG>;
> +			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "mc";
> +			phys = <&usbphy 0>;
> +			phy-names = "usb";
> +			extcon = <&usbphy 0>;
> +			status = "disabled";
> +		};
> +
> +		usbphy: phy@5100400 {
> +			compatible = "allwinner,sun50i-a100-usb-phy",
> +				     "allwinner,sun20i-d1-usb-phy";
> +			reg = <0x05100400 0x100>,
> +			      <0x05101800 0x100>,
> +			      <0x05200800 0x100>;
> +			reg-names = "phy_ctrl",
> +				    "pmu0",
> +				    "pmu1";
> +			clocks = <&ccu CLK_USB_PHY0>,
> +				 <&ccu CLK_USB_PHY1>;
> +			clock-names = "usb0_phy",
> +				      "usb1_phy";
> +			resets = <&ccu RST_USB_PHY0>,
> +				 <&ccu RST_USB_PHY1>;
> +			reset-names = "usb0_reset",
> +				      "usb1_reset";
> +			status = "disabled";
> +			#phy-cells = <1>;
> +		};
> +
> +		ehci0: usb@5101000 {
> +			compatible = "allwinner,sun50i-a100-ehci",
> +				     "generic-ehci";
> +			reg = <0x05101000 0x100>;
> +			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_OHCI0>,
> +				 <&ccu CLK_BUS_EHCI0>,
> +				 <&ccu CLK_USB_OHCI0>;
> +			resets = <&ccu RST_BUS_OHCI0>,
> +				 <&ccu RST_BUS_EHCI0>;
> +			phys = <&usbphy 0>;
> +			phy-names = "usb";
> +			status = "disabled";
> +		};
> +
> +		ohci0: usb@5101400 {
> +			compatible = "allwinner,sun50i-a100-ohci",
> +				     "generic-ohci";
> +			reg = <0x05101400 0x100>;
> +			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_OHCI0>,
> +				 <&ccu CLK_USB_OHCI0>;
> +			resets = <&ccu RST_BUS_OHCI0>;
> +			phys = <&usbphy 0>;
> +			phy-names = "usb";
> +			status = "disabled";
> +		};
> +
> +		ehci1: usb@5200000 {
> +			compatible = "allwinner,sun50i-a100-ehci",
> +				     "generic-ehci";
> +			reg = <0x05200000 0x100>;
> +			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_OHCI1>,
> +				 <&ccu CLK_BUS_EHCI1>,
> +				 <&ccu CLK_USB_OHCI1>;
> +			resets = <&ccu RST_BUS_OHCI1>,
> +				 <&ccu RST_BUS_EHCI1>;
> +			phys = <&usbphy 1>;
> +			phy-names = "usb";
> +			status = "disabled";
> +		};
> +
> +		ohci1: usb@5200400 {
> +			compatible = "allwinner,sun50i-a100-ohci",
> +				     "generic-ohci";
> +			reg = <0x05200400 0x100>;
> +			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_OHCI1>,
> +				 <&ccu CLK_USB_OHCI1>;
> +			resets = <&ccu RST_BUS_OHCI1>;
> +			phys = <&usbphy 1>;
> +			phy-names = "usb";
> +			status = "disabled";
> +		};
> +
>  		r_ccu: clock@7010000 {
>  			compatible = "allwinner,sun50i-a100-r-ccu";
>  			reg = <0x07010000 0x300>;

Re: [PATCH v2 08/13] clk: sunxi-ng: a100: enable MMC clock reparenting

[Andre Przywara]

On Thu, 31 Oct 2024 04:02:21 -0300
Cody Eksal <masterr3c0rd@epochal.quest> wrote:

> During testing, it was noted that MMC would fail to initialize, with
> "mmc: fatal err update clk timeout" being printed in the log. It was
> found that CLK_SET_RATE_NO_REPARENT was set on the MMC controllers, and
> that removing this allows MMC to initialize. Therefore, remove
> CLK_SET_RATE_NO_REPARENT from mmc0/1/2.

Well, while this change indeed prevented that error message you mentioned,
but the SD card still doesn't work for me: it probes and I can mount a
filesystem on it, but then it hangs, for instance when running an "ls" on
it. It could be my setup (lacking DT or device issue or missing kernel
config), though, and the eMMC works for me this way, but it would be good
to have that sorted. 

Also it would be good to know why CLK_SET_RATE_NO_REPARENT was put there
in the first place: I don't see it in any other MMC clocks in sunxi-ng, so
it wasn't just copied&pasted.
So was there a problem that this flag was supposed to fix? Is that
something that only applied to older kernels (back when the MMC patches
were first posted), and which has now been fixed/changed elsewhere?

I feel a bit uneasy of just removing this just because it works(TM),
especially if it doesn't really (SD card for me, for instance).

Cheers,
Andre

> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
> ---
>  drivers/clk/sunxi-ng/ccu-sun50i-a100.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a100.c b/drivers/clk/sunxi-ng/ccu-sun50i-a100.c
> index bbaa82978716..a59e420b195d 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun50i-a100.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a100.c
> @@ -436,7 +436,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830,
>  					  24, 2,	/* mux */
>  					  BIT(31),	/* gate */
>  					  2,		/* post-div */
> -					  CLK_SET_RATE_NO_REPARENT);
> +					  0);
>  
>  static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834,
>  					  0, 4,		/* M */
> @@ -444,7 +444,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834,
>  					  24, 2,	/* mux */
>  					  BIT(31),	/* gate */
>  					  2,		/* post-div */
> -					  CLK_SET_RATE_NO_REPARENT);
> +					  0);
>  
>  static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838,
>  					  0, 4,		/* M */
> @@ -452,7 +452,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838,
>  					  24, 2,	/* mux */
>  					  BIT(31),	/* gate */
>  					  2,		/* post-div */
> -					  CLK_SET_RATE_NO_REPARENT);
> +					  0);
>  
>  static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0);
>  static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0);

Re: [PATCH v2 11/13] dt-bindings: opp: h6: Add A100 operating points

[Andre Przywara]

On Thu, 31 Oct 2024 04:02:24 -0300
Cody Eksal <masterr3c0rd@epochal.quest> wrote:

> The A100, similar to the H6 and H616, use an NVMEM value to determine
> speed binnings. The method used is similar to that of the H6. However,
> the information is stored at a slightly different bit offset.
> 
> Add a new compatible for the A100.
> 
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> ---
> Changes in V2:
>  - Fix ordering of compatibles
> 
>  .../bindings/opp/allwinner,sun50i-h6-operating-points.yaml       | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
> index ec5e424bb3c8..75ab552f6ecd 100644
> --- a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
> +++ b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
> @@ -22,6 +22,7 @@ allOf:
>  properties:
>    compatible:
>      enum:
> +      - allwinner,sun50i-a100-operating-points
>        - allwinner,sun50i-h6-operating-points
>        - allwinner,sun50i-h616-operating-points
>  

Re: [PATCH v2 12/13] cpufreq: sun50i: add a100 cpufreq support

[Andre Przywara]

On Thu, 31 Oct 2024 04:02:25 -0300
Cody Eksal <masterr3c0rd@epochal.quest> wrote:

> From: Shuosheng Huang <huangshuosheng@allwinnertech.com>
> 
> Let's add cpufreq nvmem based for allwinner a100 soc. It's similar to h6,
> let us use efuse_xlate to extract the differentiated part.
> 
> Signed-off-by: Shuosheng Huang <huangshuosheng@allwinnertech.com>
> [masterr3c0rd@epochal.quest: add A100 to opp_match_list]
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>

Looks good to me, and seems to work on my Teclast P80 tablet, so:

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>

Thanks,
Andre

> ---
> Changes in V2:
>  - Add the A100 to the cpufreq-dt-platdev blacklist.
> 
>  drivers/cpufreq/cpufreq-dt-platdev.c   |  1 +
>  drivers/cpufreq/sun50i-cpufreq-nvmem.c | 28 ++++++++++++++++++++++++++
>  2 files changed, 29 insertions(+)
> 
> diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
> index 18942bfe9c95..2a3e8bd317c9 100644
> --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> @@ -103,6 +103,7 @@ static const struct of_device_id allowlist[] __initconst = {
>   * platforms using "operating-points-v2" property.
>   */
>  static const struct of_device_id blocklist[] __initconst = {
> +	{ .compatible = "allwinner,sun50i-a100" },
>  	{ .compatible = "allwinner,sun50i-h6", },
>  	{ .compatible = "allwinner,sun50i-h616", },
>  	{ .compatible = "allwinner,sun50i-h618", },
> diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
> index 293921acec93..3a29c026d364 100644
> --- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
> +++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
> @@ -22,6 +22,9 @@
>  #define NVMEM_MASK	0x7
>  #define NVMEM_SHIFT	5
>  
> +#define SUN50I_A100_NVMEM_MASK	0xf
> +#define SUN50I_A100_NVMEM_SHIFT	12
> +
>  static struct platform_device *cpufreq_dt_pdev, *sun50i_cpufreq_pdev;
>  
>  struct sunxi_cpufreq_data {
> @@ -45,6 +48,23 @@ static u32 sun50i_h6_efuse_xlate(u32 speedbin)
>  		return 0;
>  }
>  
> +static u32 sun50i_a100_efuse_xlate(u32 speedbin)
> +{
> +	u32 efuse_value;
> +
> +	efuse_value = (speedbin >> SUN50I_A100_NVMEM_SHIFT) &
> +		      SUN50I_A100_NVMEM_MASK;
> +
> +	switch (efuse_value) {
> +	case 0b100:
> +		return 2;
> +	case 0b010:
> +		return 1;
> +	default:
> +		return 0;
> +	}
> +}
> +
>  static int get_soc_id_revision(void)
>  {
>  #ifdef CONFIG_HAVE_ARM_SMCCC_DISCOVERY
> @@ -108,6 +128,10 @@ static struct sunxi_cpufreq_data sun50i_h6_cpufreq_data = {
>  	.efuse_xlate = sun50i_h6_efuse_xlate,
>  };
>  
> +static struct sunxi_cpufreq_data sun50i_a100_cpufreq_data = {
> +	.efuse_xlate = sun50i_a100_efuse_xlate,
> +};
> +
>  static struct sunxi_cpufreq_data sun50i_h616_cpufreq_data = {
>  	.efuse_xlate = sun50i_h616_efuse_xlate,
>  };
> @@ -116,6 +140,9 @@ static const struct of_device_id cpu_opp_match_list[] = {
>  	{ .compatible = "allwinner,sun50i-h6-operating-points",
>  	  .data = &sun50i_h6_cpufreq_data,
>  	},
> +	{ .compatible = "allwinner,sun50i-a100-operating-points",
> +	  .data = &sun50i_a100_cpufreq_data,
> +	},
>  	{ .compatible = "allwinner,sun50i-h616-operating-points",
>  	  .data = &sun50i_h616_cpufreq_data,
>  	},
> @@ -291,6 +318,7 @@ static struct platform_driver sun50i_cpufreq_driver = {
>  
>  static const struct of_device_id sun50i_cpufreq_match_list[] = {
>  	{ .compatible = "allwinner,sun50i-h6" },
> +	{ .compatible = "allwinner,sun50i-a100" },
>  	{ .compatible = "allwinner,sun50i-h616" },
>  	{ .compatible = "allwinner,sun50i-h618" },
>  	{ .compatible = "allwinner,sun50i-h700" },

Re: [PATCH v2 02/13] arm64: dts: allwinner: a100: add watchdog node

[Parthiban]

On 10/31/24 12:32 PM, Cody Eksal wrote:
> From: Yangtao Li <frank@allwinnertech.com>
> 
> Declare A100's watchdog in the device-tree.
> 
> Signed-off-by: Yangtao Li <frank@allwinnertech.com>
> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
Tested-by: Parthiban Nallathambi <parthiban@linumiz.com>

Thanks,
Parthiban
> ---
>  arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> index 1eca7c220ede..adb11b26045f 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> @@ -144,6 +144,14 @@ ths_calibration: calib@14 {
>  			};
>  		};
>  
> +		watchdog@30090a0 {
> +			compatible = "allwinner,sun50i-a100-wdt",
> +				     "allwinner,sun6i-a31-wdt";
> +			reg = <0x030090a0 0x20>;
> +			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&dcxo24M>;
> +		};
> +
>  		pio: pinctrl@300b000 {
>  			compatible = "allwinner,sun50i-a100-pinctrl";
>  			reg = <0x0300b000 0x400>;

Re: [PATCH v2 12/13] cpufreq: sun50i: add a100 cpufreq support

[Parthiban]

On 10/31/24 12:32 PM, Cody Eksal wrote:
> From: Shuosheng Huang <huangshuosheng@allwinnertech.com>
> 
> Let's add cpufreq nvmem based for allwinner a100 soc. It's similar to h6,
> let us use efuse_xlate to extract the differentiated part.
> 
> Signed-off-by: Shuosheng Huang <huangshuosheng@allwinnertech.com>
> [masterr3c0rd@epochal.quest: add A100 to opp_match_list]
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>

Although I couldn't get the secondary CPU's running because of missing BL31 support,
it works fine in CPU0.

Tested-by: Parthiban Nallathambi <parthiban@linumiz.com>

Thanks,
Parthiban

> ---
> Changes in V2:
>  - Add the A100 to the cpufreq-dt-platdev blacklist.
> 
>  drivers/cpufreq/cpufreq-dt-platdev.c   |  1 +
>  drivers/cpufreq/sun50i-cpufreq-nvmem.c | 28 ++++++++++++++++++++++++++
>  2 files changed, 29 insertions(+)
> 
> diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
> index 18942bfe9c95..2a3e8bd317c9 100644
> --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> @@ -103,6 +103,7 @@ static const struct of_device_id allowlist[] __initconst = {
>   * platforms using "operating-points-v2" property.
>   */
>  static const struct of_device_id blocklist[] __initconst = {
> +	{ .compatible = "allwinner,sun50i-a100" },
>  	{ .compatible = "allwinner,sun50i-h6", },
>  	{ .compatible = "allwinner,sun50i-h616", },
>  	{ .compatible = "allwinner,sun50i-h618", },
> diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
> index 293921acec93..3a29c026d364 100644
> --- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
> +++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
> @@ -22,6 +22,9 @@
>  #define NVMEM_MASK	0x7
>  #define NVMEM_SHIFT	5
>  
> +#define SUN50I_A100_NVMEM_MASK	0xf
> +#define SUN50I_A100_NVMEM_SHIFT	12
> +
>  static struct platform_device *cpufreq_dt_pdev, *sun50i_cpufreq_pdev;
>  
>  struct sunxi_cpufreq_data {
> @@ -45,6 +48,23 @@ static u32 sun50i_h6_efuse_xlate(u32 speedbin)
>  		return 0;
>  }
>  
> +static u32 sun50i_a100_efuse_xlate(u32 speedbin)
> +{
> +	u32 efuse_value;
> +
> +	efuse_value = (speedbin >> SUN50I_A100_NVMEM_SHIFT) &
> +		      SUN50I_A100_NVMEM_MASK;
> +
> +	switch (efuse_value) {
> +	case 0b100:
> +		return 2;
> +	case 0b010:
> +		return 1;
> +	default:
> +		return 0;
> +	}
> +}
> +
>  static int get_soc_id_revision(void)
>  {
>  #ifdef CONFIG_HAVE_ARM_SMCCC_DISCOVERY
> @@ -108,6 +128,10 @@ static struct sunxi_cpufreq_data sun50i_h6_cpufreq_data = {
>  	.efuse_xlate = sun50i_h6_efuse_xlate,
>  };
>  
> +static struct sunxi_cpufreq_data sun50i_a100_cpufreq_data = {
> +	.efuse_xlate = sun50i_a100_efuse_xlate,
> +};
> +
>  static struct sunxi_cpufreq_data sun50i_h616_cpufreq_data = {
>  	.efuse_xlate = sun50i_h616_efuse_xlate,
>  };
> @@ -116,6 +140,9 @@ static const struct of_device_id cpu_opp_match_list[] = {
>  	{ .compatible = "allwinner,sun50i-h6-operating-points",
>  	  .data = &sun50i_h6_cpufreq_data,
>  	},
> +	{ .compatible = "allwinner,sun50i-a100-operating-points",
> +	  .data = &sun50i_a100_cpufreq_data,
> +	},
>  	{ .compatible = "allwinner,sun50i-h616-operating-points",
>  	  .data = &sun50i_h616_cpufreq_data,
>  	},
> @@ -291,6 +318,7 @@ static struct platform_driver sun50i_cpufreq_driver = {
>  
>  static const struct of_device_id sun50i_cpufreq_match_list[] = {
>  	{ .compatible = "allwinner,sun50i-h6" },
> +	{ .compatible = "allwinner,sun50i-a100" },
>  	{ .compatible = "allwinner,sun50i-h616" },
>  	{ .compatible = "allwinner,sun50i-h618" },
>  	{ .compatible = "allwinner,sun50i-h700" },

Re: [PATCH v2 03/13] dt-bindings: phy: sun50i-a64: add a100 compatible

[Cody Eksal]

On 2024/10/31 8:36 am, Andre Przywara wrote:
> On Thu, 31 Oct 2024 04:02:16 -0300
> Cody Eksal <masterr3c0rd@epochal.quest> wrote:
> 
>> The USB PHY found in the A100 is similar to that found in the D1. Add 
>> a
>> compatible for the A100.
>> 
>> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
> 
> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
> 
>> Acked-by: Rob Herring (Arm) <robh@kernel.org>
> 
> Careful with that: you made quite some changes compared to v1, which 
> Rob
> ACKed, so I wouldn't carry over his tag here.
I had made a note of this a few days ago, but it slipped through my 
pre-submission review. I'm terribly sorry; won't make this mistake in 
the future.

- Cody

> Cheers,
> Andre
> 
>> ---
>> Changes in V2:
>>  - Update binding to allow using the D1 as a compatible.
>> 
>>  .../bindings/phy/allwinner,sun50i-a64-usb-phy.yaml     | 10 
>> +++++++---
>>  1 file changed, 7 insertions(+), 3 deletions(-)
>> 
>> diff --git 
>> a/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml 
>> b/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml
>> index f557feca9763..21209126ed00 100644
>> --- 
>> a/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml
>> +++ 
>> b/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml
>> @@ -15,9 +15,13 @@ properties:
>>      const: 1
>> 
>>    compatible:
>> -    enum:
>> -      - allwinner,sun20i-d1-usb-phy
>> -      - allwinner,sun50i-a64-usb-phy
>> +    oneOf:
>> +      - enum:
>> +          - allwinner,sun20i-d1-usb-phy
>> +          - allwinner,sun50i-a64-usb-phy
>> +      - items:
>> +          - const: allwinner,sun50i-a100-usb-phy
>> +          - const: allwinner,sun20i-d1-usb-phy
>> 
>>    reg:
>>      items:

Re: [PATCH v2 06/13] arm64: dts: allwinner: a100: add usb related nodes

[Parthiban]

On 10/31/24 12:32 PM, Cody Eksal wrote:
> From: Yangtao Li <frank@allwinnertech.com>
> 
> The Allwinner A100 has two HCI USB controllers, a OTG controller and a
> USB PHY. The PHY is compatible with that used by the D1, while the OTG
> controller is compatible with the A33. Add nodes for these to the base
> DTSI.
> 
> Signed-off-by: Yangtao Li <frank@allwinnertech.com>
> [masterr3c0rd@epochal.quest: fallback to a33-musb and d1-usb-phy, edited message]
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
Peripheral mode works after disabling ehci0 and ohci0. Otherwise,

Tested-by: Parthiban Nallathambi <parthiban@linumiz.com>

Thanks,
Parthiban
> ---
> Changes in V2:
>  - Fix sizes of reg definitions in usbphy
>  - Move #phy-cells to the end of usbphy
>  - Order nodes by MMIO address
>  - Remove dr_mode
> 
>  .../arm64/boot/dts/allwinner/sun50i-a100.dtsi | 91 +++++++++++++++++++
>  1 file changed, 91 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> index adb11b26045f..f6162a107641 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> @@ -302,6 +302,97 @@ ths: thermal-sensor@5070400 {
>  			#thermal-sensor-cells = <1>;
>  		};
>  
> +		usb_otg: usb@5100000 {
> +			compatible = "allwinner,sun50i-a100-musb",
> +				     "allwinner,sun8i-a33-musb";
> +			reg = <0x05100000 0x0400>;
> +			clocks = <&ccu CLK_BUS_OTG>;
> +			resets = <&ccu RST_BUS_OTG>;
> +			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "mc";
> +			phys = <&usbphy 0>;
> +			phy-names = "usb";
> +			extcon = <&usbphy 0>;
> +			status = "disabled";
> +		};
> +
> +		usbphy: phy@5100400 {
> +			compatible = "allwinner,sun50i-a100-usb-phy",
> +				     "allwinner,sun20i-d1-usb-phy";
> +			reg = <0x05100400 0x100>,
> +			      <0x05101800 0x100>,
> +			      <0x05200800 0x100>;
> +			reg-names = "phy_ctrl",
> +				    "pmu0",
> +				    "pmu1";
> +			clocks = <&ccu CLK_USB_PHY0>,
> +				 <&ccu CLK_USB_PHY1>;
> +			clock-names = "usb0_phy",
> +				      "usb1_phy";
> +			resets = <&ccu RST_USB_PHY0>,
> +				 <&ccu RST_USB_PHY1>;
> +			reset-names = "usb0_reset",
> +				      "usb1_reset";
> +			status = "disabled";
> +			#phy-cells = <1>;
> +		};
> +
> +		ehci0: usb@5101000 {
> +			compatible = "allwinner,sun50i-a100-ehci",
> +				     "generic-ehci";
> +			reg = <0x05101000 0x100>;
> +			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_OHCI0>,
> +				 <&ccu CLK_BUS_EHCI0>,
> +				 <&ccu CLK_USB_OHCI0>;
> +			resets = <&ccu RST_BUS_OHCI0>,
> +				 <&ccu RST_BUS_EHCI0>;
> +			phys = <&usbphy 0>;
> +			phy-names = "usb";
> +			status = "disabled";
> +		};
> +
> +		ohci0: usb@5101400 {
> +			compatible = "allwinner,sun50i-a100-ohci",
> +				     "generic-ohci";
> +			reg = <0x05101400 0x100>;
> +			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_OHCI0>,
> +				 <&ccu CLK_USB_OHCI0>;
> +			resets = <&ccu RST_BUS_OHCI0>;
> +			phys = <&usbphy 0>;
> +			phy-names = "usb";
> +			status = "disabled";
> +		};
> +
> +		ehci1: usb@5200000 {
> +			compatible = "allwinner,sun50i-a100-ehci",
> +				     "generic-ehci";
> +			reg = <0x05200000 0x100>;
> +			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_OHCI1>,
> +				 <&ccu CLK_BUS_EHCI1>,
> +				 <&ccu CLK_USB_OHCI1>;
> +			resets = <&ccu RST_BUS_OHCI1>,
> +				 <&ccu RST_BUS_EHCI1>;
> +			phys = <&usbphy 1>;
> +			phy-names = "usb";
> +			status = "disabled";
> +		};
> +
> +		ohci1: usb@5200400 {
> +			compatible = "allwinner,sun50i-a100-ohci",
> +				     "generic-ohci";
> +			reg = <0x05200400 0x100>;
> +			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_OHCI1>,
> +				 <&ccu CLK_USB_OHCI1>;
> +			resets = <&ccu RST_BUS_OHCI1>;
> +			phys = <&usbphy 1>;
> +			phy-names = "usb";
> +			status = "disabled";
> +		};
> +
>  		r_ccu: clock@7010000 {
>  			compatible = "allwinner,sun50i-a100-r-ccu";
>  			reg = <0x07010000 0x300>;

Re: [PATCH v2 06/13] arm64: dts: allwinner: a100: add usb related nodes

[Cody Eksal]

On 2024/10/31 4:02 am, Cody Eksal wrote:
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi 
> b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> index adb11b26045f..f6162a107641 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
> @@ -302,6 +302,97 @@ ths: thermal-sensor@5070400 {
>  			#thermal-sensor-cells = <1>;
>  		};
> +
> +		usb_otg: usb@5100000 {
> +			compatible = "allwinner,sun50i-a100-musb",
> +				     "allwinner,sun8i-a33-musb";
> +			reg = <0x05100000 0x0400>;
> +			clocks = <&ccu CLK_BUS_OTG>;
> +			resets = <&ccu RST_BUS_OTG>;
> +			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "mc";
> +			phys = <&usbphy 0>;
> +			phy-names = "usb";
> +			extcon = <&usbphy 0>;
> +			status = "disabled";
> +		};
Quick note: it was determined that if ehci0 and/or ohci0 are enabled,
peripheral mode does not function correctly. From my understanding, it 
is
an unrelated issue in musb that causes this; the PHY gets claimed by the
HCI nodes before MUSB, and due to some other issue, the PHY doesn't get
properly rerouted to MUSB. With those nodes disabled, attaching gadgets 
to
MUSB works correctly, and with them enabled, host mode works properly.

- Cody
> +		usbphy: phy@5100400 {
> +			compatible = "allwinner,sun50i-a100-usb-phy",
> +				     "allwinner,sun20i-d1-usb-phy";
> +			reg = <0x05100400 0x100>,
> +			      <0x05101800 0x100>,
> +			      <0x05200800 0x100>;
> +			reg-names = "phy_ctrl",
> +				    "pmu0",
> +				    "pmu1";
> +			clocks = <&ccu CLK_USB_PHY0>,
> +				 <&ccu CLK_USB_PHY1>;
> +			clock-names = "usb0_phy",
> +				      "usb1_phy";
> +			resets = <&ccu RST_USB_PHY0>,
> +				 <&ccu RST_USB_PHY1>;
> +			reset-names = "usb0_reset",
> +				      "usb1_reset";
> +			status = "disabled";
> +			#phy-cells = <1>;
> +		};
> +
> +		ehci0: usb@5101000 {
> +			compatible = "allwinner,sun50i-a100-ehci",
> +				     "generic-ehci";
> +			reg = <0x05101000 0x100>;
> +			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_OHCI0>,
> +				 <&ccu CLK_BUS_EHCI0>,
> +				 <&ccu CLK_USB_OHCI0>;
> +			resets = <&ccu RST_BUS_OHCI0>,
> +				 <&ccu RST_BUS_EHCI0>;
> +			phys = <&usbphy 0>;
> +			phy-names = "usb";
> +			status = "disabled";
> +		};
> +
> +		ohci0: usb@5101400 {
> +			compatible = "allwinner,sun50i-a100-ohci",
> +				     "generic-ohci";
> +			reg = <0x05101400 0x100>;
> +			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_OHCI0>,
> +				 <&ccu CLK_USB_OHCI0>;
> +			resets = <&ccu RST_BUS_OHCI0>;
> +			phys = <&usbphy 0>;
> +			phy-names = "usb";
> +			status = "disabled";
> +		};

Re: [PATCH v2 07/13] arm64: allwinner: A100: enable EHCI, OHCI and USB PHY nodes in Perf1

[Chen-Yu Tsai]

On Thu, Oct 31, 2024 at 3:03 PM Cody Eksal <masterr3c0rd@epochal.quest> wrote:
>
> From: Yangtao Li <frank@allwinnertech.com>
>
> Add USB support on A100 perf1 board, which include two USB2.0 port.
>
> Signed-off-by: Yangtao Li <frank@allwinnertech.com>
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
> ---
> Changes in V2:
>  - Add dr_mode here, instead of in the .dtsi
>
>  .../allwinner/sun50i-a100-allwinner-perf1.dts | 39 +++++++++++++++++++
>  1 file changed, 39 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
> index f5c5c1464482..2f8c7ee60283 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
> @@ -7,6 +7,8 @@
>
>  #include "sun50i-a100.dtsi"
>
> +#include <dt-bindings/gpio/gpio.h>
> +
>  /{
>         model = "Allwinner A100 Perf1";
>         compatible = "allwinner,a100-perf1", "allwinner,sun50i-a100";
> @@ -18,6 +20,36 @@ aliases {
>         chosen {
>                 stdout-path = "serial0:115200n8";
>         };
> +
> +       reg_usb1_vbus: usb1-vbus {
> +               compatible = "regulator-fixed";
> +               regulator-name = "usb1-vbus";
> +               regulator-min-microvolt = <5000000>;
> +               regulator-max-microvolt = <5000000>;
> +               gpio = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
> +               enable-active-high;
> +       };
> +};
> +
> +&ehci0 {
> +       status = "okay";
> +};
> +
> +&ehci1 {
> +       status = "okay";
> +};
> +
> +&ohci0 {
> +       status = "okay";
> +};
> +
> +&ohci1 {
> +       status = "okay";
> +};
> +
> +&usb_otg {
> +       dr_mode = "otg";
> +       status = "okay";

Since you noted in the previous patch that OTG doesn't work if OHCI0/EHCI0
are enabled and probed before musb, maybe we should keep them disabled
for the time being?

You could leave a TODO item above the &usb_otg node.

ChenYu

>  };
>
>  &pio {
> @@ -178,3 +210,10 @@ &uart0 {
>         pinctrl-0 = <&uart0_pb_pins>;
>         status = "okay";
>  };
> +
> +&usbphy {
> +       usb0_id_det-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
> +       usb0_vbus-supply = <&reg_drivevbus>;
> +       usb1_vbus-supply = <&reg_usb1_vbus>;
> +       status = "okay";
> +};
> --
> 2.47.0
>

Re: (subset) [PATCH v2 00/13] sunxi: A100/A133 second stage support

[Chen-Yu Tsai]

On Thu, 31 Oct 2024 04:02:13 -0300, Cody Eksal wrote:
> This is V2 of this series [5], with some changes that were requested and
> others that were made after testing on more devices. Thank you for all of
> your feedback! A changelog is available below.
> 
> ==================
> Back in 2020, two Allwinner employees, Yangtao Li and Shuosheng Huang, each
> submitted a patch series for the A100 series of SoCs; [1] intended to add
> support for the watchdog, ARM PMU, DMA, USB, and (e)MMC controller, and [2]
> implemented DVFS support. Some patches from the first series landed, but
> the rest were seemingly abandoned.
> 
> [...]

Applied to dt-for-6.13 in git@github.com:linux-sunxi/linux-sunxi.git, thanks!

[01/13] arm64: dts: allwinner: A100: Add PMU mode
        commit: 248b20ed03545656bd1775ed115369854f58f55c
[02/13] arm64: dts: allwinner: a100: add watchdog node
        commit: f84a3aa7782687ca0fa54f768fc6bb825575f91a
[03/13] dt-bindings: phy: sun50i-a64: add a100 compatible
        commit: 4402ef303d4b90748646568cf48f52eea035057a
[04/13] dt-bindings: usb: Add A100 compatible string
        commit: 1e7d0e2a53e6bf4b43f78858b1fb10aa38259375
[05/13] dt-bindings: usb: sunxi-musb: Add A100 compatible string
        commit: e144e89de0e491ea191847b0dc15a5aeb27951eb
[06/13] arm64: dts: allwinner: a100: add usb related nodes
        commit: c3cc9b02f7490d93635692cf58b0a4e517a60ab2
[09/13] arm64: allwinner: a100: Add MMC related nodes
        commit: fcfbb8d9ec584c256c0a6e1ae3174a21b007f399

Best regards,
-- 
Chen-Yu Tsai <wens@csie.org>

Re: [PATCH v2 10/13] arm64: dts: allwinner: a100: perf1: Add eMMC and MMC node

[Chen-Yu Tsai]

On Thu, Oct 31, 2024 at 3:03 PM Cody Eksal <masterr3c0rd@epochal.quest> wrote:
>
> From: Yangtao Li <frank@allwinnertech.com>
>
> A100 perf1 hava MicroSD slot and on-board eMMC module, add support for them.
>
> Signed-off-by: Yangtao Li <frank@allwinnertech.com>
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>

So I skipped this one since Andre had some questions about the previous
mmc clock patch. And I believe this one won't work without it?

ChenYu

> ---
>  .../allwinner/sun50i-a100-allwinner-perf1.dts    | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
> index 2f8c7ee60283..d418fc272b3c 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts
> @@ -39,6 +39,22 @@ &ehci1 {
>         status = "okay";
>  };
>
> +&mmc0 {
> +       vmmc-supply = <&reg_dcdc1>;
> +       cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
> +       bus-width = <4>;
> +       status = "okay";
> +};
> +
> +&mmc2 {
> +       vmmc-supply = <&reg_dcdc1>;
> +       vqmmc-supply = <&reg_aldo1>;
> +       cap-mmc-hw-reset;
> +       non-removable;
> +       bus-width = <8>;
> +       status = "okay";
> +};
> +
>  &ohci0 {
>         status = "okay";
>  };
> --
> 2.47.0
>

Re: [PATCH v2 11/13] dt-bindings: opp: h6: Add A100 operating points

[Chen-Yu Tsai]

On Thu, Oct 31, 2024 at 3:03 PM Cody Eksal <masterr3c0rd@epochal.quest> wrote:
>
> The A100, similar to the H6 and H616, use an NVMEM value to determine
> speed binnings. The method used is similar to that of the H6. However,
> the information is stored at a slightly different bit offset.
>
> Add a new compatible for the A100.
>
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>

Acked-by: Chen-Yu Tsai <wens@csie.org>

I assume Viresh will take this along with the cpufreq driver patch.

> ---
> Changes in V2:
>  - Fix ordering of compatibles
>
>  .../bindings/opp/allwinner,sun50i-h6-operating-points.yaml       | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
> index ec5e424bb3c8..75ab552f6ecd 100644
> --- a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
> +++ b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
> @@ -22,6 +22,7 @@ allOf:
>  properties:
>    compatible:
>      enum:
> +      - allwinner,sun50i-a100-operating-points
>        - allwinner,sun50i-h6-operating-points
>        - allwinner,sun50i-h616-operating-points
>
> --
> 2.47.0
>

Re: [PATCH v2 10/13] arm64: dts: allwinner: a100: perf1: Add eMMC and MMC node

[Cody Eksal]

On 2024/11/02 8:48 am, Chen-Yu Tsai wrote:
> On Thu, Oct 31, 2024 at 3:03 PM Cody Eksal <masterr3c0rd@epochal.quest> wrote:
>>
>> From: Yangtao Li <frank@allwinnertech.com>
>>
>> A100 perf1 hava MicroSD slot and on-board eMMC module, add support for them.
>>
>> Signed-off-by: Yangtao Li <frank@allwinnertech.com>
>> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
> 
> So I skipped this one since Andre had some questions about the previous
> mmc clock patch. And I believe this one won't work without it?
eMMC (mmc2) works fine after more testing, even without the clock
reparenting patch (in fact, it appears to work more consistently), but
mmc0 and mmc1 require more testing and debugging. I'll deal with
the remaining MMC issues in a future patch.

- Cody

> ChenYu
> 
>> ---
>>  .../allwinner/sun50i-a100-allwinner-perf1.dts    | 16 ++++++++++++++++
>>  1 file changed, 16 insertions(+)

Re: [PATCH v2 08/13] clk: sunxi-ng: a100: enable MMC clock reparenting

[Cody Eksal]

On 2024/10/31 9:08 am, Andre Przywara wrote:
> Well, while this change indeed prevented that error message you mentioned,
> but the SD card still doesn't work for me: it probes and I can mount a
> filesystem on it, but then it hangs, for instance when running an "ls" on
> it. It could be my setup (lacking DT or device issue or missing kernel
> config), though, and the eMMC works for me this way, but it would be good
> to have that sorted. 
I'm investigating this now; it appears mmc2/eMMC is more consistent when
CLK_NO_REPARENT is set

> Also it would be good to know why CLK_SET_RATE_NO_REPARENT was put there
> in the first place: I don't see it in any other MMC clocks in sunxi-ng, so
> it wasn't just copied&pasted.
Seeing that mmc2 acts better with the flag, perhaps it was copy + pasted
from that config. Or perhaps the issues we're running into comes from
elsewhere in the chain. At the moment, that's only speculation, though;
I'm waiting on a device that has an SD card slot so I can perform more
testing myself and debug these issues.

> So was there a problem that this flag was supposed to fix? Is that
> something that only applied to older kernels (back when the MMC patches
> were first posted), and which has now been fixed/changed elsewhere?
Yangtao Li/Frank Lee assumably no longer works at Allwinner, as the email
he used to submit this originally no longer exists, but I believe the same
Yangtao is now a maintainer of the Allwinner cpufreq subsystem, and is
CC'd on these patches. I'm sending this reply to him as well; perhaps he
may have some additional insight.

> I feel a bit uneasy of just removing this just because it works(TM),
> especially if it doesn't really (SD card for me, for instance).
I agree; I was quickly preparing V2 to hopefully get this in before the
6.13 window for the sunxi tree closed, and added this in last minute after
verifying it worked on my current device, which lacks an SD card slot.

This patch can be skipped for now, as it's apparent MMC0/1 require a little
more love before we can merge it in. I'll submit new patches in the future
once this is figured out.

Thanks!
- Cody

> Cheers,
> Andre
> 
>> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
>> ---
>>  drivers/clk/sunxi-ng/ccu-sun50i-a100.c | 6 +++---
>>  1 file changed, 3 insertions(+), 3 deletions(-)

Re: [PATCH v2 08/13] clk: sunxi-ng: a100: enable MMC clock reparenting

[Andre Przywara]

On Sat, 02 Nov 2024 18:44:41 -0300
Cody Eksal <masterr3c0rd@epochal.quest> wrote:

Hi Cody,

thanks for staying on this issue!

> On 2024/10/31 9:08 am, Andre Przywara wrote:
> > Well, while this change indeed prevented that error message you mentioned,
> > but the SD card still doesn't work for me: it probes and I can mount a
> > filesystem on it, but then it hangs, for instance when running an "ls" on
> > it. It could be my setup (lacking DT or device issue or missing kernel
> > config), though, and the eMMC works for me this way, but it would be good
> > to have that sorted.   
> I'm investigating this now; it appears mmc2/eMMC is more consistent when
> CLK_NO_REPARENT is set

What do you mean with "more consistent", exactly?
I still don't get why NO_REPARENT would help here in the first place:
we have three clocks as potential parents: OSC24MHz, PLL_PERIPH0,
PLL_PERIPH1. The first one is too slow for typical MMC rates, and
PERIPH1 is typically disabled (it's the same rates as PERIPH0, so
there is little need for it). So PERIPH0 is to clock to go, and I don't
see what NO_REPARENT would change here.

So those are my observations:
With NO_REPARENT (current mainline):
- SD card fails to probe:
  sunxi-mmc 4020000.mmc: fatal err update clk timeout
- SD card is still parented to PERIPH0-2x (probably because U-Boot set
  that up), but uses a divider of 256 for a clock rate of 4687500 Hz.
  This probably leads to the failures.
- eMMC works, but is parented to the 24MHz OSC, probably because U-Boot
  did not touch it. The clock rate is 12MHz, the read speed is 10MB/s.
With removing NO_REPARENT, so with this patch:
- SD cards probes, I can mount a VFAT fs on it, and sometimes "ls"
  that, but it hangs soon afterwards, for instance when trying to
  benchmark it.
- SD clock is set up correctly: parent is PLL_PERIPH0-2x, rate is 50
  MHz, correct for High Speed@4bit and its 25MB/s bus speed.
- eMMC works fine, clock parent is PLL-PERIPH0-2x, rate is 100 MHz,
  correct for HS-200 (100 MHz * 8 bit * 2(DDR)). The read speed is
  72MB/s, which sounds alright, and might be a limitation of the flash
  chip.

So NO_REPARENT is always worse for me.

> > Also it would be good to know why CLK_SET_RATE_NO_REPARENT was put there
> > in the first place: I don't see it in any other MMC clocks in sunxi-ng, so
> > it wasn't just copied&pasted.  
> Seeing that mmc2 acts better with the flag, perhaps it was copy + pasted
> from that config. Or perhaps the issues we're running into comes from
> elsewhere in the chain. At the moment, that's only speculation, though;
> I'm waiting on a device that has an SD card slot so I can perform more
> testing myself and debug these issues.
> 
> > So was there a problem that this flag was supposed to fix? Is that
> > something that only applied to older kernels (back when the MMC patches
> > were first posted), and which has now been fixed/changed elsewhere?  
> Yangtao Li/Frank Lee assumably no longer works at Allwinner, as the email
> he used to submit this originally no longer exists, but I believe the same
> Yangtao is now a maintainer of the Allwinner cpufreq subsystem, and is
> CC'd on these patches. I'm sending this reply to him as well; perhaps he
> may have some additional insight.
> 
> > I feel a bit uneasy of just removing this just because it works(TM),
> > especially if it doesn't really (SD card for me, for instance).  
> I agree; I was quickly preparing V2 to hopefully get this in before the
> 6.13 window for the sunxi tree closed, and added this in last minute after
> verifying it worked on my current device, which lacks an SD card slot.
> 
> This patch can be skipped for now, as it's apparent MMC0/1 require a little
> more love before we can merge it in. I'll submit new patches in the future
> once this is figured out.

This patch would be a fix anyway (with a Fixes: tag), so we can push it
still into 6.13, after -rc1, and it would be backported. So it's not as
critical, timing-wise.

Cheers,
Andre

> 
> Thanks!
> - Cody
> 
> > Cheers,
> > Andre
> >   
> >> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
> >> ---
> >>  drivers/clk/sunxi-ng/ccu-sun50i-a100.c | 6 +++---
> >>  1 file changed, 3 insertions(+), 3 deletions(-)  
> 

Re: [PATCH v2 10/13] arm64: dts: allwinner: a100: perf1: Add eMMC and MMC node

[Chen-Yu Tsai]

On Sun, Nov 3, 2024 at 5:23 AM Cody Eksal <masterr3c0rd@epochal.quest> wrote:
>
> On 2024/11/02 8:48 am, Chen-Yu Tsai wrote:
> > On Thu, Oct 31, 2024 at 3:03 PM Cody Eksal <masterr3c0rd@epochal.quest> wrote:
> >>
> >> From: Yangtao Li <frank@allwinnertech.com>
> >>
> >> A100 perf1 hava MicroSD slot and on-board eMMC module, add support for them.
> >>
> >> Signed-off-by: Yangtao Li <frank@allwinnertech.com>
> >> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
> >
> > So I skipped this one since Andre had some questions about the previous
> > mmc clock patch. And I believe this one won't work without it?
> eMMC (mmc2) works fine after more testing, even without the clock
> reparenting patch (in fact, it appears to work more consistently), but
> mmc0 and mmc1 require more testing and debugging. I'll deal with
> the remaining MMC issues in a future patch.

I think it would be better if only the eMMC was enabled. Enabling something
that is almost guaranteed to cause data corruption isn't going to be fun
for users.

ChenYu

Re: [PATCH v2 08/13] clk: sunxi-ng: a100: enable MMC clock reparenting

[Andre Przywara]

On Sun, 3 Nov 2024 02:09:29 +0000
Andre Przywara <andre.przywara@arm.com> wrote:

Hi,

> On Sat, 02 Nov 2024 18:44:41 -0300
> Cody Eksal <masterr3c0rd@epochal.quest> wrote:
> 
> Hi Cody,
> 
> thanks for staying on this issue!
> 
> > On 2024/10/31 9:08 am, Andre Przywara wrote:  
> > > Well, while this change indeed prevented that error message you mentioned,
> > > but the SD card still doesn't work for me: it probes and I can mount a
> > > filesystem on it, but then it hangs, for instance when running an "ls" on
> > > it. It could be my setup (lacking DT or device issue or missing kernel
> > > config), though, and the eMMC works for me this way, but it would be good
> > > to have that sorted.     
> > I'm investigating this now; it appears mmc2/eMMC is more consistent when
> > CLK_NO_REPARENT is set  
> 
> What do you mean with "more consistent", exactly?
> I still don't get why NO_REPARENT would help here in the first place:
> we have three clocks as potential parents: OSC24MHz, PLL_PERIPH0,
> PLL_PERIPH1. The first one is too slow for typical MMC rates, and
> PERIPH1 is typically disabled (it's the same rates as PERIPH0, so
> there is little need for it). So PERIPH0 is to clock to go, and I don't
> see what NO_REPARENT would change here.
> 
> So those are my observations:
> With NO_REPARENT (current mainline):
> - SD card fails to probe:
>   sunxi-mmc 4020000.mmc: fatal err update clk timeout
> - SD card is still parented to PERIPH0-2x (probably because U-Boot set
>   that up), but uses a divider of 256 for a clock rate of 4687500 Hz.
>   This probably leads to the failures.
> - eMMC works, but is parented to the 24MHz OSC, probably because U-Boot
>   did not touch it. The clock rate is 12MHz, the read speed is 10MB/s.
> With removing NO_REPARENT, so with this patch:
> - SD cards probes, I can mount a VFAT fs on it, and sometimes "ls"
>   that, but it hangs soon afterwards, for instance when trying to
>   benchmark it.

It turns out that this it due to a wrong DMA block size description in
the MMC driver: the A100/A133 only supports 8K blocks, not 64K as
currently advertised there. Patch for that here: [1]
With that patch I see the SD card fully working, and at the correct
speed, so this patch here is:

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Please add a Fixes tag and Cc: stable to the tags, like this:

Fixes: fb038ce4db55 ("clk: sunxi-ng: add support for the Allwinner A100 CCU")
Cc: stable@vger.kernel.org

And make sure to also Cc: that address when sending that out. Or
Chen-Yu adds the tags while committing, and we send this separately to stable?

And maybe we can change the commit message to be a bit less vague, and
just say while it's unknown why the flag was there in the first place,
it doesn't make any sense and severely limits MMC transfer speeds.

Cheers,
Andre


[1] https://lore.kernel.org/linux-sunxi/20241107014240.24669-1-andre.przywara@arm.com/T/#u

> - SD clock is set up correctly: parent is PLL_PERIPH0-2x, rate is 50
>   MHz, correct for High Speed@4bit and its 25MB/s bus speed.
> - eMMC works fine, clock parent is PLL-PERIPH0-2x, rate is 100 MHz,
>   correct for HS-200 (100 MHz * 8 bit * 2(DDR)). The read speed is
>   72MB/s, which sounds alright, and might be a limitation of the flash
>   chip.
> 
> So NO_REPARENT is always worse for me.
> 
> > > Also it would be good to know why CLK_SET_RATE_NO_REPARENT was put there
> > > in the first place: I don't see it in any other MMC clocks in sunxi-ng, so
> > > it wasn't just copied&pasted.    
> > Seeing that mmc2 acts better with the flag, perhaps it was copy + pasted
> > from that config. Or perhaps the issues we're running into comes from
> > elsewhere in the chain. At the moment, that's only speculation, though;
> > I'm waiting on a device that has an SD card slot so I can perform more
> > testing myself and debug these issues.
> >   
> > > So was there a problem that this flag was supposed to fix? Is that
> > > something that only applied to older kernels (back when the MMC patches
> > > were first posted), and which has now been fixed/changed elsewhere?    
> > Yangtao Li/Frank Lee assumably no longer works at Allwinner, as the email
> > he used to submit this originally no longer exists, but I believe the same
> > Yangtao is now a maintainer of the Allwinner cpufreq subsystem, and is
> > CC'd on these patches. I'm sending this reply to him as well; perhaps he
> > may have some additional insight.
> >   
> > > I feel a bit uneasy of just removing this just because it works(TM),
> > > especially if it doesn't really (SD card for me, for instance).    
> > I agree; I was quickly preparing V2 to hopefully get this in before the
> > 6.13 window for the sunxi tree closed, and added this in last minute after
> > verifying it worked on my current device, which lacks an SD card slot.
> > 
> > This patch can be skipped for now, as it's apparent MMC0/1 require a little
> > more love before we can merge it in. I'll submit new patches in the future
> > once this is figured out.  
> 
> This patch would be a fix anyway (with a Fixes: tag), so we can push it
> still into 6.13, after -rc1, and it would be backported. So it's not as
> critical, timing-wise.
> 
> Cheers,
> Andre
> 
> > 
> > Thanks!
> > - Cody
> >   
> > > Cheers,
> > > Andre
> > >     
> > >> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
> > >> ---
> > >>  drivers/clk/sunxi-ng/ccu-sun50i-a100.c | 6 +++---
> > >>  1 file changed, 3 insertions(+), 3 deletions(-)    
> >   
> 
> 

Re: (subset) [PATCH v2 00/13] sunxi: A100/A133 second stage support

[Chen-Yu Tsai]

On Thu, 31 Oct 2024 04:02:13 -0300, Cody Eksal wrote:
> This is V2 of this series [5], with some changes that were requested and
> others that were made after testing on more devices. Thank you for all of
> your feedback! A changelog is available below.
> 
> ==================
> Back in 2020, two Allwinner employees, Yangtao Li and Shuosheng Huang, each
> submitted a patch series for the A100 series of SoCs; [1] intended to add
> support for the watchdog, ARM PMU, DMA, USB, and (e)MMC controller, and [2]
> implemented DVFS support. Some patches from the first series landed, but
> the rest were seemingly abandoned.
> 
> [...]

Applied to dt-for-6.13 in git@github.com:linux-sunxi/linux-sunxi.git, thanks!

[10/13] arm64: dts: allwinner: a100: perf1: Add eMMC and MMC node
        commit: af1ad5675a2b5feebb49df0e0ac7dab1aeabfaa8

Best regards,
-- 
Chen-Yu Tsai <wens@csie.org>

Re: [PATCH v2 12/13] cpufreq: sun50i: add a100 cpufreq support

[Viresh Kumar]

On 31-10-24, 04:02, Cody Eksal wrote:
> From: Shuosheng Huang <huangshuosheng@allwinnertech.com>
> 
> Let's add cpufreq nvmem based for allwinner a100 soc. It's similar to h6,
> let us use efuse_xlate to extract the differentiated part.
> 
> Signed-off-by: Shuosheng Huang <huangshuosheng@allwinnertech.com>
> [masterr3c0rd@epochal.quest: add A100 to opp_match_list]
> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
> ---
> Changes in V2:
>  - Add the A100 to the cpufreq-dt-platdev blacklist.

Can this be applied to the cpufreq tree separately ?

-- 
viresh

Re: [PATCH v2 12/13] cpufreq: sun50i: add a100 cpufreq support

[Chen-Yu Tsai]

On Mon, Nov 11, 2024 at 12:13 PM Viresh Kumar <viresh.kumar@linaro.org> wrote:
>
> On 31-10-24, 04:02, Cody Eksal wrote:
> > From: Shuosheng Huang <huangshuosheng@allwinnertech.com>
> >
> > Let's add cpufreq nvmem based for allwinner a100 soc. It's similar to h6,
> > let us use efuse_xlate to extract the differentiated part.
> >
> > Signed-off-by: Shuosheng Huang <huangshuosheng@allwinnertech.com>
> > [masterr3c0rd@epochal.quest: add A100 to opp_match_list]
> > Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
> > ---
> > Changes in V2:
> >  - Add the A100 to the cpufreq-dt-platdev blacklist.
>
> Can this be applied to the cpufreq tree separately ?

Yes.

Acked-by: Chen-Yu Tsai <wens@csie.org>

Re: [PATCH v2 12/13] cpufreq: sun50i: add a100 cpufreq support

[Viresh Kumar]

On 11-11-24, 13:30, Chen-Yu Tsai wrote:
> On Mon, Nov 11, 2024 at 12:13 PM Viresh Kumar <viresh.kumar@linaro.org> wrote:
> >
> > On 31-10-24, 04:02, Cody Eksal wrote:
> > > From: Shuosheng Huang <huangshuosheng@allwinnertech.com>
> > >
> > > Let's add cpufreq nvmem based for allwinner a100 soc. It's similar to h6,
> > > let us use efuse_xlate to extract the differentiated part.
> > >
> > > Signed-off-by: Shuosheng Huang <huangshuosheng@allwinnertech.com>
> > > [masterr3c0rd@epochal.quest: add A100 to opp_match_list]
> > > Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
> > > ---
> > > Changes in V2:
> > >  - Add the A100 to the cpufreq-dt-platdev blacklist.
> >
> > Can this be applied to the cpufreq tree separately ?
> 
> Yes.
> 
> Acked-by: Chen-Yu Tsai <wens@csie.org>

Applied. Thanks.

-- 
viresh

Re: [PATCH v2 12/13] cpufreq: sun50i: add a100 cpufreq support

[Rob Herring]

On Sun, Nov 10, 2024 at 11:55 PM Viresh Kumar <viresh.kumar@linaro.org> wrote:
>
> On 11-11-24, 13:30, Chen-Yu Tsai wrote:
> > On Mon, Nov 11, 2024 at 12:13 PM Viresh Kumar <viresh.kumar@linaro.org> wrote:
> > >
> > > On 31-10-24, 04:02, Cody Eksal wrote:
> > > > From: Shuosheng Huang <huangshuosheng@allwinnertech.com>
> > > >
> > > > Let's add cpufreq nvmem based for allwinner a100 soc. It's similar to h6,
> > > > let us use efuse_xlate to extract the differentiated part.
> > > >
> > > > Signed-off-by: Shuosheng Huang <huangshuosheng@allwinnertech.com>
> > > > [masterr3c0rd@epochal.quest: add A100 to opp_match_list]
> > > > Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
> > > > ---
> > > > Changes in V2:
> > > >  - Add the A100 to the cpufreq-dt-platdev blacklist.
> > >
> > > Can this be applied to the cpufreq tree separately ?
> >
> > Yes.
> >
> > Acked-by: Chen-Yu Tsai <wens@csie.org>
>
> Applied. Thanks.

You missed the binding patch, so
"allwinner,sun50i-a100-operating-points" is undocumented. Can you pick
that up please.

Rob

Re: [PATCH v2 12/13] cpufreq: sun50i: add a100 cpufreq support

[Rob Herring]

On Mon, Nov 18, 2024 at 09:36:37AM -0600, Rob Herring wrote:
> On Sun, Nov 10, 2024 at 11:55 PM Viresh Kumar <viresh.kumar@linaro.org> wrote:
> >
> > On 11-11-24, 13:30, Chen-Yu Tsai wrote:
> > > On Mon, Nov 11, 2024 at 12:13 PM Viresh Kumar <viresh.kumar@linaro.org> wrote:
> > > >
> > > > On 31-10-24, 04:02, Cody Eksal wrote:
> > > > > From: Shuosheng Huang <huangshuosheng@allwinnertech.com>
> > > > >
> > > > > Let's add cpufreq nvmem based for allwinner a100 soc. It's similar to h6,
> > > > > let us use efuse_xlate to extract the differentiated part.
> > > > >
> > > > > Signed-off-by: Shuosheng Huang <huangshuosheng@allwinnertech.com>
> > > > > [masterr3c0rd@epochal.quest: add A100 to opp_match_list]
> > > > > Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
> > > > > ---
> > > > > Changes in V2:
> > > > >  - Add the A100 to the cpufreq-dt-platdev blacklist.
> > > >
> > > > Can this be applied to the cpufreq tree separately ?
> > >
> > > Yes.
> > >
> > > Acked-by: Chen-Yu Tsai <wens@csie.org>
> >
> > Applied. Thanks.
> 
> You missed the binding patch, so
> "allwinner,sun50i-a100-operating-points" is undocumented. Can you pick
> that up please.

Still not applied, so I applied it.

Rob

Re: [PATCH v2 12/13] cpufreq: sun50i: add a100 cpufreq support

[Viresh Kumar]

On 09-01-25, 16:53, Rob Herring wrote:
> > You missed the binding patch, so
> > "allwinner,sun50i-a100-operating-points" is undocumented. Can you pick
> > that up please.
> 
> Still not applied, so I applied it.

Somehow missed your previous email. Sorry about that.

-- 
viresh

Re: (subset) [PATCH v2 00/13] sunxi: A100/A133 second stage support

[Chen-Yu Tsai]

On Thu, 31 Oct 2024 04:02:13 -0300, Cody Eksal wrote:
> This is V2 of this series [5], with some changes that were requested and
> others that were made after testing on more devices. Thank you for all of
> your feedback! A changelog is available below.
> 
> ==================
> Back in 2020, two Allwinner employees, Yangtao Li and Shuosheng Huang, each
> submitted a patch series for the A100 series of SoCs; [1] intended to add
> support for the watchdog, ARM PMU, DMA, USB, and (e)MMC controller, and [2]
> implemented DVFS support. Some patches from the first series landed, but
> the rest were seemingly abandoned.
> 
> [...]

Applied to dt-for-6.15 in git@github.com:linux-sunxi/linux-sunxi.git, thanks!

[13/13] arm64: dts: allwinner: a100: Add CPU Operating Performance Points table
        commit: a8181e6861fec3068f393d77ff81b2aaf4ea4203

Best regards,
-- 
Chen-Yu Tsai <wens@csie.org>