* [PATCH v2 0/5] add support for T7 family clock controller
@ 2025-01-08 9:40 Jian Hu
2025-01-08 9:40 ` [PATCH v2 1/5] dt-bindings: clock: add Amlogic T7 PLL " Jian Hu
` (4 more replies)
0 siblings, 5 replies; 14+ messages in thread
From: Jian Hu @ 2025-01-08 9:40 UTC (permalink / raw)
To: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong,
Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov,
robh+dt, Rob Herring
Cc: Jian Hu, devicetree, linux-clk, linux-amlogic, linux-kernel,
linux-arm-kernel
It introduces three clock controllers:
- scmi clock controller, these clocks are managed by the SCP and handled through SCMI;
- PLL clock controller;
- peripheral clock controller.
Changes v2 since v1 at [1]:
- add CLK_MESON import
- add const for clkc_regmao_config in pll driver
- fix eth_rmii_sel parent
- update T7 PLL YAML file
[1]: https://lore.kernel.org/r/20241231060047.2298871-6-jian.hu%40amlogic.com
Jian Hu (5):
dt-bindings: clock: add Amlogic T7 PLL clock controller
dt-bindings: clock: add Amlogic T7 SCMI clock controller
dt-bindings: clock: add Amlogic T7 peripherals clock controller
clk: meson: t7: add support for the T7 SoC PLL clock
clk: meson: t7: add t7 clock peripherals controller driver
.../clock/amlogic,t7-peripherals-clkc.yaml | 111 +
.../bindings/clock/amlogic,t7-pll-clkc.yaml | 103 +
drivers/clk/meson/Kconfig | 27 +
drivers/clk/meson/Makefile | 2 +
drivers/clk/meson/t7-peripherals.c | 2323 +++++++++++++++++
drivers/clk/meson/t7-pll.c | 1193 +++++++++
.../clock/amlogic,t7-peripherals-clkc.h | 231 ++
.../dt-bindings/clock/amlogic,t7-pll-clkc.h | 57 +
include/dt-bindings/clock/amlogic,t7-scmi.h | 48 +
9 files changed, 4095 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
create mode 100644 drivers/clk/meson/t7-peripherals.c
create mode 100644 drivers/clk/meson/t7-pll.c
create mode 100644 include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h
create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h
create mode 100644 include/dt-bindings/clock/amlogic,t7-scmi.h
--
2.47.1
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH v2 1/5] dt-bindings: clock: add Amlogic T7 PLL clock controller 2025-01-08 9:40 [PATCH v2 0/5] add support for T7 family clock controller Jian Hu @ 2025-01-08 9:40 ` Jian Hu 2025-01-10 15:54 ` Rob Herring 2025-01-08 9:40 ` [PATCH v2 2/5] dt-bindings: clock: add Amlogic T7 SCMI " Jian Hu ` (3 subsequent siblings) 4 siblings, 1 reply; 14+ messages in thread From: Jian Hu @ 2025-01-08 9:40 UTC (permalink / raw) To: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring Cc: Jian Hu, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel Add DT bindings for the PLL clock controller of the Amlogic T7 SoC family. Signed-off-by: Jian Hu <jian.hu@amlogic.com> --- .../bindings/clock/amlogic,t7-pll-clkc.yaml | 103 ++++++++++++++++++ .../dt-bindings/clock/amlogic,t7-pll-clkc.h | 57 ++++++++++ 2 files changed, 160 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml new file mode 100644 index 000000000000..fd0323678d37 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +# Copyright (C) 2024 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic T7 PLL Clock Control Controller + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + - Jerome Brunet <jbrunet@baylibre.com> + - Jian Hu <jian.hu@amlogic.com> + - Xianwei Zhao <xianwei.zhao@amlogic.com> + +if: + properties: + compatible: + contains: + const: amlogic,t7-pll-mclk + +then: + properties: + clocks: + items: + - description: mclk pll input oscillator gate + - description: 24M oscillator input clock source for mclk_sel_0 + - description: fix 50Mhz input clock source for mclk_sel_0 + + clock-names: + items: + - const: input + - const: mclk_in0 + - const: mclk_in1 + +else: + properties: + clocks: + items: + - description: pll input oscillator gate + + clock-names: + items: + - const: input + +properties: + compatible: + enum: + - amlogic,t7-pll-gp0 + - amlogic,t7-pll-gp1 + - amlogic,t7-pll-hifi + - amlogic,t7-pll-pcie + - amlogic,t7-mpll + - amlogic,t7-pll-hdmi + - amlogic,t7-pll-mclk + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + minItems: 1 + maxItems: 3 + + clock-names: + minItems: 1 + maxItems: 3 + +required: + - compatible + - '#clock-cells' + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + apb { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@8080 { + compatible = "amlogic,t7-pll-gp0"; + reg = <0 0x8080 0 0x20>; + clocks = <&scmi_clk 2>; + clock-names = "input"; + #clock-cells = <1>; + }; + + clock-controller@8300 { + compatible = "amlogic,t7-pll-mclk"; + reg = <0 0x8300 0 0x18>; + clocks = <&scmi_clk 2>, + <&xtal>, + <&scmi_clk 31>; + clock-names = "input", "mclk_in0", "mclk_in1"; + #clock-cells = <1>; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,t7-pll-clkc.h b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h new file mode 100644 index 000000000000..e88c342028db --- /dev/null +++ b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + * Author: Jian Hu <jian.hu@amlogic.com> + */ + +#ifndef __T7_PLL_CLKC_H +#define __T7_PLL_CLKC_H + +/* GP0 */ +#define CLKID_GP0_PLL_DCO 0 +#define CLKID_GP0_PLL 1 + +/* GP1 */ +#define CLKID_GP1_PLL_DCO 0 +#define CLKID_GP1_PLL 1 + +/* HIFI */ +#define CLKID_HIFI_PLL_DCO 0 +#define CLKID_HIFI_PLL 1 + +/* PCIE */ +#define CLKID_PCIE_PLL_DCO 0 +#define CLKID_PCIE_PLL_DCO_DIV2 1 +#define CLKID_PCIE_PLL_OD 2 +#define CLKID_PCIE_PLL 3 + +/* MPLL */ +#define CLKID_MPLL_PREDIV 0 +#define CLKID_MPLL0_DIV 1 +#define CLKID_MPLL0 2 +#define CLKID_MPLL1_DIV 3 +#define CLKID_MPLL1 4 +#define CLKID_MPLL2_DIV 5 +#define CLKID_MPLL2 6 +#define CLKID_MPLL3_DIV 7 +#define CLKID_MPLL3 8 + +/* HDMI */ +#define CLKID_HDMI_PLL_DCO 0 +#define CLKID_HDMI_PLL_OD 1 +#define CLKID_HDMI_PLL 2 + +/* MCLK */ +#define CLKID_MCLK_PLL_DCO 0 +#define CLKID_MCLK_PRE 1 +#define CLKID_MCLK_PLL 2 +#define CLKID_MCLK_0_SEL 3 +#define CLKID_MCLK_0_DIV2 4 +#define CLKID_MCLK_0_PRE 5 +#define CLKID_MCLK_0 6 +#define CLKID_MCLK_1_SEL 7 +#define CLKID_MCLK_1_DIV2 8 +#define CLKID_MCLK_1_PRE 9 +#define CLKID_MCLK_1 10 + +#endif /* __T7_PLL_CLKC_H */ -- 2.47.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 1/5] dt-bindings: clock: add Amlogic T7 PLL clock controller 2025-01-08 9:40 ` [PATCH v2 1/5] dt-bindings: clock: add Amlogic T7 PLL " Jian Hu @ 2025-01-10 15:54 ` Rob Herring 2025-01-13 17:50 ` Jerome Brunet 2025-01-17 8:01 ` Jian Hu 0 siblings, 2 replies; 14+ messages in thread From: Rob Herring @ 2025-01-10 15:54 UTC (permalink / raw) To: Jian Hu Cc: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel On Wed, Jan 08, 2025 at 05:40:21PM +0800, Jian Hu wrote: > Add DT bindings for the PLL clock controller of the Amlogic T7 SoC family. > > Signed-off-by: Jian Hu <jian.hu@amlogic.com> > --- > .../bindings/clock/amlogic,t7-pll-clkc.yaml | 103 ++++++++++++++++++ > .../dt-bindings/clock/amlogic,t7-pll-clkc.h | 57 ++++++++++ > 2 files changed, 160 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml > create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h > > diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml > new file mode 100644 > index 000000000000..fd0323678d37 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml > @@ -0,0 +1,103 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +# Copyright (C) 2024 Amlogic, Inc. All rights reserved > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Amlogic T7 PLL Clock Control Controller > + > +maintainers: > + - Neil Armstrong <neil.armstrong@linaro.org> > + - Jerome Brunet <jbrunet@baylibre.com> > + - Jian Hu <jian.hu@amlogic.com> > + - Xianwei Zhao <xianwei.zhao@amlogic.com> > + > +if: Move this after 'required' section. Generally we put 'if' under 'allOf' because we're likely to have another if/then schema on the next compatible added. If you don't think this binding will ever get used on another chip, then it is fine as-is. > + properties: > + compatible: > + contains: > + const: amlogic,t7-pll-mclk > + > +then: > + properties: > + clocks: > + items: > + - description: mclk pll input oscillator gate > + - description: 24M oscillator input clock source for mclk_sel_0 > + - description: fix 50Mhz input clock source for mclk_sel_0 > + > + clock-names: > + items: > + - const: input > + - const: mclk_in0 > + - const: mclk_in1 Move these to top-level and then both of these are just 'minItems: 3'. > + > +else: > + properties: > + clocks: > + items: > + - description: pll input oscillator gate > + > + clock-names: > + items: > + - const: input And 'maxItems: 1' here. > + > +properties: > + compatible: > + enum: > + - amlogic,t7-pll-gp0 > + - amlogic,t7-pll-gp1 > + - amlogic,t7-pll-hifi > + - amlogic,t7-pll-pcie > + - amlogic,t7-mpll > + - amlogic,t7-pll-hdmi > + - amlogic,t7-pll-mclk > + > + reg: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > + clocks: > + minItems: 1 > + maxItems: 3 > + > + clock-names: > + minItems: 1 > + maxItems: 3 These are the 'top-level' definitions if that's not clear. > + > +required: > + - compatible > + - '#clock-cells' > + - reg > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + apb { > + #address-cells = <2>; > + #size-cells = <2>; > + > + clock-controller@8080 { > + compatible = "amlogic,t7-pll-gp0"; > + reg = <0 0x8080 0 0x20>; > + clocks = <&scmi_clk 2>; > + clock-names = "input"; > + #clock-cells = <1>; > + }; > + > + clock-controller@8300 { > + compatible = "amlogic,t7-pll-mclk"; > + reg = <0 0x8300 0 0x18>; > + clocks = <&scmi_clk 2>, > + <&xtal>, > + <&scmi_clk 31>; > + clock-names = "input", "mclk_in0", "mclk_in1"; > + #clock-cells = <1>; > + }; > + }; > diff --git a/include/dt-bindings/clock/amlogic,t7-pll-clkc.h b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h > new file mode 100644 > index 000000000000..e88c342028db > --- /dev/null > +++ b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h > @@ -0,0 +1,57 @@ > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ > +/* > + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. > + * Author: Jian Hu <jian.hu@amlogic.com> > + */ > + > +#ifndef __T7_PLL_CLKC_H > +#define __T7_PLL_CLKC_H > + > +/* GP0 */ > +#define CLKID_GP0_PLL_DCO 0 > +#define CLKID_GP0_PLL 1 > + > +/* GP1 */ > +#define CLKID_GP1_PLL_DCO 0 > +#define CLKID_GP1_PLL 1 > + > +/* HIFI */ > +#define CLKID_HIFI_PLL_DCO 0 > +#define CLKID_HIFI_PLL 1 > + > +/* PCIE */ > +#define CLKID_PCIE_PLL_DCO 0 > +#define CLKID_PCIE_PLL_DCO_DIV2 1 > +#define CLKID_PCIE_PLL_OD 2 > +#define CLKID_PCIE_PLL 3 > + > +/* MPLL */ > +#define CLKID_MPLL_PREDIV 0 > +#define CLKID_MPLL0_DIV 1 > +#define CLKID_MPLL0 2 > +#define CLKID_MPLL1_DIV 3 > +#define CLKID_MPLL1 4 > +#define CLKID_MPLL2_DIV 5 > +#define CLKID_MPLL2 6 > +#define CLKID_MPLL3_DIV 7 > +#define CLKID_MPLL3 8 > + > +/* HDMI */ > +#define CLKID_HDMI_PLL_DCO 0 > +#define CLKID_HDMI_PLL_OD 1 > +#define CLKID_HDMI_PLL 2 > + > +/* MCLK */ > +#define CLKID_MCLK_PLL_DCO 0 > +#define CLKID_MCLK_PRE 1 > +#define CLKID_MCLK_PLL 2 > +#define CLKID_MCLK_0_SEL 3 > +#define CLKID_MCLK_0_DIV2 4 > +#define CLKID_MCLK_0_PRE 5 > +#define CLKID_MCLK_0 6 > +#define CLKID_MCLK_1_SEL 7 > +#define CLKID_MCLK_1_DIV2 8 > +#define CLKID_MCLK_1_PRE 9 > +#define CLKID_MCLK_1 10 > + > +#endif /* __T7_PLL_CLKC_H */ > -- > 2.47.1 > ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 1/5] dt-bindings: clock: add Amlogic T7 PLL clock controller 2025-01-10 15:54 ` Rob Herring @ 2025-01-13 17:50 ` Jerome Brunet 2025-01-17 8:04 ` Jian Hu 2025-01-17 8:01 ` Jian Hu 1 sibling, 1 reply; 14+ messages in thread From: Jerome Brunet @ 2025-01-13 17:50 UTC (permalink / raw) To: Rob Herring Cc: Jian Hu, Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel On Fri 10 Jan 2025 at 09:54, Rob Herring <robh@kernel.org> wrote: > On Wed, Jan 08, 2025 at 05:40:21PM +0800, Jian Hu wrote: >> Add DT bindings for the PLL clock controller of the Amlogic T7 SoC family. >> >> Signed-off-by: Jian Hu <jian.hu@amlogic.com> >> --- >> .../bindings/clock/amlogic,t7-pll-clkc.yaml | 103 ++++++++++++++++++ >> .../dt-bindings/clock/amlogic,t7-pll-clkc.h | 57 ++++++++++ >> 2 files changed, 160 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml >> create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h >> >> diff --git >> a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml >> b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml >> new file mode 100644 >> index 000000000000..fd0323678d37 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml >> @@ -0,0 +1,103 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +# Copyright (C) 2024 Amlogic, Inc. All rights reserved >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Amlogic T7 PLL Clock Control Controller >> + >> +maintainers: >> + - Neil Armstrong <neil.armstrong@linaro.org> >> + - Jerome Brunet <jbrunet@baylibre.com> >> + - Jian Hu <jian.hu@amlogic.com> >> + - Xianwei Zhao <xianwei.zhao@amlogic.com> >> + >> +if: > > Move this after 'required' section. > > Generally we put 'if' under 'allOf' because we're likely to have another > if/then schema on the next compatible added. If you don't think this > binding will ever get used on another chip, then it is fine as-is. > >> + properties: >> + compatible: >> + contains: >> + const: amlogic,t7-pll-mclk >> + >> +then: >> + properties: >> + clocks: >> + items: >> + - description: mclk pll input oscillator gate >> + - description: 24M oscillator input clock source for mclk_sel_0 >> + - description: fix 50Mhz input clock source for mclk_sel_0 The rate is whatever the clock will actually be. Better not to mention it in this doc. >> + >> + clock-names: >> + items: one being "input" and other suffixed "_in" looks really odd >> + - const: input >> + - const: mclk_in0 >> + - const: mclk_in1 or just in0, in1, in2 if you are going with Rob's suggestion. Having "mclk_" in the top level would be confusing. > > Move these to top-level and then both of these are just 'minItems: 3'. > >> + >> +else: >> + properties: >> + clocks: >> + items: >> + - description: pll input oscillator gate >> + >> + clock-names: >> + items: >> + - const: input > > And 'maxItems: 1' here. > >> + >> +properties: >> + compatible: >> + enum: >> + - amlogic,t7-pll-gp0 >> + - amlogic,t7-pll-gp1 >> + - amlogic,t7-pll-hifi >> + - amlogic,t7-pll-pcie >> + - amlogic,t7-mpll >> + - amlogic,t7-pll-hdmi >> + - amlogic,t7-pll-mclk >> + >> + reg: >> + maxItems: 1 >> + >> + '#clock-cells': >> + const: 1 >> + >> + clocks: >> + minItems: 1 >> + maxItems: 3 >> + >> + clock-names: >> + minItems: 1 >> + maxItems: 3 > > These are the 'top-level' definitions if that's not clear. > >> + >> +required: >> + - compatible >> + - '#clock-cells' >> + - reg >> + - clocks >> + - clock-names >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + apb { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + clock-controller@8080 { >> + compatible = "amlogic,t7-pll-gp0"; >> + reg = <0 0x8080 0 0x20>; >> + clocks = <&scmi_clk 2>; >> + clock-names = "input"; >> + #clock-cells = <1>; >> + }; >> + >> + clock-controller@8300 { >> + compatible = "amlogic,t7-pll-mclk"; >> + reg = <0 0x8300 0 0x18>; >> + clocks = <&scmi_clk 2>, >> + <&xtal>, >> + <&scmi_clk 31>; >> + clock-names = "input", "mclk_in0", "mclk_in1"; >> + #clock-cells = <1>; >> + }; >> + }; >> diff --git a/include/dt-bindings/clock/amlogic,t7-pll-clkc.h b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h >> new file mode 100644 >> index 000000000000..e88c342028db >> --- /dev/null >> +++ b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h >> @@ -0,0 +1,57 @@ >> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ >> +/* >> + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. >> + * Author: Jian Hu <jian.hu@amlogic.com> >> + */ >> + >> +#ifndef __T7_PLL_CLKC_H >> +#define __T7_PLL_CLKC_H >> + >> +/* GP0 */ >> +#define CLKID_GP0_PLL_DCO 0 >> +#define CLKID_GP0_PLL 1 >> + >> +/* GP1 */ >> +#define CLKID_GP1_PLL_DCO 0 >> +#define CLKID_GP1_PLL 1 >> + >> +/* HIFI */ >> +#define CLKID_HIFI_PLL_DCO 0 >> +#define CLKID_HIFI_PLL 1 >> + >> +/* PCIE */ >> +#define CLKID_PCIE_PLL_DCO 0 >> +#define CLKID_PCIE_PLL_DCO_DIV2 1 >> +#define CLKID_PCIE_PLL_OD 2 >> +#define CLKID_PCIE_PLL 3 >> + >> +/* MPLL */ >> +#define CLKID_MPLL_PREDIV 0 >> +#define CLKID_MPLL0_DIV 1 >> +#define CLKID_MPLL0 2 >> +#define CLKID_MPLL1_DIV 3 >> +#define CLKID_MPLL1 4 >> +#define CLKID_MPLL2_DIV 5 >> +#define CLKID_MPLL2 6 >> +#define CLKID_MPLL3_DIV 7 >> +#define CLKID_MPLL3 8 >> + >> +/* HDMI */ >> +#define CLKID_HDMI_PLL_DCO 0 >> +#define CLKID_HDMI_PLL_OD 1 >> +#define CLKID_HDMI_PLL 2 >> + >> +/* MCLK */ >> +#define CLKID_MCLK_PLL_DCO 0 >> +#define CLKID_MCLK_PRE 1 >> +#define CLKID_MCLK_PLL 2 >> +#define CLKID_MCLK_0_SEL 3 >> +#define CLKID_MCLK_0_DIV2 4 >> +#define CLKID_MCLK_0_PRE 5 >> +#define CLKID_MCLK_0 6 >> +#define CLKID_MCLK_1_SEL 7 >> +#define CLKID_MCLK_1_DIV2 8 >> +#define CLKID_MCLK_1_PRE 9 >> +#define CLKID_MCLK_1 10 >> + >> +#endif /* __T7_PLL_CLKC_H */ >> -- >> 2.47.1 >> -- Jerome ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 1/5] dt-bindings: clock: add Amlogic T7 PLL clock controller 2025-01-13 17:50 ` Jerome Brunet @ 2025-01-17 8:04 ` Jian Hu 0 siblings, 0 replies; 14+ messages in thread From: Jian Hu @ 2025-01-17 8:04 UTC (permalink / raw) To: Jerome Brunet, Rob Herring Cc: Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel Hi, Jerome Thanks for your review. On 2025/1/14 1:50, Jerome Brunet wrote: > [ EXTERNAL EMAIL ] > > On Fri 10 Jan 2025 at 09:54, Rob Herring <robh@kernel.org> wrote: > >> On Wed, Jan 08, 2025 at 05:40:21PM +0800, Jian Hu wrote: >>> Add DT bindings for the PLL clock controller of the Amlogic T7 SoC family. >>> >>> Signed-off-by: Jian Hu <jian.hu@amlogic.com> >>> --- >>> .../bindings/clock/amlogic,t7-pll-clkc.yaml | 103 ++++++++++++++++++ >>> .../dt-bindings/clock/amlogic,t7-pll-clkc.h | 57 ++++++++++ >>> 2 files changed, 160 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml >>> create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h >>> >>> diff --git >>> a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml >>> b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml >>> new file mode 100644 >>> index 000000000000..fd0323678d37 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml >>> @@ -0,0 +1,103 @@ >>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >>> +# Copyright (C) 2024 Amlogic, Inc. All rights reserved >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Amlogic T7 PLL Clock Control Controller >>> + >>> +maintainers: >>> + - Neil Armstrong <neil.armstrong@linaro.org> >>> + - Jerome Brunet <jbrunet@baylibre.com> >>> + - Jian Hu <jian.hu@amlogic.com> >>> + - Xianwei Zhao <xianwei.zhao@amlogic.com> >>> + >>> +if: >> Move this after 'required' section. >> >> Generally we put 'if' under 'allOf' because we're likely to have another >> if/then schema on the next compatible added. If you don't think this >> binding will ever get used on another chip, then it is fine as-is. >> >>> + properties: >>> + compatible: >>> + contains: >>> + const: amlogic,t7-pll-mclk >>> + >>> +then: >>> + properties: >>> + clocks: >>> + items: >>> + - description: mclk pll input oscillator gate >>> + - description: 24M oscillator input clock source for mclk_sel_0 >>> + - description: fix 50Mhz input clock source for mclk_sel_0 > The rate is whatever the clock will actually be. Better not to mention > it in this doc. OK, I will remove the rate here. >>> + >>> + clock-names: >>> + items: > one being "input" and other suffixed "_in" looks really odd > >>> + - const: input >>> + - const: mclk_in0 >>> + - const: mclk_in1 > or just in0, in1, in2 if you are going with Rob's suggestion. > Having "mclk_" in the top level would be confusing. Ok, I will use in0/in1/in2 for them. > -- > 2.47.1 > > -- > Jerome ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 1/5] dt-bindings: clock: add Amlogic T7 PLL clock controller 2025-01-10 15:54 ` Rob Herring 2025-01-13 17:50 ` Jerome Brunet @ 2025-01-17 8:01 ` Jian Hu 1 sibling, 0 replies; 14+ messages in thread From: Jian Hu @ 2025-01-17 8:01 UTC (permalink / raw) To: Rob Herring Cc: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel Hi, Rob Thanks for your review On 2025/1/10 23:54, Rob Herring wrote: > [ EXTERNAL EMAIL ] > > On Wed, Jan 08, 2025 at 05:40:21PM +0800, Jian Hu wrote: >> Add DT bindings for the PLL clock controller of the Amlogic T7 SoC family. >> >> Signed-off-by: Jian Hu <jian.hu@amlogic.com> >> --- >> .../bindings/clock/amlogic,t7-pll-clkc.yaml | 103 ++++++++++++++++++ >> .../dt-bindings/clock/amlogic,t7-pll-clkc.h | 57 ++++++++++ >> 2 files changed, 160 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml >> create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h >> >> diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml >> new file mode 100644 >> index 000000000000..fd0323678d37 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml >> @@ -0,0 +1,103 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +# Copyright (C) 2024 Amlogic, Inc. All rights reserved >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Amlogic T7 PLL Clock Control Controller >> + >> +maintainers: >> + - Neil Armstrong <neil.armstrong@linaro.org> >> + - Jerome Brunet <jbrunet@baylibre.com> >> + - Jian Hu <jian.hu@amlogic.com> >> + - Xianwei Zhao <xianwei.zhao@amlogic.com> >> + >> +if: > Move this after 'required' section. > > Generally we put 'if' under 'allOf' because we're likely to have another > if/then schema on the next compatible added. If you don't think this > binding will ever get used on another chip, then it is fine as-is. OK, I will move 'if' after 'required'. and add two 'if' for them. >> + properties: >> + compatible: >> + contains: >> + const: amlogic,t7-pll-mclk >> + >> +then: >> + properties: >> + clocks: >> + items: >> + - description: mclk pll input oscillator gate >> + - description: 24M oscillator input clock source for mclk_sel_0 >> + - description: fix 50Mhz input clock source for mclk_sel_0 >> + >> + clock-names: >> + items: >> + - const: input >> + - const: mclk_in0 >> + - const: mclk_in1 > Move these to top-level and then both of these are just 'minItems: 3'. Ok. >> + >> +else: >> + properties: >> + clocks: >> + items: >> + - description: pll input oscillator gate >> + >> + clock-names: >> + items: >> + - const: input > And 'maxItems: 1' here. Ok. > >> + >> +properties: >> + compatible: >> + enum: >> + - amlogic,t7-pll-gp0 >> + - amlogic,t7-pll-gp1 >> + - amlogic,t7-pll-hifi >> + - amlogic,t7-pll-pcie >> + - amlogic,t7-mpll >> + - amlogic,t7-pll-hdmi >> + - amlogic,t7-pll-mclk >> + >> + reg: >> + maxItems: 1 >> + >> + '#clock-cells': >> + const: 1 >> + >> + clocks: >> + minItems: 1 >> + maxItems: 3 >> + >> + clock-names: >> + minItems: 1 >> + maxItems: 3 > These are the 'top-level' definitions if that's not clear. Ok, I will put it in the top. >> + >> +required: >> + - compatible >> + - '#clock-cells' >> + - reg >> + - clocks >> + - clock-names >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + apb { >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + clock-controller@8080 { >> + compatible = "amlogic,t7-pll-gp0"; >> + reg = <0 0x8080 0 0x20>; >> + clocks = <&scmi_clk 2>; >> + clock-names = "input"; >> + #clock-cells = <1>; >> + }; >> + >> + clock-controller@8300 { >> + compatible = "amlogic,t7-pll-mclk"; >> + reg = <0 0x8300 0 0x18>; >> + clocks = <&scmi_clk 2>, >> + <&xtal>, >> + <&scmi_clk 31>; >> + clock-names = "input", "mclk_in0", "mclk_in1"; >> + #clock-cells = <1>; >> + }; >> + }; >> diff --git a/include/dt-bindings/clock/amlogic,t7-pll-clkc.h b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h >> new file mode 100644 >> index 000000000000..e88c342028db >> --- /dev/null >> +++ b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h >> @@ -0,0 +1,57 @@ >> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ >> +/* >> + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. >> + * Author: Jian Hu <jian.hu@amlogic.com> >> + */ >> + >> +#ifndef __T7_PLL_CLKC_H >> +#define __T7_PLL_CLKC_H >> + >> +/* GP0 */ >> +#define CLKID_GP0_PLL_DCO 0 >> +#define CLKID_GP0_PLL 1 >> + >> +/* GP1 */ >> +#define CLKID_GP1_PLL_DCO 0 >> +#define CLKID_GP1_PLL 1 >> + >> +/* HIFI */ >> +#define CLKID_HIFI_PLL_DCO 0 >> +#define CLKID_HIFI_PLL 1 >> + >> +/* PCIE */ >> +#define CLKID_PCIE_PLL_DCO 0 >> +#define CLKID_PCIE_PLL_DCO_DIV2 1 >> +#define CLKID_PCIE_PLL_OD 2 >> +#define CLKID_PCIE_PLL 3 >> + >> +/* MPLL */ >> +#define CLKID_MPLL_PREDIV 0 >> +#define CLKID_MPLL0_DIV 1 >> +#define CLKID_MPLL0 2 >> +#define CLKID_MPLL1_DIV 3 >> +#define CLKID_MPLL1 4 >> +#define CLKID_MPLL2_DIV 5 >> +#define CLKID_MPLL2 6 >> +#define CLKID_MPLL3_DIV 7 >> +#define CLKID_MPLL3 8 >> + >> +/* HDMI */ >> +#define CLKID_HDMI_PLL_DCO 0 >> +#define CLKID_HDMI_PLL_OD 1 >> +#define CLKID_HDMI_PLL 2 >> + >> +/* MCLK */ >> +#define CLKID_MCLK_PLL_DCO 0 >> +#define CLKID_MCLK_PRE 1 >> +#define CLKID_MCLK_PLL 2 >> +#define CLKID_MCLK_0_SEL 3 >> +#define CLKID_MCLK_0_DIV2 4 >> +#define CLKID_MCLK_0_PRE 5 >> +#define CLKID_MCLK_0 6 >> +#define CLKID_MCLK_1_SEL 7 >> +#define CLKID_MCLK_1_DIV2 8 >> +#define CLKID_MCLK_1_PRE 9 >> +#define CLKID_MCLK_1 10 >> + >> +#endif /* __T7_PLL_CLKC_H */ >> -- >> 2.47.1 >> ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 2/5] dt-bindings: clock: add Amlogic T7 SCMI clock controller 2025-01-08 9:40 [PATCH v2 0/5] add support for T7 family clock controller Jian Hu 2025-01-08 9:40 ` [PATCH v2 1/5] dt-bindings: clock: add Amlogic T7 PLL " Jian Hu @ 2025-01-08 9:40 ` Jian Hu 2025-01-08 9:40 ` [PATCH v2 3/5] dt-bindings: clock: add Amlogic T7 peripherals " Jian Hu ` (2 subsequent siblings) 4 siblings, 0 replies; 14+ messages in thread From: Jian Hu @ 2025-01-08 9:40 UTC (permalink / raw) To: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring Cc: Jian Hu, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel Add DT bindings for the SCMI clock controller of the Amlogic T7 SoC family. Signed-off-by: Jian Hu <jian.hu@amlogic.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> --- include/dt-bindings/clock/amlogic,t7-scmi.h | 48 +++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 include/dt-bindings/clock/amlogic,t7-scmi.h diff --git a/include/dt-bindings/clock/amlogic,t7-scmi.h b/include/dt-bindings/clock/amlogic,t7-scmi.h new file mode 100644 index 000000000000..aa2431ea72ed --- /dev/null +++ b/include/dt-bindings/clock/amlogic,t7-scmi.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + * Author: Jian Hu <jian.hu@amlogic.com> + */ + +#ifndef __T7_SCMI_CLKC_H +#define __T7_SCMI_CLKC_H + +#define CLKID_DDR_PLL_OSC 0 +#define CLKID_AUD_PLL_OSC 1 +#define CLKID_TOP_PLL_OSC 2 +#define CLKID_TCON_PLL_OSC 3 +#define CLKID_USB_PLL0_OSC 4 +#define CLKID_USB_PLL1_OSC 5 +#define CLKID_MCLK_PLL_OSC 6 +#define CLKID_PCIE_OSC 7 +#define CLKID_ETH_PLL_OSC 8 +#define CLKID_PCIE_REFCLK_PLL_OSC 9 +#define CLKID_EARC_OSC 10 +#define CLKID_SYS1_PLL_OSC 11 +#define CLKID_HDMI_PLL_OSC 12 +#define CLKID_SYS_CLK 13 +#define CLKID_AXI_CLK 14 +#define CLKID_FIXED_PLL_DCO 15 +#define CLKID_FIXED_PLL 16 +#define CLKID_FCLK_DIV2_DIV 17 +#define CLKID_FCLK_DIV2 18 +#define CLKID_FCLK_DIV2P5_DIV 19 +#define CLKID_FCLK_DIV2P5 20 +#define CLKID_FCLK_DIV3_DIV 21 +#define CLKID_FCLK_DIV3 22 +#define CLKID_FCLK_DIV4_DIV 23 +#define CLKID_FCLK_DIV4 24 +#define CLKID_FCLK_DIV5_DIV 25 +#define CLKID_FCLK_DIV5 26 +#define CLKID_FCLK_DIV7_DIV 27 +#define CLKID_FCLK_DIV7 28 +#define CLKID_FCLK_50M_DIV 29 +#define CLKID_FCLK_50M 30 +#define CLKID_CPU_CLK 31 +#define CLKID_A73_CLK 32 +#define CLKID_CPU_CLK_DIV16_DIV 33 +#define CLKID_CPU_CLK_DIV16 34 +#define CLKID_A73_CLK_DIV16_DIV 35 +#define CLKID_A73_CLK_DIV16 36 + +#endif /* __T7_SCMI_CLKC_H */ -- 2.47.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 3/5] dt-bindings: clock: add Amlogic T7 peripherals clock controller 2025-01-08 9:40 [PATCH v2 0/5] add support for T7 family clock controller Jian Hu 2025-01-08 9:40 ` [PATCH v2 1/5] dt-bindings: clock: add Amlogic T7 PLL " Jian Hu 2025-01-08 9:40 ` [PATCH v2 2/5] dt-bindings: clock: add Amlogic T7 SCMI " Jian Hu @ 2025-01-08 9:40 ` Jian Hu 2025-01-08 9:40 ` [PATCH v2 4/5] clk: meson: t7: add support for the T7 SoC PLL clock Jian Hu 2025-01-08 9:40 ` [PATCH v2 5/5] clk: meson: t7: add t7 clock peripherals controller driver Jian Hu 4 siblings, 0 replies; 14+ messages in thread From: Jian Hu @ 2025-01-08 9:40 UTC (permalink / raw) To: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring Cc: Jian Hu, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel Add DT bindings for the peripheral clock controller of the Amlogic T7 SoC family. Signed-off-by: Jian Hu <jian.hu@amlogic.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> --- .../clock/amlogic,t7-peripherals-clkc.yaml | 111 +++++++++ .../clock/amlogic,t7-peripherals-clkc.h | 231 ++++++++++++++++++ 2 files changed, 342 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml create mode 100644 include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml new file mode 100644 index 000000000000..eba24937defd --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,t7-peripherals-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic T7 Peripherals Clock Controller + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + - Jerome Brunet <jbrunet@baylibre.com> + - Xianwei Zhao <xianwei.zhao@amlogic.com> + - Jian Hu <jian.hu@amlogic.com> + +properties: + compatible: + const: amlogic,t7-peripherals-clkc + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + minItems: 13 + items: + - description: input oscillator + - description: input sys clk + - description: input fclk div 2 + - description: input fclk div 2p5 + - description: input fclk div 3 + - description: input fclk div 4 + - description: input fclk div 5 + - description: input fclk div 7 + - description: input hifi pll + - description: input gp0 pll + - description: input gp1 pll + - description: input mpll1 + - description: input mpll2 + - description: external input rmii oscillator (optional) + - description: input video pll0 (optional) + - description: external pad input for rtc (optional) + + clock-names: + minItems: 13 + items: + - const: xtal + - const: sys + - const: fdiv2 + - const: fdiv2p5 + - const: fdiv3 + - const: fdiv4 + - const: fdiv5 + - const: fdiv7 + - const: hifi + - const: gp0 + - const: gp1 + - const: mpll1 + - const: mpll2 + - const: ext_rmii + - const: vid_pll0 + - const: ext_rtc + +required: + - compatible + - '#clock-cells' + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + apb { + #address-cells = <2>; + #size-cells = <2>; + + clkc_periphs:clock-controller@0 { + compatible = "amlogic,t7-peripherals-clkc"; + reg = <0 0x0 0 0x1c8>; + #clock-cells = <1>; + clocks = <&xtal>, + <&scmi_clk 13>, + <&scmi_clk 18>, + <&scmi_clk 20>, + <&scmi_clk 22>, + <&scmi_clk 24>, + <&scmi_clk 26>, + <&scmi_clk 28>, + <&hifi 1>, + <&gp0 1>, + <&gp1 1>, + <&mpll 4>, + <&mpll 6>; + clock-names = "xtal", + "sys", + "fdiv2", + "fdiv2p5", + "fdiv3", + "fdiv4", + "fdiv5", + "fdiv7", + "hifi", + "gp0", + "gp1", + "mpll1", + "mpll2"; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h new file mode 100644 index 000000000000..703d7bb6f2ca --- /dev/null +++ b/include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h @@ -0,0 +1,231 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) 2023 Amlogic, Inc. All rights reserved. + * Author: Jian Hu <jian.hu@amlogic.com> + */ + +#ifndef __T7_PERIPHERALS_CLKC_H +#define __T7_PERIPHERALS_CLKC_H + +#define CLKID_RTC_32K_IN 0 +#define CLKID_RTC_32K_DIV 1 +#define CLKID_RTC_32K_FORCE_SEL 2 +#define CLKID_RTC_32K_OUT 3 +#define CLKID_RTC_32K_MUX0_0 4 +#define CLKID_RTC_32K_MUX0_1 5 +#define CLKID_RTC 6 +#define CLKID_CECB_32K_IN 7 +#define CLKID_CECB_32K_DIV 8 +#define CLKID_CECB_32K_SEL_PRE 9 +#define CLKID_CECB_32K_SEL 10 +#define CLKID_CECA_32K_IN 11 +#define CLKID_CECA_32K_DIV 12 +#define CLKID_CECA_32K_SEL_PRE 13 +#define CLKID_CECA_32K_SEL 14 +#define CLKID_CECA_32K 15 +#define CLKID_CECB_32K 16 +#define CLKID_SC_SEL 17 +#define CLKID_SC_DIV 18 +#define CLKID_SC 19 +#define CLKID_DSPA_A_SEL 20 +#define CLKID_DSPA_A_DIV 21 +#define CLKID_DSPA_A 22 +#define CLKID_DSPA_B_SEL 23 +#define CLKID_DSPA_B_DIV 24 +#define CLKID_DSPA_B 25 +#define CLKID_DSPA 26 +#define CLKID_DSPB_A_SEL 27 +#define CLKID_DSPB_A_DIV 28 +#define CLKID_DSPB_A 29 +#define CLKID_DSPB_B_SEL 30 +#define CLKID_DSPB_B_DIV 31 +#define CLKID_DSPB_B 32 +#define CLKID_DSPB 33 +#define CLKID_CLK_24M 34 +#define CLKID_CLK_24M_DIV2 35 +#define CLKID_CLK_12M 36 +#define CLKID_ANAKIN_0_SEL 37 +#define CLKID_ANAKIN_0_DIV 38 +#define CLKID_ANAKIN_0 39 +#define CLKID_ANAKIN_1_SEL 40 +#define CLKID_ANAKIN_1_DIV 41 +#define CLKID_ANAKIN_1 42 +#define CLKID_ANAKIN 43 +#define CLKID_ANAKIN_CLK 44 +#define CLKID_FCLK_DIV2_DIVN_PRE 45 +#define CLKID_FCLK_DIV2_DIVN 46 +#define CLKID_TS_DIV 47 +#define CLKID_TS 48 +#define CLKID_MIPI_CSI_PHY_0_SEL 49 +#define CLKID_MIPI_CSI_PHY_0_DIV 50 +#define CLKID_MIPI_CSI_PHY_0 51 +#define CLKID_MIPI_CSI_PHY_1_SEL 52 +#define CLKID_MIPI_CSI_PHY_1_DIV 53 +#define CLKID_MIPI_CSI_PHY_1 54 +#define CLKID_MIPI_CSI_PHY 55 +#define CLKID_MIPI_ISP_SEL 56 +#define CLKID_MIPI_ISP_DIV 57 +#define CLKID_MIPI_ISP 58 +#define CLKID_MALI_0_SEL 59 +#define CLKID_MALI_0_DIV 60 +#define CLKID_MALI_0 61 +#define CLKID_MALI_1_SEL 62 +#define CLKID_MALI_1_DIV 63 +#define CLKID_MALI_1 64 +#define CLKID_MALI 65 +#define CLKID_ETH_RMII_SEL 66 +#define CLKID_ETH_RMII_DIV 67 +#define CLKID_ETH_RMII 68 +#define CLKID_FCLK_DIV2_DIV8 69 +#define CLKID_ETH_125M 70 +#define CLKID_SD_EMMC_C_SEL 71 +#define CLKID_SD_EMMC_C_DIV 72 +#define CLKID_SD_EMMC_C 73 +#define CLKID_SD_EMMC_A_SEL 74 +#define CLKID_SD_EMMC_A_DIV 75 +#define CLKID_SD_EMMC_A 76 +#define CLKID_SD_EMMC_B_SEL 77 +#define CLKID_SD_EMMC_B_DIV 78 +#define CLKID_SD_EMMC_B 79 +#define CLKID_SPICC0_SEL 80 +#define CLKID_SPICC0_DIV 81 +#define CLKID_SPICC0 82 +#define CLKID_SPICC1_SEL 83 +#define CLKID_SPICC1_DIV 84 +#define CLKID_SPICC1 85 +#define CLKID_SPICC2_SEL 86 +#define CLKID_SPICC2_DIV 87 +#define CLKID_SPICC2 88 +#define CLKID_SPICC3_SEL 89 +#define CLKID_SPICC3_DIV 90 +#define CLKID_SPICC3 91 +#define CLKID_SPICC4_SEL 92 +#define CLKID_SPICC4_DIV 93 +#define CLKID_SPICC4 94 +#define CLKID_SPICC5_SEL 95 +#define CLKID_SPICC5_DIV 96 +#define CLKID_SPICC5 97 +#define CLKID_SARADC_SEL 98 +#define CLKID_SARADC_DIV 99 +#define CLKID_SARADC 100 +#define CLKID_PWM_A_SEL 101 +#define CLKID_PWM_A_DIV 102 +#define CLKID_PWM_A 103 +#define CLKID_PWM_B_SEL 104 +#define CLKID_PWM_B_DIV 105 +#define CLKID_PWM_B 106 +#define CLKID_PWM_C_SEL 107 +#define CLKID_PWM_C_DIV 108 +#define CLKID_PWM_C 109 +#define CLKID_PWM_D_SEL 110 +#define CLKID_PWM_D_DIV 111 +#define CLKID_PWM_D 112 +#define CLKID_PWM_E_SEL 113 +#define CLKID_PWM_E_DIV 114 +#define CLKID_PWM_E 115 +#define CLKID_PWM_F_SEL 116 +#define CLKID_PWM_F_DIV 117 +#define CLKID_PWM_F 118 +#define CLKID_PWM_AO_A_SEL 119 +#define CLKID_PWM_AO_A_DIV 120 +#define CLKID_PWM_AO_A 121 +#define CLKID_PWM_AO_B_SEL 122 +#define CLKID_PWM_AO_B_DIV 123 +#define CLKID_PWM_AO_B 124 +#define CLKID_PWM_AO_C_SEL 125 +#define CLKID_PWM_AO_C_DIV 126 +#define CLKID_PWM_AO_C 127 +#define CLKID_PWM_AO_D_SEL 128 +#define CLKID_PWM_AO_D_DIV 129 +#define CLKID_PWM_AO_D 130 +#define CLKID_PWM_AO_E_SEL 131 +#define CLKID_PWM_AO_E_DIV 132 +#define CLKID_PWM_AO_E 133 +#define CLKID_PWM_AO_F_SEL 134 +#define CLKID_PWM_AO_F_DIV 135 +#define CLKID_PWM_AO_F 136 +#define CLKID_PWM_AO_G_SEL 137 +#define CLKID_PWM_AO_G_DIV 138 +#define CLKID_PWM_AO_G 139 +#define CLKID_PWM_AO_H_SEL 140 +#define CLKID_PWM_AO_H_DIV 141 +#define CLKID_PWM_AO_H 142 +#define CLKID_SYS_DDR 143 +#define CLKID_SYS_DOS 144 +#define CLKID_SYS_MIPI_DSI_A 145 +#define CLKID_SYS_MIPI_DSI_B 146 +#define CLKID_SYS_ETHPHY 147 +#define CLKID_SYS_MALI 148 +#define CLKID_SYS_AOCPU 149 +#define CLKID_SYS_AUCPU 150 +#define CLKID_SYS_CEC 151 +#define CLKID_SYS_GDC 152 +#define CLKID_SYS_DESWARP 153 +#define CLKID_SYS_AMPIPE_NAND 154 +#define CLKID_SYS_AMPIPE_ETH 155 +#define CLKID_SYS_AM2AXI0 156 +#define CLKID_SYS_AM2AXI1 157 +#define CLKID_SYS_AM2AXI2 158 +#define CLKID_SYS_SD_EMMC_A 159 +#define CLKID_SYS_SD_EMMC_B 160 +#define CLKID_SYS_SD_EMMC_C 161 +#define CLKID_SYS_SMARTCARD 162 +#define CLKID_SYS_ACODEC 163 +#define CLKID_SYS_SPIFC 164 +#define CLKID_SYS_MSR_CLK 165 +#define CLKID_SYS_IR_CTRL 166 +#define CLKID_SYS_AUDIO 167 +#define CLKID_SYS_ETH 168 +#define CLKID_SYS_UART_A 169 +#define CLKID_SYS_UART_B 170 +#define CLKID_SYS_UART_C 171 +#define CLKID_SYS_UART_D 172 +#define CLKID_SYS_UART_E 173 +#define CLKID_SYS_UART_F 174 +#define CLKID_SYS_AIFIFO 175 +#define CLKID_SYS_SPICC2 176 +#define CLKID_SYS_SPICC3 177 +#define CLKID_SYS_SPICC4 178 +#define CLKID_SYS_TS_A73 179 +#define CLKID_SYS_TS_A53 180 +#define CLKID_SYS_SPICC5 181 +#define CLKID_SYS_G2D 182 +#define CLKID_SYS_SPICC0 183 +#define CLKID_SYS_SPICC1 184 +#define CLKID_SYS_PCIE 185 +#define CLKID_SYS_USB 186 +#define CLKID_SYS_PCIE_PHY 187 +#define CLKID_SYS_I2C_AO_A 188 +#define CLKID_SYS_I2C_AO_B 189 +#define CLKID_SYS_I2C_M_A 190 +#define CLKID_SYS_I2C_M_B 191 +#define CLKID_SYS_I2C_M_C 192 +#define CLKID_SYS_I2C_M_D 193 +#define CLKID_SYS_I2C_M_E 194 +#define CLKID_SYS_I2C_M_F 195 +#define CLKID_SYS_HDMITX_APB 196 +#define CLKID_SYS_I2C_S_A 197 +#define CLKID_SYS_HDMIRX_PCLK 198 +#define CLKID_SYS_MMC_APB 199 +#define CLKID_SYS_MIPI_ISP_PCLK 200 +#define CLKID_SYS_RSA 201 +#define CLKID_SYS_PCLK_SYS_APB 202 +#define CLKID_SYS_A73PCLK_APB 203 +#define CLKID_SYS_DSPA 204 +#define CLKID_SYS_DSPB 205 +#define CLKID_SYS_VPU_INTR 206 +#define CLKID_SYS_SAR_ADC 207 +#define CLKID_SYS_GIC 208 +#define CLKID_SYS_TS_GPU 209 +#define CLKID_SYS_TS_NNA 210 +#define CLKID_SYS_TS_VPU 211 +#define CLKID_SYS_TS_HEVC 212 +#define CLKID_SYS_PWM_AB 213 +#define CLKID_SYS_PWM_CD 214 +#define CLKID_SYS_PWM_EF 215 +#define CLKID_SYS_PWM_AO_AB 216 +#define CLKID_SYS_PWM_AO_CD 217 +#define CLKID_SYS_PWM_AO_EF 218 +#define CLKID_SYS_PWM_AO_GH 219 + +#endif /* __T7_PERIPHERALS_CLKC_H */ -- 2.47.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 4/5] clk: meson: t7: add support for the T7 SoC PLL clock 2025-01-08 9:40 [PATCH v2 0/5] add support for T7 family clock controller Jian Hu ` (2 preceding siblings ...) 2025-01-08 9:40 ` [PATCH v2 3/5] dt-bindings: clock: add Amlogic T7 peripherals " Jian Hu @ 2025-01-08 9:40 ` Jian Hu 2025-01-13 18:05 ` Jerome Brunet 2025-01-08 9:40 ` [PATCH v2 5/5] clk: meson: t7: add t7 clock peripherals controller driver Jian Hu 4 siblings, 1 reply; 14+ messages in thread From: Jian Hu @ 2025-01-08 9:40 UTC (permalink / raw) To: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring Cc: Jian Hu, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel Add PLL clock controller driver for the Amlogic T7 SoC family. Signed-off-by: Jian Hu <jian.hu@amlogic.com> --- drivers/clk/meson/Kconfig | 14 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/t7-pll.c | 1193 ++++++++++++++++++++++++++++++++++++ 3 files changed, 1208 insertions(+) create mode 100644 drivers/clk/meson/t7-pll.c diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 78f648c9c97d..6878b035a7ac 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -201,4 +201,18 @@ config COMMON_CLK_S4_PERIPHERALS help Support for the peripherals clock controller on Amlogic S805X2 and S905Y4 devices, AKA S4. Say Y if you want S4 peripherals clock controller to work. + +config COMMON_CLK_T7_PLL + tristate "Amlogic T7 SoC PLL controller support" + depends on ARM64 + default y + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_CLKC_UTILS + select COMMON_CLK_MESON_PLL + imply COMMON_CLK_SCMI + help + Support for the PLL clock controller on Amlogic A311D2 based + device, AKA T7. PLLs are required by most peripheral to operate + Say Y if you are a T7 based device. + endmenu diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index bc56a47931c1..646257694c34 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -27,3 +27,4 @@ obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) += s4-peripherals.o +obj-$(CONFIG_COMMON_CLK_T7_PLL) += t7-pll.o diff --git a/drivers/clk/meson/t7-pll.c b/drivers/clk/meson/t7-pll.c new file mode 100644 index 000000000000..a6113b7dfe11 --- /dev/null +++ b/drivers/clk/meson/t7-pll.c @@ -0,0 +1,1193 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + * Author: Jian Hu <jian.hu@amlogic.com> + */ + +#include <linux/clk-provider.h> +#include <linux/platform_device.h> +#include "clk-regmap.h" +#include "clk-pll.h" +#include "clk-mpll.h" +#include "meson-clkc-utils.h" +#include "meson-eeclk.h" +#include <dt-bindings/clock/amlogic,t7-pll-clkc.h> + +#define ANACTRL_GP0PLL_CTRL0 0x00 +#define ANACTRL_GP0PLL_CTRL1 0x04 +#define ANACTRL_GP0PLL_CTRL2 0x08 +#define ANACTRL_GP0PLL_CTRL3 0x0c +#define ANACTRL_GP0PLL_CTRL4 0x10 +#define ANACTRL_GP0PLL_CTRL5 0x14 +#define ANACTRL_GP0PLL_CTRL6 0x18 +#define ANACTRL_GP0PLL_STS 0x1c + +#define ANACTRL_GP1PLL_CTRL0 0x00 +#define ANACTRL_GP1PLL_CTRL1 0x04 +#define ANACTRL_GP1PLL_CTRL2 0x08 +#define ANACTRL_GP1PLL_CTRL3 0x0c +#define ANACTRL_GP1PLL_STS 0x1c + +#define ANACTRL_HIFIPLL_CTRL0 0x00 +#define ANACTRL_HIFIPLL_CTRL1 0x04 +#define ANACTRL_HIFIPLL_CTRL2 0x08 +#define ANACTRL_HIFIPLL_CTRL3 0x0c +#define ANACTRL_HIFIPLL_CTRL4 0x10 +#define ANACTRL_HIFIPLL_CTRL5 0x14 +#define ANACTRL_HIFIPLL_CTRL6 0x18 +#define ANACTRL_HIFIPLL_STS 0x1c + +#define ANACTRL_PCIEPLL_CTRL0 0x00 +#define ANACTRL_PCIEPLL_CTRL1 0x04 +#define ANACTRL_PCIEPLL_CTRL2 0x08 +#define ANACTRL_PCIEPLL_CTRL3 0x0c +#define ANACTRL_PCIEPLL_CTRL4 0x10 +#define ANACTRL_PCIEPLL_CTRL5 0x14 +#define ANACTRL_PCIEPLL_STS 0x18 + +#define ANACTRL_MPLL_CTRL0 0x00 +#define ANACTRL_MPLL_CTRL1 0x04 +#define ANACTRL_MPLL_CTRL2 0x08 +#define ANACTRL_MPLL_CTRL3 0x0c +#define ANACTRL_MPLL_CTRL4 0x10 +#define ANACTRL_MPLL_CTRL5 0x14 +#define ANACTRL_MPLL_CTRL6 0x18 +#define ANACTRL_MPLL_CTRL7 0x1c +#define ANACTRL_MPLL_CTRL8 0x20 +#define ANACTRL_MPLL_STS 0x24 + +#define ANACTRL_HDMIPLL_CTRL0 0x00 +#define ANACTRL_HDMIPLL_CTRL1 0x04 +#define ANACTRL_HDMIPLL_CTRL2 0x08 +#define ANACTRL_HDMIPLL_CTRL3 0x0c +#define ANACTRL_HDMIPLL_CTRL4 0x10 +#define ANACTRL_HDMIPLL_CTRL5 0x14 +#define ANACTRL_HDMIPLL_CTRL6 0x18 +#define ANACTRL_HDMIPLL_STS 0x1c + +#define ANACTRL_MCLK_PLL_CNTL0 0x00 +#define ANACTRL_MCLK_PLL_CNTL1 0x04 +#define ANACTRL_MCLK_PLL_CNTL2 0x08 +#define ANACTRL_MCLK_PLL_CNTL3 0x0c +#define ANACTRL_MCLK_PLL_CNTL4 0x10 +#define ANACTRL_MCLK_PLL_STS 0x14 + +static const struct pll_mult_range media_pll_mult_range = { + .min = 125, + .max = 250, +}; + +static const struct reg_sequence gp0_init_regs[] = { + { .reg = ANACTRL_GP0PLL_CTRL1, .def = 0x00000000 }, + { .reg = ANACTRL_GP0PLL_CTRL2, .def = 0x00000000 }, + { .reg = ANACTRL_GP0PLL_CTRL3, .def = 0x48681c00 }, + { .reg = ANACTRL_GP0PLL_CTRL4, .def = 0x88770290 }, + { .reg = ANACTRL_GP0PLL_CTRL5, .def = 0x3927200a }, + { .reg = ANACTRL_GP0PLL_CTRL6, .def = 0x56540000 }, +}; + +static struct clk_regmap gp0_pll_dco = { + .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = ANACTRL_GP0PLL_CTRL0, + .shift = 28, + .width = 1, + }, + .m = { + .reg_off = ANACTRL_GP0PLL_CTRL0, + .shift = 0, + .width = 8, + }, + .n = { + .reg_off = ANACTRL_GP0PLL_CTRL0, + .shift = 10, + .width = 5, + }, + .l = { + .reg_off = ANACTRL_GP0PLL_STS, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = ANACTRL_GP0PLL_CTRL0, + .shift = 29, + .width = 1, + }, + .range = &media_pll_mult_range, + .init_regs = gp0_init_regs, + .init_count = ARRAY_SIZE(gp0_init_regs), + }, + .hw.init = &(struct clk_init_data){ + .name = "gp0_pll_dco", + .ops = &meson_clk_pll_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "input", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap gp0_pll = { + .data = &(struct clk_regmap_div_data){ + .offset = ANACTRL_GP0PLL_CTRL0, + .shift = 16, + .width = 3, + .flags = CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init = &(struct clk_init_data) { + .name = "gp0_pll", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &gp0_pll_dco.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +/* + * The gp1 pll IP is different with gp0 pll, the PLL DCO range is + * 1.6GHZ - 3.2GHZ, and the reg_sequence is short + */ +static const struct pll_mult_range gp1_pll_mult_range = { + .min = 67, + .max = 133, +}; + +static const struct reg_sequence gp1_init_regs[] = { + { .reg = ANACTRL_GP1PLL_CTRL1, .def = 0x1420500f }, + { .reg = ANACTRL_GP1PLL_CTRL2, .def = 0x00023001 }, + { .reg = ANACTRL_GP1PLL_CTRL3, .def = 0x00000000 }, +}; + +static struct clk_regmap gp1_pll_dco = { + .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = ANACTRL_GP1PLL_CTRL0, + .shift = 28, + .width = 1, + }, + .m = { + .reg_off = ANACTRL_GP1PLL_CTRL0, + .shift = 0, + .width = 8, + }, + .n = { + .reg_off = ANACTRL_GP1PLL_CTRL0, + .shift = 16, + .width = 5, + }, + .l = { + .reg_off = ANACTRL_GP1PLL_STS, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = ANACTRL_GP1PLL_CTRL0, + .shift = 29, + .width = 1, + }, + .range = &gp1_pll_mult_range, + .init_regs = gp1_init_regs, + .init_count = ARRAY_SIZE(gp1_init_regs), + }, + .hw.init = &(struct clk_init_data){ + .name = "gp1_pll_dco", + .ops = &meson_clk_pll_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "input", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap gp1_pll = { + .data = &(struct clk_regmap_div_data){ + .offset = ANACTRL_GP1PLL_CTRL0, + .shift = 12, + .width = 3, + .flags = CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init = &(struct clk_init_data) { + .name = "gp1_pll", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &gp1_pll_dco.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence hifi_init_regs[] = { + { .reg = ANACTRL_HIFIPLL_CTRL1, .def = 0x00000000 }, + { .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00000000 }, + { .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x6a285c00 }, + { .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x65771290 }, + { .reg = ANACTRL_HIFIPLL_CTRL5, .def = 0x3927200a }, + { .reg = ANACTRL_HIFIPLL_CTRL6, .def = 0x56540000 } +}; + +static struct clk_regmap hifi_pll_dco = { + .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = ANACTRL_HIFIPLL_CTRL0, + .shift = 28, + .width = 1, + }, + .m = { + .reg_off = ANACTRL_HIFIPLL_CTRL0, + .shift = 0, + .width = 8, + }, + .n = { + .reg_off = ANACTRL_HIFIPLL_CTRL0, + .shift = 10, + .width = 5, + }, + .l = { + .reg_off = ANACTRL_HIFIPLL_STS, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = ANACTRL_HIFIPLL_CTRL0, + .shift = 29, + .width = 1, + }, + .range = &media_pll_mult_range, + .init_regs = hifi_init_regs, + .init_count = ARRAY_SIZE(hifi_init_regs), + }, + .hw.init = &(struct clk_init_data){ + .name = "hifi_pll_dco", + .ops = &meson_clk_pll_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "input", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap hifi_pll = { + .data = &(struct clk_regmap_div_data){ + .offset = ANACTRL_HIFIPLL_CTRL0, + .shift = 16, + .width = 2, + .flags = CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init = &(struct clk_init_data) { + .name = "hifi_pll", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &hifi_pll_dco.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +/* + * The T7 PCIE PLL is fined tuned to deliver a very precise + * 100MHz reference clock for the PCIe Analog PHY, and thus requires + * a strict register sequence to enable the PLL. + */ +static const struct reg_sequence pcie_pll_init_regs[] = { + { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x200c04c8 }, + { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x300c04c8 }, + { .reg = ANACTRL_PCIEPLL_CTRL1, .def = 0x30000000 }, + { .reg = ANACTRL_PCIEPLL_CTRL2, .def = 0x00001100 }, + { .reg = ANACTRL_PCIEPLL_CTRL3, .def = 0x10058e00 }, + { .reg = ANACTRL_PCIEPLL_CTRL4, .def = 0x000100c0 }, + { .reg = ANACTRL_PCIEPLL_CTRL5, .def = 0x68000048 }, + { .reg = ANACTRL_PCIEPLL_CTRL5, .def = 0x68000068, .delay_us = 20 }, + { .reg = ANACTRL_PCIEPLL_CTRL4, .def = 0x008100c0, .delay_us = 20 }, + { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x340c04c8 }, + { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x140c04c8, .delay_us = 20 }, + { .reg = ANACTRL_PCIEPLL_CTRL2, .def = 0x00001000 } +}; + +static struct clk_regmap pcie_pll_dco = { + .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = ANACTRL_PCIEPLL_CTRL0, + .shift = 28, + .width = 1, + }, + .m = { + .reg_off = ANACTRL_PCIEPLL_CTRL0, + .shift = 0, + .width = 8, + }, + .n = { + .reg_off = ANACTRL_PCIEPLL_CTRL0, + .shift = 10, + .width = 5, + }, + .l = { + .reg_off = ANACTRL_PCIEPLL_CTRL0, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = ANACTRL_PCIEPLL_CTRL0, + .shift = 29, + .width = 1, + }, + .init_regs = pcie_pll_init_regs, + .init_count = ARRAY_SIZE(pcie_pll_init_regs), + }, + .hw.init = &(struct clk_init_data){ + .name = "pcie_pll_dco", + .ops = &meson_clk_pcie_pll_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "input", + }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor pcie_pll_dco_div2 = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "pcie_pll_dco_div2", + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { + &pcie_pll_dco.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap pcie_pll_od = { + .data = &(struct clk_regmap_div_data){ + .offset = ANACTRL_PCIEPLL_CTRL0, + .shift = 16, + .width = 5, + .flags = CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, + }, + .hw.init = &(struct clk_init_data){ + .name = "pcie_pll_od", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &pcie_pll_dco_div2.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_fixed_factor pcie_pll = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "pcie_pll", + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { + &pcie_pll_od.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_fixed_factor mpll_prediv = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "mpll_prediv", + .ops = &clk_fixed_factor_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "input", + }, + .num_parents = 1, + }, +}; + +static const struct reg_sequence mpll0_init_regs[] = { + { .reg = ANACTRL_MPLL_CTRL2, .def = 0x40000033 } +}; + +static struct clk_regmap mpll0_div = { + .data = &(struct meson_clk_mpll_data){ + .sdm = { + .reg_off = ANACTRL_MPLL_CTRL1, + .shift = 0, + .width = 14, + }, + .sdm_en = { + .reg_off = ANACTRL_MPLL_CTRL1, + .shift = 30, + .width = 1, + }, + .n2 = { + .reg_off = ANACTRL_MPLL_CTRL1, + .shift = 20, + .width = 9, + }, + .ssen = { + .reg_off = ANACTRL_MPLL_CTRL1, + .shift = 29, + .width = 1, + }, + .init_regs = mpll0_init_regs, + .init_count = ARRAY_SIZE(mpll0_init_regs), + }, + .hw.init = &(struct clk_init_data){ + .name = "mpll0_div", + .ops = &meson_clk_mpll_ops, + .parent_hws = (const struct clk_hw *[]) { + &mpll_prediv.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap mpll0 = { + .data = &(struct clk_regmap_gate_data){ + .offset = ANACTRL_MPLL_CTRL1, + .bit_idx = 31, + }, + .hw.init = &(struct clk_init_data){ + .name = "mpll0", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { &mpll0_div.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence mpll1_init_regs[] = { + { .reg = ANACTRL_MPLL_CTRL4, .def = 0x40000033 } +}; + +static struct clk_regmap mpll1_div = { + .data = &(struct meson_clk_mpll_data){ + .sdm = { + .reg_off = ANACTRL_MPLL_CTRL3, + .shift = 0, + .width = 14, + }, + .sdm_en = { + .reg_off = ANACTRL_MPLL_CTRL3, + .shift = 30, + .width = 1, + }, + .n2 = { + .reg_off = ANACTRL_MPLL_CTRL3, + .shift = 20, + .width = 9, + }, + .ssen = { + .reg_off = ANACTRL_MPLL_CTRL3, + .shift = 29, + .width = 1, + }, + .init_regs = mpll1_init_regs, + .init_count = ARRAY_SIZE(mpll1_init_regs), + }, + .hw.init = &(struct clk_init_data){ + .name = "mpll1_div", + .ops = &meson_clk_mpll_ops, + .parent_hws = (const struct clk_hw *[]) { + &mpll_prediv.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap mpll1 = { + .data = &(struct clk_regmap_gate_data){ + .offset = ANACTRL_MPLL_CTRL3, + .bit_idx = 31, + }, + .hw.init = &(struct clk_init_data){ + .name = "mpll1", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { &mpll1_div.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence mpll2_init_regs[] = { + { .reg = ANACTRL_MPLL_CTRL6, .def = 0x40000033 } +}; + +static struct clk_regmap mpll2_div = { + .data = &(struct meson_clk_mpll_data){ + .sdm = { + .reg_off = ANACTRL_MPLL_CTRL5, + .shift = 0, + .width = 14, + }, + .sdm_en = { + .reg_off = ANACTRL_MPLL_CTRL5, + .shift = 30, + .width = 1, + }, + .n2 = { + .reg_off = ANACTRL_MPLL_CTRL5, + .shift = 20, + .width = 9, + }, + .ssen = { + .reg_off = ANACTRL_MPLL_CTRL5, + .shift = 29, + .width = 1, + }, + .init_regs = mpll2_init_regs, + .init_count = ARRAY_SIZE(mpll2_init_regs), + }, + .hw.init = &(struct clk_init_data){ + .name = "mpll2_div", + .ops = &meson_clk_mpll_ops, + .parent_hws = (const struct clk_hw *[]) { + &mpll_prediv.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap mpll2 = { + .data = &(struct clk_regmap_gate_data){ + .offset = ANACTRL_MPLL_CTRL5, + .bit_idx = 31, + }, + .hw.init = &(struct clk_init_data){ + .name = "mpll2", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { &mpll2_div.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence mpll3_init_regs[] = { + { .reg = ANACTRL_MPLL_CTRL8, .def = 0x40000033 } +}; + +static struct clk_regmap mpll3_div = { + .data = &(struct meson_clk_mpll_data){ + .sdm = { + .reg_off = ANACTRL_MPLL_CTRL7, + .shift = 0, + .width = 14, + }, + .sdm_en = { + .reg_off = ANACTRL_MPLL_CTRL7, + .shift = 30, + .width = 1, + }, + .n2 = { + .reg_off = ANACTRL_MPLL_CTRL7, + .shift = 20, + .width = 9, + }, + .ssen = { + .reg_off = ANACTRL_MPLL_CTRL7, + .shift = 29, + .width = 1, + }, + .init_regs = mpll3_init_regs, + .init_count = ARRAY_SIZE(mpll3_init_regs), + }, + .hw.init = &(struct clk_init_data){ + .name = "mpll3_div", + .ops = &meson_clk_mpll_ops, + .parent_hws = (const struct clk_hw *[]) { + &mpll_prediv.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap mpll3 = { + .data = &(struct clk_regmap_gate_data){ + .offset = ANACTRL_MPLL_CTRL7, + .bit_idx = 31, + }, + .hw.init = &(struct clk_init_data){ + .name = "mpll3", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { &mpll3_div.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const struct reg_sequence hdmi_init_regs[] = { + { .reg = ANACTRL_HDMIPLL_CTRL1, .def = 0x00000000 }, + { .reg = ANACTRL_HDMIPLL_CTRL2, .def = 0x00000000 }, + { .reg = ANACTRL_HDMIPLL_CTRL3, .def = 0x6a28dc00 }, + { .reg = ANACTRL_HDMIPLL_CTRL4, .def = 0x65771290 }, + { .reg = ANACTRL_HDMIPLL_CTRL5, .def = 0x39272000 }, + { .reg = ANACTRL_HDMIPLL_CTRL6, .def = 0x56540000 } +}; + +static struct clk_regmap hdmi_pll_dco = { + .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = ANACTRL_HDMIPLL_CTRL0, + .shift = 28, + .width = 1, + }, + .m = { + .reg_off = ANACTRL_HDMIPLL_CTRL0, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = ANACTRL_HDMIPLL_CTRL0, + .shift = 10, + .width = 5, + }, + .l = { + .reg_off = ANACTRL_HDMIPLL_CTRL0, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = ANACTRL_HDMIPLL_CTRL0, + .shift = 29, + .width = 1, + }, + .range = &media_pll_mult_range, + .init_regs = hdmi_init_regs, + .init_count = ARRAY_SIZE(hdmi_init_regs), + }, + .hw.init = &(struct clk_init_data){ + .name = "hdmi_pll_dco", + .ops = &meson_clk_pll_ops, + .parent_data = (const struct clk_parent_data []) { + { .fw_name = "input", } + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap hdmi_pll_od = { + .data = &(struct clk_regmap_div_data){ + .offset = ANACTRL_HDMIPLL_CTRL0, + .shift = 16, + .width = 4, + .flags = CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init = &(struct clk_init_data){ + .name = "hdmi_pll_od", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &hdmi_pll_dco.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap hdmi_pll = { + .data = &(struct clk_regmap_div_data){ + .offset = ANACTRL_HDMIPLL_CTRL0, + .shift = 20, + .width = 2, + .flags = CLK_DIVIDER_POWER_OF_TWO, + }, + .hw.init = &(struct clk_init_data){ + .name = "hdmi_pll", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &hdmi_pll_od.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const struct pll_mult_range mclk_pll_mult_range = { + .min = 67, + .max = 133, +}; + +static const struct reg_sequence mclk_init_regs[] = { + { .reg = ANACTRL_MCLK_PLL_CNTL1, .def = 0x1470500f }, + { .reg = ANACTRL_MCLK_PLL_CNTL2, .def = 0x00023041 }, + { .reg = ANACTRL_MCLK_PLL_CNTL3, .def = 0x18180000 }, + { .reg = ANACTRL_MCLK_PLL_CNTL4, .def = 0x00180303 }, + { .reg = ANACTRL_MCLK_PLL_CNTL2, .def = 0x00023001, .delay_us = 20 } +}; + +static struct clk_regmap mclk_pll_dco = { + .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = ANACTRL_MCLK_PLL_CNTL0, + .shift = 28, + .width = 1, + }, + .m = { + .reg_off = ANACTRL_MCLK_PLL_CNTL0, + .shift = 0, + .width = 8, + }, + .n = { + .reg_off = ANACTRL_MCLK_PLL_CNTL0, + .shift = 16, + .width = 5, + }, + .l = { + .reg_off = ANACTRL_MCLK_PLL_CNTL0, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = ANACTRL_MCLK_PLL_CNTL0, + .shift = 29, + .width = 1, + }, + .range = &mclk_pll_mult_range, + .init_regs = mclk_init_regs, + .init_count = ARRAY_SIZE(mclk_init_regs), + }, + .hw.init = &(struct clk_init_data){ + .name = "mclk_pll_dco", + .ops = &meson_clk_pll_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "input", + }, + .num_parents = 1, + }, +}; + +/* max div is 16 */ +static const struct clk_div_table mclk_div[] = { + { .val = 0, .div = 1 }, + { .val = 1, .div = 2 }, + { .val = 2, .div = 4 }, + { .val = 3, .div = 8 }, + { .val = 4, .div = 16 }, + { /* sentinel */ } +}; + +static struct clk_regmap mclk_pre_od = { + .data = &(struct clk_regmap_div_data){ + .offset = ANACTRL_MCLK_PLL_CNTL0, + .shift = 12, + .width = 3, + .table = mclk_div, + }, + .hw.init = &(struct clk_init_data){ + .name = "mclk_pre_od", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &mclk_pll_dco.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mclk_pll = { + .data = &(struct clk_regmap_div_data){ + .offset = ANACTRL_MCLK_PLL_CNTL4, + .shift = 16, + .width = 5, + .flags = CLK_DIVIDER_ONE_BASED, + }, + .hw.init = &(struct clk_init_data){ + .name = "mclk_pll", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &mclk_pre_od.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mclk_0_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = ANACTRL_MCLK_PLL_CNTL4, + .mask = 0x3, + .shift = 4, + }, + .hw.init = &(struct clk_init_data){ + .name = "mclk_0_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .hw = &mclk_pll.hw }, + { .fw_name = "mclk_in0", }, + { .fw_name = "mclk_in1", }, + }, + .num_parents = 3, + }, +}; + +static struct clk_fixed_factor mclk_0_div2 = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "mclk_0_div2", + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { &mclk_0_sel.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mclk_0_pre = { + .data = &(struct clk_regmap_gate_data){ + .offset = ANACTRL_MCLK_PLL_CNTL4, + .bit_idx = 2, + }, + .hw.init = &(struct clk_init_data) { + .name = "mclk_0_pre", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &mclk_0_div2.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mclk_0 = { + .data = &(struct clk_regmap_gate_data){ + .offset = ANACTRL_MCLK_PLL_CNTL4, + .bit_idx = 0, + }, + .hw.init = &(struct clk_init_data) { + .name = "mclk_0", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &mclk_0_pre.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mclk_1_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = ANACTRL_MCLK_PLL_CNTL4, + .mask = 0x3, + .shift = 12, + }, + .hw.init = &(struct clk_init_data){ + .name = "mclk_1_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .hw = &mclk_pll.hw }, + { .fw_name = "mclk_in0", }, + { .fw_name = "mclk_in1", }, + }, + .num_parents = 3, + }, +}; + +static struct clk_fixed_factor mclk_1_div2 = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "mclk_1_div2", + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { &mclk_1_sel.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mclk_1_pre = { + .data = &(struct clk_regmap_gate_data){ + .offset = ANACTRL_MCLK_PLL_CNTL4, + .bit_idx = 10, + }, + .hw.init = &(struct clk_init_data) { + .name = "mclk_1_pre", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &mclk_1_div2.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mclk_1 = { + .data = &(struct clk_regmap_gate_data){ + .offset = ANACTRL_MCLK_PLL_CNTL4, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data) { + .name = "mclk_1", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &mclk_1_pre.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_hw *t7_gp0_hw_clks[] = { + [CLKID_GP0_PLL_DCO] = &gp0_pll_dco.hw, + [CLKID_GP0_PLL] = &gp0_pll.hw, +}; + +static struct clk_hw *t7_gp1_hw_clks[] = { + [CLKID_GP1_PLL_DCO] = &gp1_pll_dco.hw, + [CLKID_GP0_PLL] = &gp1_pll.hw, +}; + +static struct clk_hw *t7_hifi_hw_clks[] = { + [CLKID_HIFI_PLL_DCO] = &hifi_pll_dco.hw, + [CLKID_HIFI_PLL] = &hifi_pll.hw, +}; + +static struct clk_hw *t7_pcie_hw_clks[] = { + [CLKID_PCIE_PLL_DCO] = &pcie_pll_dco.hw, + [CLKID_PCIE_PLL_DCO_DIV2] = &pcie_pll_dco_div2.hw, + [CLKID_PCIE_PLL_OD] = &pcie_pll_od.hw, + [CLKID_PCIE_PLL] = &pcie_pll.hw, +}; + +static struct clk_hw *t7_mpll_hw_clks[] = { + [CLKID_MPLL_PREDIV] = &mpll_prediv.hw, + [CLKID_MPLL0_DIV] = &mpll0_div.hw, + [CLKID_MPLL0] = &mpll0.hw, + [CLKID_MPLL1_DIV] = &mpll1_div.hw, + [CLKID_MPLL1] = &mpll1.hw, + [CLKID_MPLL2_DIV] = &mpll2_div.hw, + [CLKID_MPLL2] = &mpll2.hw, + [CLKID_MPLL3_DIV] = &mpll3_div.hw, + [CLKID_MPLL3] = &mpll3.hw, +}; + +static struct clk_hw *t7_hdmi_hw_clks[] = { + [CLKID_HDMI_PLL_DCO] = &hdmi_pll_dco.hw, + [CLKID_HDMI_PLL_OD] = &hdmi_pll_od.hw, + [CLKID_HDMI_PLL] = &hdmi_pll.hw, +}; + +static struct clk_hw *t7_mclk_hw_clks[] = { + [CLKID_MCLK_PLL_DCO] = &mclk_pll_dco.hw, + [CLKID_MCLK_PRE] = &mclk_pre_od.hw, + [CLKID_MCLK_PLL] = &mclk_pll.hw, + [CLKID_MCLK_0_SEL] = &mclk_0_sel.hw, + [CLKID_MCLK_0_DIV2] = &mclk_0_div2.hw, + [CLKID_MCLK_0_PRE] = &mclk_0_pre.hw, + [CLKID_MCLK_0] = &mclk_0.hw, + [CLKID_MCLK_1_SEL] = &mclk_1_sel.hw, + [CLKID_MCLK_1_DIV2] = &mclk_1_div2.hw, + [CLKID_MCLK_1_PRE] = &mclk_1_pre.hw, + [CLKID_MCLK_1] = &mclk_1.hw, +}; + +static struct clk_regmap *const t7_gp0_regmaps[] = { + &gp0_pll_dco, + &gp0_pll, +}; + +static struct clk_regmap *const t7_gp1_regmaps[] = { + &gp1_pll_dco, + &gp1_pll, +}; + +static struct clk_regmap *const t7_hifi_regmaps[] = { + &hifi_pll_dco, + &hifi_pll, +}; + +static struct clk_regmap *const t7_pcie_regmaps[] = { + &pcie_pll_dco, + &pcie_pll_od, +}; + +static struct clk_regmap *const t7_mpll_regmaps[] = { + &mpll0_div, + &mpll0, + &mpll1_div, + &mpll1, + &mpll2_div, + &mpll2, + &mpll3_div, + &mpll3, +}; + +static struct clk_regmap *const t7_hdmi_regmaps[] = { + &hdmi_pll_dco, + &hdmi_pll_od, + &hdmi_pll, +}; + +static struct clk_regmap *const t7_mclk_regmaps[] = { + &mclk_pll_dco, + &mclk_pre_od, + &mclk_pll, + &mclk_0_sel, + &mclk_0_pre, + &mclk_0, + &mclk_1_sel, + &mclk_1_pre, + &mclk_1, +}; + +static const struct regmap_config clkc_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + +static int amlogic_t7_pll_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct meson_eeclkc_data *data; + void __iomem *base; + struct regmap *map; + int i, ret; + + data = of_device_get_match_data(&pdev->dev); + if (!data) + return -EINVAL; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + map = devm_regmap_init_mmio(dev, base, &clkc_regmap_config); + if (IS_ERR(map)) + return PTR_ERR(map); + + /* Populate regmap for the regmap backed clocks */ + for (i = 0; i < data->regmap_clk_num; i++) + data->regmap_clks[i]->map = map; + + if (data->init_count) + regmap_multi_reg_write(map, data->init_regs, + data->init_count); + + /* Register clocks */ + for (i = 0; i < data->hw_clks.num; i++) { + ret = devm_clk_hw_register(dev, data->hw_clks.hws[i]); + if (ret) + return ret; + } + + return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks); +} + +static const struct meson_eeclkc_data t7_gp0_data = { + .regmap_clks = t7_gp0_regmaps, + .regmap_clk_num = ARRAY_SIZE(t7_gp0_regmaps), + .hw_clks = { + .hws = t7_gp0_hw_clks, + .num = ARRAY_SIZE(t7_gp0_hw_clks), + }, +}; + +static const struct meson_eeclkc_data t7_gp1_data = { + .regmap_clks = t7_gp1_regmaps, + .regmap_clk_num = ARRAY_SIZE(t7_gp1_regmaps), + .hw_clks = { + .hws = t7_gp1_hw_clks, + .num = ARRAY_SIZE(t7_gp1_hw_clks), + }, +}; + +static const struct meson_eeclkc_data t7_hifi_data = { + .regmap_clks = t7_hifi_regmaps, + .regmap_clk_num = ARRAY_SIZE(t7_hifi_regmaps), + .hw_clks = { + .hws = t7_hifi_hw_clks, + .num = ARRAY_SIZE(t7_hifi_hw_clks), + }, +}; + +static const struct meson_eeclkc_data t7_pcie_data = { + .regmap_clks = t7_pcie_regmaps, + .regmap_clk_num = ARRAY_SIZE(t7_pcie_regmaps), + .hw_clks = { + .hws = t7_pcie_hw_clks, + .num = ARRAY_SIZE(t7_pcie_hw_clks), + }, +}; + +static const struct reg_sequence mpll_init_regs[] = { + { .reg = ANACTRL_MPLL_CTRL0, .def = 0x00000543 } +}; + +static const struct meson_eeclkc_data t7_mpll_data = { + .regmap_clks = t7_mpll_regmaps, + .regmap_clk_num = ARRAY_SIZE(t7_mpll_regmaps), + .init_regs = mpll_init_regs, + .init_count = ARRAY_SIZE(mpll_init_regs), + .hw_clks = { + .hws = t7_mpll_hw_clks, + .num = ARRAY_SIZE(t7_mpll_hw_clks), + }, +}; + +static const struct meson_eeclkc_data t7_hdmi_data = { + .regmap_clks = t7_hdmi_regmaps, + .regmap_clk_num = ARRAY_SIZE(t7_hdmi_regmaps), + .hw_clks = { + .hws = t7_hdmi_hw_clks, + .num = ARRAY_SIZE(t7_hdmi_hw_clks), + }, +}; + +static const struct meson_eeclkc_data t7_mclk_data = { + .regmap_clks = t7_mclk_regmaps, + .regmap_clk_num = ARRAY_SIZE(t7_mclk_regmaps), + .hw_clks = { + .hws = t7_mclk_hw_clks, + .num = ARRAY_SIZE(t7_mclk_hw_clks), + }, +}; + +static const struct of_device_id t7_pll_clkc_match_table[] = { + { + .compatible = "amlogic,t7-pll-gp0", + .data = &t7_gp0_data, + }, + { + .compatible = "amlogic,t7-pll-gp1", + .data = &t7_gp1_data, + }, + { + .compatible = "amlogic,t7-pll-hifi", + .data = &t7_hifi_data, + }, + { + .compatible = "amlogic,t7-pll-pcie", + .data = &t7_pcie_data, + }, + { + .compatible = "amlogic,t7-mpll", + .data = &t7_mpll_data, + }, + { + .compatible = "amlogic,t7-pll-hdmi", + .data = &t7_hdmi_data, + }, + { + .compatible = "amlogic,t7-pll-mclk", + .data = &t7_mclk_data, + }, + {} +}; +MODULE_DEVICE_TABLE(of, t7_pll_clkc_match_table); + +static struct platform_driver t7_pll_clkc_driver = { + .probe = amlogic_t7_pll_probe, + .driver = { + .name = "t7-pll-clkc", + .of_match_table = t7_pll_clkc_match_table, + }, +}; + +MODULE_DESCRIPTION("Amlogic T7 PLL Clock Controller driver"); +module_platform_driver(t7_pll_clkc_driver); +MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(CLK_MESON); -- 2.47.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 4/5] clk: meson: t7: add support for the T7 SoC PLL clock 2025-01-08 9:40 ` [PATCH v2 4/5] clk: meson: t7: add support for the T7 SoC PLL clock Jian Hu @ 2025-01-13 18:05 ` Jerome Brunet 2025-01-17 8:14 ` Jian Hu 0 siblings, 1 reply; 14+ messages in thread From: Jerome Brunet @ 2025-01-13 18:05 UTC (permalink / raw) To: Jian Hu Cc: Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel On Wed 08 Jan 2025 at 17:40, Jian Hu <jian.hu@amlogic.com> wrote: > Add PLL clock controller driver for the Amlogic T7 SoC family. > > Signed-off-by: Jian Hu <jian.hu@amlogic.com> > --- > drivers/clk/meson/Kconfig | 14 + > drivers/clk/meson/Makefile | 1 + > drivers/clk/meson/t7-pll.c | 1193 ++++++++++++++++++++++++++++++++++++ > 3 files changed, 1208 insertions(+) > create mode 100644 drivers/clk/meson/t7-pll.c > > diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig > index 78f648c9c97d..6878b035a7ac 100644 > --- a/drivers/clk/meson/Kconfig > +++ b/drivers/clk/meson/Kconfig > @@ -201,4 +201,18 @@ config COMMON_CLK_S4_PERIPHERALS > help > Support for the peripherals clock controller on Amlogic S805X2 and S905Y4 > devices, AKA S4. Say Y if you want S4 peripherals clock controller to work. > + > +config COMMON_CLK_T7_PLL > + tristate "Amlogic T7 SoC PLL controller support" > + depends on ARM64 > + default y > + select COMMON_CLK_MESON_REGMAP > + select COMMON_CLK_MESON_CLKC_UTILS > + select COMMON_CLK_MESON_PLL > + imply COMMON_CLK_SCMI > + help > + Support for the PLL clock controller on Amlogic A311D2 based > + device, AKA T7. PLLs are required by most peripheral to operate > + Say Y if you are a T7 based device. > + > endmenu > diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile > index bc56a47931c1..646257694c34 100644 > --- a/drivers/clk/meson/Makefile > +++ b/drivers/clk/meson/Makefile > @@ -27,3 +27,4 @@ obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o > obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o > obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o > obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) += s4-peripherals.o > +obj-$(CONFIG_COMMON_CLK_T7_PLL) += t7-pll.o > diff --git a/drivers/clk/meson/t7-pll.c b/drivers/clk/meson/t7-pll.c > new file mode 100644 > index 000000000000..a6113b7dfe11 > --- /dev/null > +++ b/drivers/clk/meson/t7-pll.c > @@ -0,0 +1,1193 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) > +/* > + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. > + * Author: Jian Hu <jian.hu@amlogic.com> > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/platform_device.h> > +#include "clk-regmap.h" > +#include "clk-pll.h" > +#include "clk-mpll.h" > +#include "meson-clkc-utils.h" > +#include "meson-eeclk.h" > +#include <dt-bindings/clock/amlogic,t7-pll-clkc.h> > + > +#define ANACTRL_GP0PLL_CTRL0 0x00 > +#define ANACTRL_GP0PLL_CTRL1 0x04 > +#define ANACTRL_GP0PLL_CTRL2 0x08 > +#define ANACTRL_GP0PLL_CTRL3 0x0c > +#define ANACTRL_GP0PLL_CTRL4 0x10 > +#define ANACTRL_GP0PLL_CTRL5 0x14 > +#define ANACTRL_GP0PLL_CTRL6 0x18 > +#define ANACTRL_GP0PLL_STS 0x1c > + > +#define ANACTRL_GP1PLL_CTRL0 0x00 > +#define ANACTRL_GP1PLL_CTRL1 0x04 > +#define ANACTRL_GP1PLL_CTRL2 0x08 > +#define ANACTRL_GP1PLL_CTRL3 0x0c > +#define ANACTRL_GP1PLL_STS 0x1c > + > +#define ANACTRL_HIFIPLL_CTRL0 0x00 > +#define ANACTRL_HIFIPLL_CTRL1 0x04 > +#define ANACTRL_HIFIPLL_CTRL2 0x08 > +#define ANACTRL_HIFIPLL_CTRL3 0x0c > +#define ANACTRL_HIFIPLL_CTRL4 0x10 > +#define ANACTRL_HIFIPLL_CTRL5 0x14 > +#define ANACTRL_HIFIPLL_CTRL6 0x18 > +#define ANACTRL_HIFIPLL_STS 0x1c > + > +#define ANACTRL_PCIEPLL_CTRL0 0x00 > +#define ANACTRL_PCIEPLL_CTRL1 0x04 > +#define ANACTRL_PCIEPLL_CTRL2 0x08 > +#define ANACTRL_PCIEPLL_CTRL3 0x0c > +#define ANACTRL_PCIEPLL_CTRL4 0x10 > +#define ANACTRL_PCIEPLL_CTRL5 0x14 > +#define ANACTRL_PCIEPLL_STS 0x18 > + > +#define ANACTRL_MPLL_CTRL0 0x00 > +#define ANACTRL_MPLL_CTRL1 0x04 > +#define ANACTRL_MPLL_CTRL2 0x08 > +#define ANACTRL_MPLL_CTRL3 0x0c > +#define ANACTRL_MPLL_CTRL4 0x10 > +#define ANACTRL_MPLL_CTRL5 0x14 > +#define ANACTRL_MPLL_CTRL6 0x18 > +#define ANACTRL_MPLL_CTRL7 0x1c > +#define ANACTRL_MPLL_CTRL8 0x20 > +#define ANACTRL_MPLL_STS 0x24 > + > +#define ANACTRL_HDMIPLL_CTRL0 0x00 > +#define ANACTRL_HDMIPLL_CTRL1 0x04 > +#define ANACTRL_HDMIPLL_CTRL2 0x08 > +#define ANACTRL_HDMIPLL_CTRL3 0x0c > +#define ANACTRL_HDMIPLL_CTRL4 0x10 > +#define ANACTRL_HDMIPLL_CTRL5 0x14 > +#define ANACTRL_HDMIPLL_CTRL6 0x18 > +#define ANACTRL_HDMIPLL_STS 0x1c > + > +#define ANACTRL_MCLK_PLL_CNTL0 0x00 > +#define ANACTRL_MCLK_PLL_CNTL1 0x04 > +#define ANACTRL_MCLK_PLL_CNTL2 0x08 > +#define ANACTRL_MCLK_PLL_CNTL3 0x0c > +#define ANACTRL_MCLK_PLL_CNTL4 0x10 > +#define ANACTRL_MCLK_PLL_STS 0x14 > + > +static const struct pll_mult_range media_pll_mult_range = { > + .min = 125, > + .max = 250, > +}; From now on I expect naming to be more predictable. This is part of an ongoing clean-up to be able to more easily share common part between SoC. The convention will be based on what's the most the rest of drivers/clk/meson to minimize the alignnment diff In the general, clk names, ID name and variable as much as possible, variables soc id prefixed > + > +static const struct reg_sequence gp0_init_regs[] = { t7_gp0_pll_init_regs > + { .reg = ANACTRL_GP0PLL_CTRL1, .def = 0x00000000 }, > + { .reg = ANACTRL_GP0PLL_CTRL2, .def = 0x00000000 }, > + { .reg = ANACTRL_GP0PLL_CTRL3, .def = 0x48681c00 }, > + { .reg = ANACTRL_GP0PLL_CTRL4, .def = 0x88770290 }, > + { .reg = ANACTRL_GP0PLL_CTRL5, .def = 0x3927200a }, > + { .reg = ANACTRL_GP0PLL_CTRL6, .def = 0x56540000 }, > +}; > + > +static struct clk_regmap gp0_pll_dco = { t7_gp0_pll_dco > + .data = &(struct meson_clk_pll_data){ > + .en = { > + .reg_off = ANACTRL_GP0PLL_CTRL0, > + .shift = 28, > + .width = 1, > + }, > + .m = { > + .reg_off = ANACTRL_GP0PLL_CTRL0, > + .shift = 0, > + .width = 8, > + }, > + .n = { > + .reg_off = ANACTRL_GP0PLL_CTRL0, > + .shift = 10, > + .width = 5, > + }, > + .l = { > + .reg_off = ANACTRL_GP0PLL_STS, > + .shift = 31, > + .width = 1, > + }, > + .rst = { > + .reg_off = ANACTRL_GP0PLL_CTRL0, > + .shift = 29, > + .width = 1, > + }, > + .range = &media_pll_mult_range, > + .init_regs = gp0_init_regs, > + .init_count = ARRAY_SIZE(gp0_init_regs), > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "gp0_pll_dco", > + .ops = &meson_clk_pll_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "input", > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap gp0_pll = { t7_gp0_pll ... and so on. > + .data = &(struct clk_regmap_div_data){ > + .offset = ANACTRL_GP0PLL_CTRL0, > + .shift = 16, > + .width = 3, > + .flags = CLK_DIVIDER_POWER_OF_TWO, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "gp0_pll", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &gp0_pll_dco.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +/* > + * The gp1 pll IP is different with gp0 pll, the PLL DCO range is > + * 1.6GHZ - 3.2GHZ, and the reg_sequence is short > + */ > +static const struct pll_mult_range gp1_pll_mult_range = { > + .min = 67, > + .max = 133, > +}; > + > +static const struct reg_sequence gp1_init_regs[] = { > + { .reg = ANACTRL_GP1PLL_CTRL1, .def = 0x1420500f }, > + { .reg = ANACTRL_GP1PLL_CTRL2, .def = 0x00023001 }, > + { .reg = ANACTRL_GP1PLL_CTRL3, .def = 0x00000000 }, > +}; > + > +static struct clk_regmap gp1_pll_dco = { > + .data = &(struct meson_clk_pll_data){ > + .en = { > + .reg_off = ANACTRL_GP1PLL_CTRL0, > + .shift = 28, > + .width = 1, > + }, > + .m = { > + .reg_off = ANACTRL_GP1PLL_CTRL0, > + .shift = 0, > + .width = 8, > + }, > + .n = { > + .reg_off = ANACTRL_GP1PLL_CTRL0, > + .shift = 16, > + .width = 5, > + }, > + .l = { > + .reg_off = ANACTRL_GP1PLL_STS, > + .shift = 31, > + .width = 1, > + }, > + .rst = { > + .reg_off = ANACTRL_GP1PLL_CTRL0, > + .shift = 29, > + .width = 1, > + }, > + .range = &gp1_pll_mult_range, > + .init_regs = gp1_init_regs, > + .init_count = ARRAY_SIZE(gp1_init_regs), > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "gp1_pll_dco", > + .ops = &meson_clk_pll_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "input", > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap gp1_pll = { > + .data = &(struct clk_regmap_div_data){ > + .offset = ANACTRL_GP1PLL_CTRL0, > + .shift = 12, > + .width = 3, > + .flags = CLK_DIVIDER_POWER_OF_TWO, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "gp1_pll", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &gp1_pll_dco.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static const struct reg_sequence hifi_init_regs[] = { > + { .reg = ANACTRL_HIFIPLL_CTRL1, .def = 0x00000000 }, > + { .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00000000 }, > + { .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x6a285c00 }, > + { .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x65771290 }, > + { .reg = ANACTRL_HIFIPLL_CTRL5, .def = 0x3927200a }, > + { .reg = ANACTRL_HIFIPLL_CTRL6, .def = 0x56540000 } > +}; > + > +static struct clk_regmap hifi_pll_dco = { > + .data = &(struct meson_clk_pll_data){ > + .en = { > + .reg_off = ANACTRL_HIFIPLL_CTRL0, > + .shift = 28, > + .width = 1, > + }, > + .m = { > + .reg_off = ANACTRL_HIFIPLL_CTRL0, > + .shift = 0, > + .width = 8, > + }, > + .n = { > + .reg_off = ANACTRL_HIFIPLL_CTRL0, > + .shift = 10, > + .width = 5, > + }, > + .l = { > + .reg_off = ANACTRL_HIFIPLL_STS, > + .shift = 31, > + .width = 1, > + }, > + .rst = { > + .reg_off = ANACTRL_HIFIPLL_CTRL0, > + .shift = 29, > + .width = 1, > + }, > + .range = &media_pll_mult_range, > + .init_regs = hifi_init_regs, > + .init_count = ARRAY_SIZE(hifi_init_regs), > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "hifi_pll_dco", > + .ops = &meson_clk_pll_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "input", > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap hifi_pll = { > + .data = &(struct clk_regmap_div_data){ > + .offset = ANACTRL_HIFIPLL_CTRL0, > + .shift = 16, > + .width = 2, > + .flags = CLK_DIVIDER_POWER_OF_TWO, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "hifi_pll", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &hifi_pll_dco.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +/* > + * The T7 PCIE PLL is fined tuned to deliver a very precise > + * 100MHz reference clock for the PCIe Analog PHY, and thus requires > + * a strict register sequence to enable the PLL. > + */ > +static const struct reg_sequence pcie_pll_init_regs[] = { > + { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x200c04c8 }, > + { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x300c04c8 }, > + { .reg = ANACTRL_PCIEPLL_CTRL1, .def = 0x30000000 }, > + { .reg = ANACTRL_PCIEPLL_CTRL2, .def = 0x00001100 }, > + { .reg = ANACTRL_PCIEPLL_CTRL3, .def = 0x10058e00 }, > + { .reg = ANACTRL_PCIEPLL_CTRL4, .def = 0x000100c0 }, > + { .reg = ANACTRL_PCIEPLL_CTRL5, .def = 0x68000048 }, > + { .reg = ANACTRL_PCIEPLL_CTRL5, .def = 0x68000068, .delay_us = 20 }, > + { .reg = ANACTRL_PCIEPLL_CTRL4, .def = 0x008100c0, .delay_us = 20 }, > + { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x340c04c8 }, > + { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x140c04c8, .delay_us = 20 }, > + { .reg = ANACTRL_PCIEPLL_CTRL2, .def = 0x00001000 } > +}; > + > +static struct clk_regmap pcie_pll_dco = { > + .data = &(struct meson_clk_pll_data){ > + .en = { > + .reg_off = ANACTRL_PCIEPLL_CTRL0, > + .shift = 28, > + .width = 1, > + }, > + .m = { > + .reg_off = ANACTRL_PCIEPLL_CTRL0, > + .shift = 0, > + .width = 8, > + }, > + .n = { > + .reg_off = ANACTRL_PCIEPLL_CTRL0, > + .shift = 10, > + .width = 5, > + }, > + .l = { > + .reg_off = ANACTRL_PCIEPLL_CTRL0, > + .shift = 31, > + .width = 1, > + }, > + .rst = { > + .reg_off = ANACTRL_PCIEPLL_CTRL0, > + .shift = 29, > + .width = 1, > + }, > + .init_regs = pcie_pll_init_regs, > + .init_count = ARRAY_SIZE(pcie_pll_init_regs), > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "pcie_pll_dco", > + .ops = &meson_clk_pcie_pll_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "input", > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_fixed_factor pcie_pll_dco_div2 = { > + .mult = 1, > + .div = 2, > + .hw.init = &(struct clk_init_data){ > + .name = "pcie_pll_dco_div2", > + .ops = &clk_fixed_factor_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &pcie_pll_dco.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap pcie_pll_od = { > + .data = &(struct clk_regmap_div_data){ > + .offset = ANACTRL_PCIEPLL_CTRL0, > + .shift = 16, > + .width = 5, > + .flags = CLK_DIVIDER_ONE_BASED | > + CLK_DIVIDER_ALLOW_ZERO, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "pcie_pll_od", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &pcie_pll_dco_div2.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_fixed_factor pcie_pll = { > + .mult = 1, > + .div = 2, > + .hw.init = &(struct clk_init_data){ > + .name = "pcie_pll", > + .ops = &clk_fixed_factor_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &pcie_pll_od.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_fixed_factor mpll_prediv = { > + .mult = 1, > + .div = 2, > + .hw.init = &(struct clk_init_data){ > + .name = "mpll_prediv", > + .ops = &clk_fixed_factor_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "input", > + }, > + .num_parents = 1, > + }, > +}; > + > +static const struct reg_sequence mpll0_init_regs[] = { > + { .reg = ANACTRL_MPLL_CTRL2, .def = 0x40000033 } > +}; > + > +static struct clk_regmap mpll0_div = { > + .data = &(struct meson_clk_mpll_data){ > + .sdm = { > + .reg_off = ANACTRL_MPLL_CTRL1, > + .shift = 0, > + .width = 14, > + }, > + .sdm_en = { > + .reg_off = ANACTRL_MPLL_CTRL1, > + .shift = 30, > + .width = 1, > + }, > + .n2 = { > + .reg_off = ANACTRL_MPLL_CTRL1, > + .shift = 20, > + .width = 9, > + }, > + .ssen = { > + .reg_off = ANACTRL_MPLL_CTRL1, > + .shift = 29, > + .width = 1, > + }, > + .init_regs = mpll0_init_regs, > + .init_count = ARRAY_SIZE(mpll0_init_regs), > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mpll0_div", > + .ops = &meson_clk_mpll_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &mpll_prediv.hw > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap mpll0 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = ANACTRL_MPLL_CTRL1, > + .bit_idx = 31, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mpll0", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { &mpll0_div.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static const struct reg_sequence mpll1_init_regs[] = { > + { .reg = ANACTRL_MPLL_CTRL4, .def = 0x40000033 } > +}; > + > +static struct clk_regmap mpll1_div = { > + .data = &(struct meson_clk_mpll_data){ > + .sdm = { > + .reg_off = ANACTRL_MPLL_CTRL3, > + .shift = 0, > + .width = 14, > + }, > + .sdm_en = { > + .reg_off = ANACTRL_MPLL_CTRL3, > + .shift = 30, > + .width = 1, > + }, > + .n2 = { > + .reg_off = ANACTRL_MPLL_CTRL3, > + .shift = 20, > + .width = 9, > + }, > + .ssen = { > + .reg_off = ANACTRL_MPLL_CTRL3, > + .shift = 29, > + .width = 1, > + }, > + .init_regs = mpll1_init_regs, > + .init_count = ARRAY_SIZE(mpll1_init_regs), > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mpll1_div", > + .ops = &meson_clk_mpll_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &mpll_prediv.hw > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap mpll1 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = ANACTRL_MPLL_CTRL3, > + .bit_idx = 31, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mpll1", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { &mpll1_div.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static const struct reg_sequence mpll2_init_regs[] = { > + { .reg = ANACTRL_MPLL_CTRL6, .def = 0x40000033 } > +}; > + > +static struct clk_regmap mpll2_div = { > + .data = &(struct meson_clk_mpll_data){ > + .sdm = { > + .reg_off = ANACTRL_MPLL_CTRL5, > + .shift = 0, > + .width = 14, > + }, > + .sdm_en = { > + .reg_off = ANACTRL_MPLL_CTRL5, > + .shift = 30, > + .width = 1, > + }, > + .n2 = { > + .reg_off = ANACTRL_MPLL_CTRL5, > + .shift = 20, > + .width = 9, > + }, > + .ssen = { > + .reg_off = ANACTRL_MPLL_CTRL5, > + .shift = 29, > + .width = 1, > + }, > + .init_regs = mpll2_init_regs, > + .init_count = ARRAY_SIZE(mpll2_init_regs), > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mpll2_div", > + .ops = &meson_clk_mpll_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &mpll_prediv.hw > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap mpll2 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = ANACTRL_MPLL_CTRL5, > + .bit_idx = 31, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mpll2", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { &mpll2_div.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static const struct reg_sequence mpll3_init_regs[] = { > + { .reg = ANACTRL_MPLL_CTRL8, .def = 0x40000033 } > +}; > + > +static struct clk_regmap mpll3_div = { > + .data = &(struct meson_clk_mpll_data){ > + .sdm = { > + .reg_off = ANACTRL_MPLL_CTRL7, > + .shift = 0, > + .width = 14, > + }, > + .sdm_en = { > + .reg_off = ANACTRL_MPLL_CTRL7, > + .shift = 30, > + .width = 1, > + }, > + .n2 = { > + .reg_off = ANACTRL_MPLL_CTRL7, > + .shift = 20, > + .width = 9, > + }, > + .ssen = { > + .reg_off = ANACTRL_MPLL_CTRL7, > + .shift = 29, > + .width = 1, > + }, > + .init_regs = mpll3_init_regs, > + .init_count = ARRAY_SIZE(mpll3_init_regs), > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mpll3_div", > + .ops = &meson_clk_mpll_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &mpll_prediv.hw > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap mpll3 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = ANACTRL_MPLL_CTRL7, > + .bit_idx = 31, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mpll3", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { &mpll3_div.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static const struct reg_sequence hdmi_init_regs[] = { > + { .reg = ANACTRL_HDMIPLL_CTRL1, .def = 0x00000000 }, > + { .reg = ANACTRL_HDMIPLL_CTRL2, .def = 0x00000000 }, > + { .reg = ANACTRL_HDMIPLL_CTRL3, .def = 0x6a28dc00 }, > + { .reg = ANACTRL_HDMIPLL_CTRL4, .def = 0x65771290 }, > + { .reg = ANACTRL_HDMIPLL_CTRL5, .def = 0x39272000 }, > + { .reg = ANACTRL_HDMIPLL_CTRL6, .def = 0x56540000 } > +}; > + > +static struct clk_regmap hdmi_pll_dco = { > + .data = &(struct meson_clk_pll_data){ > + .en = { > + .reg_off = ANACTRL_HDMIPLL_CTRL0, > + .shift = 28, > + .width = 1, > + }, > + .m = { > + .reg_off = ANACTRL_HDMIPLL_CTRL0, > + .shift = 0, > + .width = 9, > + }, > + .n = { > + .reg_off = ANACTRL_HDMIPLL_CTRL0, > + .shift = 10, > + .width = 5, > + }, > + .l = { > + .reg_off = ANACTRL_HDMIPLL_CTRL0, > + .shift = 31, > + .width = 1, > + }, > + .rst = { > + .reg_off = ANACTRL_HDMIPLL_CTRL0, > + .shift = 29, > + .width = 1, > + }, > + .range = &media_pll_mult_range, > + .init_regs = hdmi_init_regs, > + .init_count = ARRAY_SIZE(hdmi_init_regs), > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "hdmi_pll_dco", > + .ops = &meson_clk_pll_ops, > + .parent_data = (const struct clk_parent_data []) { > + { .fw_name = "input", } > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap hdmi_pll_od = { > + .data = &(struct clk_regmap_div_data){ > + .offset = ANACTRL_HDMIPLL_CTRL0, > + .shift = 16, > + .width = 4, > + .flags = CLK_DIVIDER_POWER_OF_TWO, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "hdmi_pll_od", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &hdmi_pll_dco.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap hdmi_pll = { > + .data = &(struct clk_regmap_div_data){ > + .offset = ANACTRL_HDMIPLL_CTRL0, > + .shift = 20, > + .width = 2, > + .flags = CLK_DIVIDER_POWER_OF_TWO, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "hdmi_pll", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &hdmi_pll_od.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static const struct pll_mult_range mclk_pll_mult_range = { > + .min = 67, > + .max = 133, > +}; > + > +static const struct reg_sequence mclk_init_regs[] = { > + { .reg = ANACTRL_MCLK_PLL_CNTL1, .def = 0x1470500f }, > + { .reg = ANACTRL_MCLK_PLL_CNTL2, .def = 0x00023041 }, > + { .reg = ANACTRL_MCLK_PLL_CNTL3, .def = 0x18180000 }, > + { .reg = ANACTRL_MCLK_PLL_CNTL4, .def = 0x00180303 }, > + { .reg = ANACTRL_MCLK_PLL_CNTL2, .def = 0x00023001, .delay_us = 20 } > +}; > + > +static struct clk_regmap mclk_pll_dco = { > + .data = &(struct meson_clk_pll_data){ > + .en = { > + .reg_off = ANACTRL_MCLK_PLL_CNTL0, > + .shift = 28, > + .width = 1, > + }, > + .m = { > + .reg_off = ANACTRL_MCLK_PLL_CNTL0, > + .shift = 0, > + .width = 8, > + }, > + .n = { > + .reg_off = ANACTRL_MCLK_PLL_CNTL0, > + .shift = 16, > + .width = 5, > + }, > + .l = { > + .reg_off = ANACTRL_MCLK_PLL_CNTL0, > + .shift = 31, > + .width = 1, > + }, > + .rst = { > + .reg_off = ANACTRL_MCLK_PLL_CNTL0, > + .shift = 29, > + .width = 1, > + }, > + .range = &mclk_pll_mult_range, > + .init_regs = mclk_init_regs, > + .init_count = ARRAY_SIZE(mclk_init_regs), > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mclk_pll_dco", > + .ops = &meson_clk_pll_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "input", > + }, > + .num_parents = 1, > + }, > +}; > + > +/* max div is 16 */ > +static const struct clk_div_table mclk_div[] = { > + { .val = 0, .div = 1 }, > + { .val = 1, .div = 2 }, > + { .val = 2, .div = 4 }, > + { .val = 3, .div = 8 }, > + { .val = 4, .div = 16 }, > + { /* sentinel */ } > +}; > + > +static struct clk_regmap mclk_pre_od = { > + .data = &(struct clk_regmap_div_data){ > + .offset = ANACTRL_MCLK_PLL_CNTL0, > + .shift = 12, > + .width = 3, > + .table = mclk_div, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mclk_pre_od", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &mclk_pll_dco.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap mclk_pll = { > + .data = &(struct clk_regmap_div_data){ > + .offset = ANACTRL_MCLK_PLL_CNTL4, > + .shift = 16, > + .width = 5, > + .flags = CLK_DIVIDER_ONE_BASED, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mclk_pll", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &mclk_pre_od.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap mclk_0_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = ANACTRL_MCLK_PLL_CNTL4, > + .mask = 0x3, > + .shift = 4, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mclk_0_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = (const struct clk_parent_data []) { > + { .hw = &mclk_pll.hw }, > + { .fw_name = "mclk_in0", }, > + { .fw_name = "mclk_in1", }, > + }, > + .num_parents = 3, > + }, > +}; > + > +static struct clk_fixed_factor mclk_0_div2 = { > + .mult = 1, > + .div = 2, > + .hw.init = &(struct clk_init_data){ > + .name = "mclk_0_div2", > + .ops = &clk_fixed_factor_ops, > + .parent_hws = (const struct clk_hw *[]) { &mclk_0_sel.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap mclk_0_pre = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = ANACTRL_MCLK_PLL_CNTL4, > + .bit_idx = 2, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "mclk_0_pre", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &mclk_0_div2.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap mclk_0 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = ANACTRL_MCLK_PLL_CNTL4, > + .bit_idx = 0, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "mclk_0", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &mclk_0_pre.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap mclk_1_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = ANACTRL_MCLK_PLL_CNTL4, > + .mask = 0x3, > + .shift = 12, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mclk_1_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = (const struct clk_parent_data []) { > + { .hw = &mclk_pll.hw }, > + { .fw_name = "mclk_in0", }, > + { .fw_name = "mclk_in1", }, > + }, > + .num_parents = 3, > + }, > +}; > + > +static struct clk_fixed_factor mclk_1_div2 = { > + .mult = 1, > + .div = 2, > + .hw.init = &(struct clk_init_data){ > + .name = "mclk_1_div2", > + .ops = &clk_fixed_factor_ops, > + .parent_hws = (const struct clk_hw *[]) { &mclk_1_sel.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap mclk_1_pre = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = ANACTRL_MCLK_PLL_CNTL4, > + .bit_idx = 10, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "mclk_1_pre", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &mclk_1_div2.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap mclk_1 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = ANACTRL_MCLK_PLL_CNTL4, > + .bit_idx = 8, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "mclk_1", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &mclk_1_pre.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_hw *t7_gp0_hw_clks[] = { > + [CLKID_GP0_PLL_DCO] = &gp0_pll_dco.hw, > + [CLKID_GP0_PLL] = &gp0_pll.hw, > +}; > + > +static struct clk_hw *t7_gp1_hw_clks[] = { > + [CLKID_GP1_PLL_DCO] = &gp1_pll_dco.hw, > + [CLKID_GP0_PLL] = &gp1_pll.hw, ^ This won't go well ... > +}; > + > +static struct clk_hw *t7_hifi_hw_clks[] = { > + [CLKID_HIFI_PLL_DCO] = &hifi_pll_dco.hw, > + [CLKID_HIFI_PLL] = &hifi_pll.hw, > +}; > + > +static struct clk_hw *t7_pcie_hw_clks[] = { > + [CLKID_PCIE_PLL_DCO] = &pcie_pll_dco.hw, > + [CLKID_PCIE_PLL_DCO_DIV2] = &pcie_pll_dco_div2.hw, > + [CLKID_PCIE_PLL_OD] = &pcie_pll_od.hw, > + [CLKID_PCIE_PLL] = &pcie_pll.hw, > +}; > + > +static struct clk_hw *t7_mpll_hw_clks[] = { > + [CLKID_MPLL_PREDIV] = &mpll_prediv.hw, > + [CLKID_MPLL0_DIV] = &mpll0_div.hw, > + [CLKID_MPLL0] = &mpll0.hw, > + [CLKID_MPLL1_DIV] = &mpll1_div.hw, > + [CLKID_MPLL1] = &mpll1.hw, > + [CLKID_MPLL2_DIV] = &mpll2_div.hw, > + [CLKID_MPLL2] = &mpll2.hw, > + [CLKID_MPLL3_DIV] = &mpll3_div.hw, > + [CLKID_MPLL3] = &mpll3.hw, > +}; > + > +static struct clk_hw *t7_hdmi_hw_clks[] = { > + [CLKID_HDMI_PLL_DCO] = &hdmi_pll_dco.hw, > + [CLKID_HDMI_PLL_OD] = &hdmi_pll_od.hw, > + [CLKID_HDMI_PLL] = &hdmi_pll.hw, > +}; > + > +static struct clk_hw *t7_mclk_hw_clks[] = { > + [CLKID_MCLK_PLL_DCO] = &mclk_pll_dco.hw, > + [CLKID_MCLK_PRE] = &mclk_pre_od.hw, > + [CLKID_MCLK_PLL] = &mclk_pll.hw, > + [CLKID_MCLK_0_SEL] = &mclk_0_sel.hw, > + [CLKID_MCLK_0_DIV2] = &mclk_0_div2.hw, > + [CLKID_MCLK_0_PRE] = &mclk_0_pre.hw, > + [CLKID_MCLK_0] = &mclk_0.hw, > + [CLKID_MCLK_1_SEL] = &mclk_1_sel.hw, > + [CLKID_MCLK_1_DIV2] = &mclk_1_div2.hw, > + [CLKID_MCLK_1_PRE] = &mclk_1_pre.hw, > + [CLKID_MCLK_1] = &mclk_1.hw, > +}; > + > +static struct clk_regmap *const t7_gp0_regmaps[] = { > + &gp0_pll_dco, > + &gp0_pll, > +}; > + > +static struct clk_regmap *const t7_gp1_regmaps[] = { > + &gp1_pll_dco, > + &gp1_pll, > +}; > + > +static struct clk_regmap *const t7_hifi_regmaps[] = { > + &hifi_pll_dco, > + &hifi_pll, > +}; > + > +static struct clk_regmap *const t7_pcie_regmaps[] = { > + &pcie_pll_dco, > + &pcie_pll_od, > +}; > + > +static struct clk_regmap *const t7_mpll_regmaps[] = { > + &mpll0_div, > + &mpll0, > + &mpll1_div, > + &mpll1, > + &mpll2_div, > + &mpll2, > + &mpll3_div, > + &mpll3, > +}; > + > +static struct clk_regmap *const t7_hdmi_regmaps[] = { > + &hdmi_pll_dco, > + &hdmi_pll_od, > + &hdmi_pll, > +}; > + > +static struct clk_regmap *const t7_mclk_regmaps[] = { > + &mclk_pll_dco, > + &mclk_pre_od, > + &mclk_pll, > + &mclk_0_sel, > + &mclk_0_pre, > + &mclk_0, > + &mclk_1_sel, > + &mclk_1_pre, > + &mclk_1, > +}; > + > +static const struct regmap_config clkc_regmap_config = { > + .reg_bits = 32, > + .val_bits = 32, > + .reg_stride = 4, > +}; > + > +static int amlogic_t7_pll_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + const struct meson_eeclkc_data *data; > + void __iomem *base; > + struct regmap *map; > + int i, ret; > + > + data = of_device_get_match_data(&pdev->dev); > + if (!data) > + return -EINVAL; > + > + base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(base)) > + return PTR_ERR(base); > + > + map = devm_regmap_init_mmio(dev, base, &clkc_regmap_config); > + if (IS_ERR(map)) > + return PTR_ERR(map); > + > + /* Populate regmap for the regmap backed clocks */ > + for (i = 0; i < data->regmap_clk_num; i++) > + data->regmap_clks[i]->map = map; > + > + if (data->init_count) > + regmap_multi_reg_write(map, data->init_regs, > + data->init_count); > + > + /* Register clocks */ > + for (i = 0; i < data->hw_clks.num; i++) { > + ret = devm_clk_hw_register(dev, data->hw_clks.hws[i]); > + if (ret) > + return ret; > + } > + > + return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks); > +} > + > +static const struct meson_eeclkc_data t7_gp0_data = { > + .regmap_clks = t7_gp0_regmaps, > + .regmap_clk_num = ARRAY_SIZE(t7_gp0_regmaps), > + .hw_clks = { > + .hws = t7_gp0_hw_clks, > + .num = ARRAY_SIZE(t7_gp0_hw_clks), > + }, > +}; > + > +static const struct meson_eeclkc_data t7_gp1_data = { > + .regmap_clks = t7_gp1_regmaps, > + .regmap_clk_num = ARRAY_SIZE(t7_gp1_regmaps), > + .hw_clks = { > + .hws = t7_gp1_hw_clks, > + .num = ARRAY_SIZE(t7_gp1_hw_clks), > + }, > +}; > + > +static const struct meson_eeclkc_data t7_hifi_data = { > + .regmap_clks = t7_hifi_regmaps, > + .regmap_clk_num = ARRAY_SIZE(t7_hifi_regmaps), > + .hw_clks = { > + .hws = t7_hifi_hw_clks, > + .num = ARRAY_SIZE(t7_hifi_hw_clks), > + }, > +}; > + > +static const struct meson_eeclkc_data t7_pcie_data = { > + .regmap_clks = t7_pcie_regmaps, > + .regmap_clk_num = ARRAY_SIZE(t7_pcie_regmaps), > + .hw_clks = { > + .hws = t7_pcie_hw_clks, > + .num = ARRAY_SIZE(t7_pcie_hw_clks), > + }, > +}; > + > +static const struct reg_sequence mpll_init_regs[] = { > + { .reg = ANACTRL_MPLL_CTRL0, .def = 0x00000543 } > +}; > + > +static const struct meson_eeclkc_data t7_mpll_data = { > + .regmap_clks = t7_mpll_regmaps, > + .regmap_clk_num = ARRAY_SIZE(t7_mpll_regmaps), > + .init_regs = mpll_init_regs, > + .init_count = ARRAY_SIZE(mpll_init_regs), > + .hw_clks = { > + .hws = t7_mpll_hw_clks, > + .num = ARRAY_SIZE(t7_mpll_hw_clks), > + }, > +}; > + > +static const struct meson_eeclkc_data t7_hdmi_data = { > + .regmap_clks = t7_hdmi_regmaps, > + .regmap_clk_num = ARRAY_SIZE(t7_hdmi_regmaps), > + .hw_clks = { > + .hws = t7_hdmi_hw_clks, > + .num = ARRAY_SIZE(t7_hdmi_hw_clks), > + }, > +}; > + > +static const struct meson_eeclkc_data t7_mclk_data = { > + .regmap_clks = t7_mclk_regmaps, > + .regmap_clk_num = ARRAY_SIZE(t7_mclk_regmaps), > + .hw_clks = { > + .hws = t7_mclk_hw_clks, > + .num = ARRAY_SIZE(t7_mclk_hw_clks), > + }, > +}; > + > +static const struct of_device_id t7_pll_clkc_match_table[] = { > + { > + .compatible = "amlogic,t7-pll-gp0", > + .data = &t7_gp0_data, > + }, > + { > + .compatible = "amlogic,t7-pll-gp1", > + .data = &t7_gp1_data, > + }, > + { > + .compatible = "amlogic,t7-pll-hifi", > + .data = &t7_hifi_data, > + }, > + { > + .compatible = "amlogic,t7-pll-pcie", > + .data = &t7_pcie_data, > + }, > + { > + .compatible = "amlogic,t7-mpll", > + .data = &t7_mpll_data, > + }, > + { > + .compatible = "amlogic,t7-pll-hdmi", > + .data = &t7_hdmi_data, > + }, > + { > + .compatible = "amlogic,t7-pll-mclk", > + .data = &t7_mclk_data, > + }, > + {} > +}; > +MODULE_DEVICE_TABLE(of, t7_pll_clkc_match_table); > + > +static struct platform_driver t7_pll_clkc_driver = { > + .probe = amlogic_t7_pll_probe, > + .driver = { > + .name = "t7-pll-clkc", > + .of_match_table = t7_pll_clkc_match_table, > + }, > +}; > + > +MODULE_DESCRIPTION("Amlogic T7 PLL Clock Controller driver"); > +module_platform_driver(t7_pll_clkc_driver); > +MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>"); > +MODULE_LICENSE("GPL"); > +MODULE_IMPORT_NS(CLK_MESON); -- Jerome ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 4/5] clk: meson: t7: add support for the T7 SoC PLL clock 2025-01-13 18:05 ` Jerome Brunet @ 2025-01-17 8:14 ` Jian Hu 0 siblings, 0 replies; 14+ messages in thread From: Jian Hu @ 2025-01-17 8:14 UTC (permalink / raw) To: Jerome Brunet Cc: Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel On 2025/1/14 2:05, Jerome Brunet wrote: > [ EXTERNAL EMAIL ] > > On Wed 08 Jan 2025 at 17:40, Jian Hu <jian.hu@amlogic.com> wrote: > >> Add PLL clock controller driver for the Amlogic T7 SoC family. >> >> Signed-off-by: Jian Hu <jian.hu@amlogic.com> >> --- >> drivers/clk/meson/Kconfig | 14 + >> drivers/clk/meson/Makefile | 1 + >> drivers/clk/meson/t7-pll.c | 1193 ++++++++++++++++++++++++++++++++++++ >> 3 files changed, 1208 insertions(+) >> create mode 100644 drivers/clk/meson/t7-pll.c >> >> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig >> index 78f648c9c97d..6878b035a7ac 100644 >> --- a/drivers/clk/meson/Kconfig >> +++ b/drivers/clk/meson/Kconfig >> @@ -201,4 +201,18 @@ config COMMON_CLK_S4_PERIPHERALS >> help >> Support for the peripherals clock controller on Amlogic S805X2 and S905Y4 >> devices, AKA S4. Say Y if you want S4 peripherals clock controller to work. >> + >> +config COMMON_CLK_T7_PLL >> + tristate "Amlogic T7 SoC PLL controller support" >> + depends on ARM64 >> + default y >> + select COMMON_CLK_MESON_REGMAP >> + select COMMON_CLK_MESON_CLKC_UTILS >> + select COMMON_CLK_MESON_PLL >> + imply COMMON_CLK_SCMI >> + help >> + Support for the PLL clock controller on Amlogic A311D2 based >> + device, AKA T7. PLLs are required by most peripheral to operate >> + Say Y if you are a T7 based device. >> + >> endmenu >> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile >> index bc56a47931c1..646257694c34 100644 >> --- a/drivers/clk/meson/Makefile >> +++ b/drivers/clk/meson/Makefile >> @@ -27,3 +27,4 @@ obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o >> obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o >> obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o >> obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) += s4-peripherals.o >> +obj-$(CONFIG_COMMON_CLK_T7_PLL) += t7-pll.o >> diff --git a/drivers/clk/meson/t7-pll.c b/drivers/clk/meson/t7-pll.c >> new file mode 100644 >> index 000000000000..a6113b7dfe11 >> --- /dev/null >> +++ b/drivers/clk/meson/t7-pll.c >> @@ -0,0 +1,1193 @@ >> +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) >> +/* >> + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. >> + * Author: Jian Hu <jian.hu@amlogic.com> >> + */ >> + >> +#include <linux/clk-provider.h> >> +#include <linux/platform_device.h> >> +#include "clk-regmap.h" >> +#include "clk-pll.h" >> +#include "clk-mpll.h" >> +#include "meson-clkc-utils.h" >> +#include "meson-eeclk.h" >> +#include <dt-bindings/clock/amlogic,t7-pll-clkc.h> >> + >> +#define ANACTRL_GP0PLL_CTRL0 0x00 >> +#define ANACTRL_GP0PLL_CTRL1 0x04 >> +#define ANACTRL_GP0PLL_CTRL2 0x08 >> +#define ANACTRL_GP0PLL_CTRL3 0x0c >> +#define ANACTRL_GP0PLL_CTRL4 0x10 >> +#define ANACTRL_GP0PLL_CTRL5 0x14 >> +#define ANACTRL_GP0PLL_CTRL6 0x18 >> +#define ANACTRL_GP0PLL_STS 0x1c >> + >> +#define ANACTRL_GP1PLL_CTRL0 0x00 >> +#define ANACTRL_GP1PLL_CTRL1 0x04 >> +#define ANACTRL_GP1PLL_CTRL2 0x08 >> +#define ANACTRL_GP1PLL_CTRL3 0x0c >> +#define ANACTRL_GP1PLL_STS 0x1c >> + >> +#define ANACTRL_HIFIPLL_CTRL0 0x00 >> +#define ANACTRL_HIFIPLL_CTRL1 0x04 >> +#define ANACTRL_HIFIPLL_CTRL2 0x08 >> +#define ANACTRL_HIFIPLL_CTRL3 0x0c >> +#define ANACTRL_HIFIPLL_CTRL4 0x10 >> +#define ANACTRL_HIFIPLL_CTRL5 0x14 >> +#define ANACTRL_HIFIPLL_CTRL6 0x18 >> +#define ANACTRL_HIFIPLL_STS 0x1c >> + >> +#define ANACTRL_PCIEPLL_CTRL0 0x00 >> +#define ANACTRL_PCIEPLL_CTRL1 0x04 >> +#define ANACTRL_PCIEPLL_CTRL2 0x08 >> +#define ANACTRL_PCIEPLL_CTRL3 0x0c >> +#define ANACTRL_PCIEPLL_CTRL4 0x10 >> +#define ANACTRL_PCIEPLL_CTRL5 0x14 >> +#define ANACTRL_PCIEPLL_STS 0x18 >> + >> +#define ANACTRL_MPLL_CTRL0 0x00 >> +#define ANACTRL_MPLL_CTRL1 0x04 >> +#define ANACTRL_MPLL_CTRL2 0x08 >> +#define ANACTRL_MPLL_CTRL3 0x0c >> +#define ANACTRL_MPLL_CTRL4 0x10 >> +#define ANACTRL_MPLL_CTRL5 0x14 >> +#define ANACTRL_MPLL_CTRL6 0x18 >> +#define ANACTRL_MPLL_CTRL7 0x1c >> +#define ANACTRL_MPLL_CTRL8 0x20 >> +#define ANACTRL_MPLL_STS 0x24 >> + >> +#define ANACTRL_HDMIPLL_CTRL0 0x00 >> +#define ANACTRL_HDMIPLL_CTRL1 0x04 >> +#define ANACTRL_HDMIPLL_CTRL2 0x08 >> +#define ANACTRL_HDMIPLL_CTRL3 0x0c >> +#define ANACTRL_HDMIPLL_CTRL4 0x10 >> +#define ANACTRL_HDMIPLL_CTRL5 0x14 >> +#define ANACTRL_HDMIPLL_CTRL6 0x18 >> +#define ANACTRL_HDMIPLL_STS 0x1c >> + >> +#define ANACTRL_MCLK_PLL_CNTL0 0x00 >> +#define ANACTRL_MCLK_PLL_CNTL1 0x04 >> +#define ANACTRL_MCLK_PLL_CNTL2 0x08 >> +#define ANACTRL_MCLK_PLL_CNTL3 0x0c >> +#define ANACTRL_MCLK_PLL_CNTL4 0x10 >> +#define ANACTRL_MCLK_PLL_STS 0x14 >> + >> +static const struct pll_mult_range media_pll_mult_range = { >> + .min = 125, >> + .max = 250, >> +}; > From now on I expect naming to be more predictable. > This is part of an ongoing clean-up to be able to more easily share > common part between SoC. The convention will be based on what's > the most the rest of drivers/clk/meson to minimize the alignnment diff > > In the general, clk names, ID name and variable as much as possible, > variables soc id prefixed Agreed with you. >> + >> +static const struct reg_sequence gp0_init_regs[] = { > t7_gp0_pll_init_regs Ok. > >> + { .reg = ANACTRL_GP0PLL_CTRL1, .def = 0x00000000 }, >> + { .reg = ANACTRL_GP0PLL_CTRL2, .def = 0x00000000 }, >> + { .reg = ANACTRL_GP0PLL_CTRL3, .def = 0x48681c00 }, >> + { .reg = ANACTRL_GP0PLL_CTRL4, .def = 0x88770290 }, >> + { .reg = ANACTRL_GP0PLL_CTRL5, .def = 0x3927200a }, >> + { .reg = ANACTRL_GP0PLL_CTRL6, .def = 0x56540000 }, >> +}; >> + >> +static struct clk_regmap gp0_pll_dco = { > t7_gp0_pll_dco Ok. > >> + .data = &(struct meson_clk_pll_data){ >> + .en = { >> + .reg_off = ANACTRL_GP0PLL_CTRL0, >> + .shift = 28, >> + .width = 1, >> + }, >> + .m = { >> + .reg_off = ANACTRL_GP0PLL_CTRL0, >> + .shift = 0, >> + .width = 8, >> + }, >> + .n = { >> + .reg_off = ANACTRL_GP0PLL_CTRL0, >> + .shift = 10, >> + .width = 5, >> + }, >> + .l = { >> + .reg_off = ANACTRL_GP0PLL_STS, >> + .shift = 31, >> + .width = 1, >> + }, >> + .rst = { >> + .reg_off = ANACTRL_GP0PLL_CTRL0, >> + .shift = 29, >> + .width = 1, >> + }, >> + .range = &media_pll_mult_range, >> + .init_regs = gp0_init_regs, >> + .init_count = ARRAY_SIZE(gp0_init_regs), >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "gp0_pll_dco", >> + .ops = &meson_clk_pll_ops, >> + .parent_data = &(const struct clk_parent_data) { >> + .fw_name = "input", >> + }, >> + .num_parents = 1, >> + }, >> +}; >> + >> +static struct clk_regmap gp0_pll = { > t7_gp0_pll ... and so on. Ok, I will add t7_ prefix for the varibles and names. Also apply for t7-peripherals.c. >> + .data = &(struct clk_regmap_div_data){ >> + .offset = ANACTRL_GP0PLL_CTRL0, >> + .shift = 16, >> + .width = 3, >> + .flags = CLK_DIVIDER_POWER_OF_TWO, >> + }, >> + .hw.init = &(struct clk_init_data) { >> + .name = "gp0_pll", >> + .ops = &clk_regmap_divider_ops, >> + .parent_hws = (const struct clk_hw *[]) { >> + &gp0_pll_dco.hw >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + }, >> +}; >> ...... >> + >> +static struct clk_hw *t7_gp0_hw_clks[] = { >> + [CLKID_GP0_PLL_DCO] = &gp0_pll_dco.hw, >> + [CLKID_GP0_PLL] = &gp0_pll.hw, >> +}; >> + >> +static struct clk_hw *t7_gp1_hw_clks[] = { >> + [CLKID_GP1_PLL_DCO] = &gp1_pll_dco.hw, >> + [CLKID_GP0_PLL] = &gp1_pll.hw, > ^ > This won't go well ... Ok, I will fix it in next verion. > ...... > -- > Jerome ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 5/5] clk: meson: t7: add t7 clock peripherals controller driver 2025-01-08 9:40 [PATCH v2 0/5] add support for T7 family clock controller Jian Hu ` (3 preceding siblings ...) 2025-01-08 9:40 ` [PATCH v2 4/5] clk: meson: t7: add support for the T7 SoC PLL clock Jian Hu @ 2025-01-08 9:40 ` Jian Hu 2025-01-13 18:18 ` Jerome Brunet 4 siblings, 1 reply; 14+ messages in thread From: Jian Hu @ 2025-01-08 9:40 UTC (permalink / raw) To: Jerome Brunet, Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring Cc: Jian Hu, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel Add Peripheral clock controller driver for the Amlogic T7 SoC family. Signed-off-by: Jian Hu <jian.hu@amlogic.com> --- drivers/clk/meson/Kconfig | 13 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/t7-peripherals.c | 2323 ++++++++++++++++++++++++++++ 3 files changed, 2337 insertions(+) create mode 100644 drivers/clk/meson/t7-peripherals.c diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 6878b035a7ac..1f5fd4c0f79f 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -215,4 +215,17 @@ config COMMON_CLK_T7_PLL device, AKA T7. PLLs are required by most peripheral to operate Say Y if you are a T7 based device. +config COMMON_CLK_T7_PERIPHERALS + tristate "Amlogic T7 SoC peripherals clock controller support" + depends on ARM64 + default y + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_CLKC_UTILS + select COMMON_CLK_MESON_DUALDIV + imply COMMON_CLK_SCMI + imply COMMON_CLK_T7_PLL + help + Support for the Peripherals clock controller on Amlogic A311D2 based + device, AKA T7. Peripherals are required by most peripheral to operate + Say Y if you are a T7 based device. endmenu diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 646257694c34..6fef3188af30 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -28,3 +28,4 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) += s4-peripherals.o obj-$(CONFIG_COMMON_CLK_T7_PLL) += t7-pll.o +obj-$(CONFIG_COMMON_CLK_T7_PERIPHERALS) += t7-peripherals.o diff --git a/drivers/clk/meson/t7-peripherals.c b/drivers/clk/meson/t7-peripherals.c new file mode 100644 index 000000000000..4b9c4061ab39 --- /dev/null +++ b/drivers/clk/meson/t7-peripherals.c @@ -0,0 +1,2323 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + * Author: Jian Hu <jian.hu@amlogic.com> + */ + +#include <linux/clk-provider.h> +#include <linux/platform_device.h> +#include "clk-dualdiv.h" +#include "clk-regmap.h" +#include "meson-clkc-utils.h" +#include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h> + +#define CLKCTRL_RTC_BY_OSCIN_CTRL0 0x8 +#define CLKCTRL_RTC_BY_OSCIN_CTRL1 0xc +#define CLKCTRL_RTC_CTRL 0x10 +#define CLKCTRL_SYS_CLK_CTRL0 0x40 +#define CLKCTRL_SYS_CLK_EN0_REG0 0x44 +#define CLKCTRL_SYS_CLK_EN0_REG1 0x48 +#define CLKCTRL_SYS_CLK_EN0_REG2 0x4c +#define CLKCTRL_SYS_CLK_EN0_REG3 0x50 +#define CLKCTRL_CECA_CTRL0 0x88 +#define CLKCTRL_CECA_CTRL1 0x8c +#define CLKCTRL_CECB_CTRL0 0x90 +#define CLKCTRL_CECB_CTRL1 0x94 +#define CLKCTRL_SC_CLK_CTRL 0x98 +#define CLKCTRL_DSPA_CLK_CTRL0 0x9c +#define CLKCTRL_DSPB_CLK_CTRL0 0xa0 +#define CLKCTRL_CLK12_24_CTRL 0xa8 +#define CLKCTRL_ANAKIN_CLK_CTRL 0xac +#define CLKCTRL_MIPI_CSI_PHY_CLK_CTRL 0x10c +#define CLKCTRL_MIPI_ISP_CLK_CTRL 0x110 +#define CLKCTRL_TS_CLK_CTRL 0x158 +#define CLKCTRL_MALI_CLK_CTRL 0x15c +#define CLKCTRL_ETH_CLK_CTRL 0x164 +#define CLKCTRL_NAND_CLK_CTRL 0x168 +#define CLKCTRL_SD_EMMC_CLK_CTRL 0x16c +#define CLKCTRL_SPICC_CLK_CTRL 0x174 +#define CLKCTRL_SAR_CLK_CTRL0 0x17c +#define CLKCTRL_PWM_CLK_AB_CTRL 0x180 +#define CLKCTRL_PWM_CLK_CD_CTRL 0x184 +#define CLKCTRL_PWM_CLK_EF_CTRL 0x188 +#define CLKCTRL_PWM_CLK_AO_AB_CTRL 0x1a0 +#define CLKCTRL_PWM_CLK_AO_CD_CTRL 0x1a4 +#define CLKCTRL_PWM_CLK_AO_EF_CTRL 0x1a8 +#define CLKCTRL_PWM_CLK_AO_GH_CTRL 0x1ac +#define CLKCTRL_SPICC_CLK_CTRL1 0x1c0 +#define CLKCTRL_SPICC_CLK_CTRL2 0x1c4 + +static struct clk_regmap rtc_32k_in = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_RTC_BY_OSCIN_CTRL0, + .bit_idx = 31, + }, + .hw.init = &(struct clk_init_data) { + .name = "rtc_32k_in", + .ops = &clk_regmap_gate_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static const struct meson_clk_dualdiv_param clk_32k_div_table[] = { + { + .n1 = 733, .m1 = 8, + .n2 = 732, .m2 = 11, + .dual = 1, + }, + {} +}; + +static struct clk_regmap rtc_32k_div = { + .data = &(struct meson_clk_dualdiv_data){ + .n1 = { + .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0, + .shift = 0, + .width = 12, + }, + .n2 = { + .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0, + .shift = 12, + .width = 12, + }, + .m1 = { + .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL1, + .shift = 0, + .width = 12, + }, + .m2 = { + .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL1, + .shift = 12, + .width = 12, + }, + .dual = { + .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0, + .shift = 28, + .width = 1, + }, + .table = clk_32k_div_table, + }, + .hw.init = &(struct clk_init_data){ + .name = "rtc_32k_div", + .ops = &meson_clk_dualdiv_ops, + .parent_hws = (const struct clk_hw *[]) { + &rtc_32k_in.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap rtc_32k_force_sel = { + .data = &(struct clk_regmap_mux_data) { + .offset = CLKCTRL_RTC_BY_OSCIN_CTRL1, + .mask = 0x1, + .shift = 24, + }, + .hw.init = &(struct clk_init_data){ + .name = "rtc_32k_force_sel", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &rtc_32k_div.hw, + &rtc_32k_in.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap rtc_32k_out = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_RTC_BY_OSCIN_CTRL0, + .bit_idx = 30, + }, + .hw.init = &(struct clk_init_data) { + .name = "rtc_32k_out", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &rtc_32k_force_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap rtc_32k_mux0_0 = { + .data = &(struct clk_regmap_mux_data) { + .offset = CLKCTRL_RTC_CTRL, + .mask = 0x1, + .shift = 0, + }, + .hw.init = &(struct clk_init_data){ + .name = "rtc_32k_mux0_0", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .fw_name = "xtal", }, + { .hw = &rtc_32k_out.hw }, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap rtc_32k_mux0_1 = { + .data = &(struct clk_regmap_mux_data) { + .offset = CLKCTRL_RTC_CTRL, + .mask = 0x1, + .shift = 0, + }, + .hw.init = &(struct clk_init_data){ + .name = "rtc_32k_mux0_1", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .fw_name = "pad", }, + { .fw_name = "xtal", }, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap rtc = { + .data = &(struct clk_regmap_mux_data) { + .offset = CLKCTRL_RTC_CTRL, + .mask = 0x1, + .shift = 1, + }, + .hw.init = &(struct clk_init_data){ + .name = "rtc", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &rtc_32k_mux0_0.hw, + &rtc_32k_mux0_1.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap ceca_32k_in = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_CECA_CTRL0, + .bit_idx = 31, + }, + .hw.init = &(struct clk_init_data) { + .name = "ceca_32k_in", + .ops = &clk_regmap_gate_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap ceca_32k_div = { + .data = &(struct meson_clk_dualdiv_data){ + .n1 = { + .reg_off = CLKCTRL_CECA_CTRL0, + .shift = 0, + .width = 12, + }, + .n2 = { + .reg_off = CLKCTRL_CECA_CTRL0, + .shift = 12, + .width = 12, + }, + .m1 = { + .reg_off = CLKCTRL_CECA_CTRL1, + .shift = 0, + .width = 12, + }, + .m2 = { + .reg_off = CLKCTRL_CECA_CTRL1, + .shift = 12, + .width = 12, + }, + .dual = { + .reg_off = CLKCTRL_CECA_CTRL0, + .shift = 28, + .width = 1, + }, + .table = clk_32k_div_table, + }, + .hw.init = &(struct clk_init_data){ + .name = "ceca_32k_div", + .ops = &meson_clk_dualdiv_ops, + .parent_hws = (const struct clk_hw *[]) { + &ceca_32k_in.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap ceca_32k_sel_pre = { + .data = &(struct clk_regmap_mux_data) { + .offset = CLKCTRL_CECA_CTRL1, + .mask = 0x1, + .shift = 24, + }, + .hw.init = &(struct clk_init_data){ + .name = "ceca_32k_sel_pre", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &ceca_32k_div.hw, + &ceca_32k_in.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap ceca_32k_sel = { + .data = &(struct clk_regmap_mux_data) { + .offset = CLKCTRL_CECA_CTRL1, + .mask = 0x1, + .shift = 31, + }, + .hw.init = &(struct clk_init_data){ + .name = "ceca_32k_sel", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &ceca_32k_sel_pre.hw, + &rtc.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap ceca_32k_out = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_CECA_CTRL0, + .bit_idx = 30, + }, + .hw.init = &(struct clk_init_data){ + .name = "ceca_32k_out", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &ceca_32k_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap cecb_32k_in = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_CECB_CTRL0, + .bit_idx = 31, + }, + .hw.init = &(struct clk_init_data) { + .name = "cecb_32k_in", + .ops = &clk_regmap_gate_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap cecb_32k_div = { + .data = &(struct meson_clk_dualdiv_data){ + .n1 = { + .reg_off = CLKCTRL_CECB_CTRL0, + .shift = 0, + .width = 12, + }, + .n2 = { + .reg_off = CLKCTRL_CECB_CTRL0, + .shift = 12, + .width = 12, + }, + .m1 = { + .reg_off = CLKCTRL_CECB_CTRL1, + .shift = 0, + .width = 12, + }, + .m2 = { + .reg_off = CLKCTRL_CECB_CTRL1, + .shift = 12, + .width = 12, + }, + .dual = { + .reg_off = CLKCTRL_CECB_CTRL0, + .shift = 28, + .width = 1, + }, + .table = clk_32k_div_table, + }, + .hw.init = &(struct clk_init_data){ + .name = "cecb_32k_div", + .ops = &meson_clk_dualdiv_ops, + .parent_hws = (const struct clk_hw *[]) { + &cecb_32k_in.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap cecb_32k_sel_pre = { + .data = &(struct clk_regmap_mux_data) { + .offset = CLKCTRL_CECB_CTRL1, + .mask = 0x1, + .shift = 24, + }, + .hw.init = &(struct clk_init_data){ + .name = "cecb_32k_sel_pre", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &cecb_32k_div.hw, + &cecb_32k_in.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap cecb_32k_sel = { + .data = &(struct clk_regmap_mux_data) { + .offset = CLKCTRL_CECB_CTRL1, + .mask = 0x1, + .shift = 31, + }, + .hw.init = &(struct clk_init_data){ + .name = "cecb_32k_sel", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &cecb_32k_sel_pre.hw, + &rtc.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap cecb_32k_out = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_CECB_CTRL0, + .bit_idx = 30, + }, + .hw.init = &(struct clk_init_data){ + .name = "cecb_32k_out", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &cecb_32k_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +/* Smartcard Clock */ +static const struct clk_parent_data sc_parents[] = { + { .fw_name = "fdiv4", }, + { .fw_name = "fdiv3", }, + { .fw_name = "fdiv5", }, + { .fw_name = "xtal", }, +}; + +static struct clk_regmap sc_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_SC_CLK_CTRL, + .mask = 0x3, + .shift = 9, + }, + .hw.init = &(struct clk_init_data){ + .name = "sc_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = sc_parents, + .num_parents = ARRAY_SIZE(sc_parents), + }, +}; + +static struct clk_regmap sc_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_SC_CLK_CTRL, + .shift = 0, + .width = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "sc_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &sc_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap sc = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_SC_CLK_CTRL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data) { + .name = "sc", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &sc_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +/* + * The DSPA/B IP is clocked by two identical clocks (dspa/b_a and dspa/b_b) + * muxed by a glitch-free switch. + */ +static const struct clk_parent_data dsp_ab_parent_data[] = { + { .fw_name = "xtal", }, + { .fw_name = "fdiv2p5", }, + { .fw_name = "fdiv3", }, + { .fw_name = "fdiv5", }, + { .fw_name = "hifi", }, + { .fw_name = "fdiv4", }, + { .fw_name = "fdiv7", }, + { .hw = &rtc.hw }, +}; + +static struct clk_regmap dspa_a_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_DSPA_CLK_CTRL0, + .mask = 0x7, + .shift = 10, + }, + .hw.init = &(struct clk_init_data){ + .name = "dspa_a_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = dsp_ab_parent_data, + .num_parents = ARRAY_SIZE(dsp_ab_parent_data), + }, +}; + +static struct clk_regmap dspa_a_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_DSPA_CLK_CTRL0, + .shift = 0, + .width = 10, + }, + .hw.init = &(struct clk_init_data){ + .name = "dspa_a_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &dspa_a_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspa_a = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_DSPA_CLK_CTRL0, + .bit_idx = 13, + }, + .hw.init = &(struct clk_init_data) { + .name = "dspa_a", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &dspa_a_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspa_b_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_DSPA_CLK_CTRL0, + .mask = 0x7, + .shift = 26, + }, + .hw.init = &(struct clk_init_data){ + .name = "dspa_b_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = dsp_ab_parent_data, + .num_parents = ARRAY_SIZE(dsp_ab_parent_data), + }, +}; + +static struct clk_regmap dspa_b_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_DSPA_CLK_CTRL0, + .shift = 16, + .width = 10, + }, + .hw.init = &(struct clk_init_data){ + .name = "dspa_b_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &dspa_b_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspa_b = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_DSPA_CLK_CTRL0, + .bit_idx = 29, + }, + .hw.init = &(struct clk_init_data) { + .name = "dspa_b", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &dspa_b_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspa = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_DSPA_CLK_CTRL0, + .mask = 0x1, + .shift = 15, + }, + .hw.init = &(struct clk_init_data){ + .name = "dspa", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &dspa_a.hw, + &dspa_b.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspb_a_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_DSPB_CLK_CTRL0, + .mask = 0x7, + .shift = 10, + }, + .hw.init = &(struct clk_init_data){ + .name = "dspb_a_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = dsp_ab_parent_data, + .num_parents = ARRAY_SIZE(dsp_ab_parent_data), + }, +}; + +static struct clk_regmap dspb_a_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_DSPB_CLK_CTRL0, + .shift = 0, + .width = 10, + }, + .hw.init = &(struct clk_init_data){ + .name = "dspb_a_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &dspb_a_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspb_a = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_DSPB_CLK_CTRL0, + .bit_idx = 13, + }, + .hw.init = &(struct clk_init_data) { + .name = "dspb_a", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &dspb_a_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspb_b_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_DSPB_CLK_CTRL0, + .mask = 0x7, + .shift = 26, + }, + .hw.init = &(struct clk_init_data){ + .name = "dspb_b_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = dsp_ab_parent_data, + .num_parents = ARRAY_SIZE(dsp_ab_parent_data), + }, +}; + +static struct clk_regmap dspb_b_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_DSPB_CLK_CTRL0, + .shift = 16, + .width = 10, + }, + .hw.init = &(struct clk_init_data){ + .name = "dspb_b_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &dspb_b_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspb_b = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_DSPB_CLK_CTRL0, + .bit_idx = 29, + }, + .hw.init = &(struct clk_init_data) { + .name = "dspb_b", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &dspb_b_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspb = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_DSPB_CLK_CTRL0, + .mask = 0x1, + .shift = 15, + }, + .hw.init = &(struct clk_init_data){ + .name = "dspb", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &dspb_a.hw, + &dspb_b.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap clk_24m = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_CLK12_24_CTRL, + .bit_idx = 11, + }, + .hw.init = &(struct clk_init_data) { + .name = "24m", + .ops = &clk_regmap_gate_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor clk_24m_div2 = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "24m_div2", + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { + &clk_24m.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap clk_12m = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_CLK12_24_CTRL, + .bit_idx = 10, + }, + .hw.init = &(struct clk_init_data) { + .name = "12m", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &clk_24m_div2.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap fdiv2_divn_pre = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_CLK12_24_CTRL, + .shift = 0, + .width = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "fdiv2_divn_pre", + .ops = &clk_regmap_divider_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "fdiv2", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap fdiv2_divn = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_CLK12_24_CTRL, + .bit_idx = 12, + }, + .hw.init = &(struct clk_init_data){ + .name = "fdiv2_divn", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &fdiv2_divn_pre.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +/* + * The NNA IP is clocked by two identical clocks (anakin_0 and anakin_1) + * muxed by a glitch-free switch. + */ +static const struct clk_parent_data anakin_parent_data[] = { + { .fw_name = "fdiv4", }, + { .fw_name = "fdiv3", }, + { .fw_name = "fdiv5", }, + { .fw_name = "fdiv2", }, + { .fw_name = "vid_pll0", }, + { .fw_name = "mpll1", }, + { .fw_name = "mpll2", }, + { .fw_name = "fdiv2p5", }, +}; + +static struct clk_regmap anakin_0_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_ANAKIN_CLK_CTRL, + .mask = 0x7, + .shift = 9, + }, + .hw.init = &(struct clk_init_data){ + .name = "anakin_0_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = anakin_parent_data, + .num_parents = ARRAY_SIZE(anakin_parent_data), + }, +}; + +static struct clk_regmap anakin_0_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_ANAKIN_CLK_CTRL, + .shift = 0, + .width = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "anakin_0_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &anakin_0_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap anakin_0 = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_ANAKIN_CLK_CTRL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data) { + .name = "anakin_0", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { &anakin_0_div.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap anakin_1_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_ANAKIN_CLK_CTRL, + .mask = 0x7, + .shift = 25, + }, + .hw.init = &(struct clk_init_data){ + .name = "anakin_1_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = anakin_parent_data, + .num_parents = ARRAY_SIZE(anakin_parent_data), + }, +}; + +static struct clk_regmap anakin_1_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_ANAKIN_CLK_CTRL, + .shift = 16, + .width = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "anakin_1_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &anakin_1_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap anakin_1 = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_ANAKIN_CLK_CTRL, + .bit_idx = 24, + }, + .hw.init = &(struct clk_init_data) { + .name = "anakin_1", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &anakin_1_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap anakin = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_ANAKIN_CLK_CTRL, + .mask = 1, + .shift = 31, + }, + .hw.init = &(struct clk_init_data){ + .name = "anakin_sel", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &anakin_0.hw, + &anakin_1.hw + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT + }, +}; + +static struct clk_regmap anakin_clk = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_ANAKIN_CLK_CTRL, + .bit_idx = 30, + }, + .hw.init = &(struct clk_init_data) { + .name = "anakin_clk", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &anakin.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT + }, +}; + +static const struct clk_parent_data mipi_csi_parents[] = { + { .fw_name = "xtal", }, + { .fw_name = "gp1", }, + { .fw_name = "mpll1", }, + { .fw_name = "mpll2", }, + { .fw_name = "fdiv3", }, + { .fw_name = "fdiv4", }, + { .fw_name = "fdiv5", }, + { .fw_name = "fdiv7", }, +}; + +static struct clk_regmap mipi_csi_phy0_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, + .mask = 0x7, + .shift = 9, + }, + .hw.init = &(struct clk_init_data){ + .name = "mipi_csi_phy0_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = mipi_csi_parents, + .num_parents = ARRAY_SIZE(mipi_csi_parents), + }, +}; + +static struct clk_regmap mipi_csi_phy0_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, + .shift = 0, + .width = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "mipi_csi_phy0_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &mipi_csi_phy0_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mipi_csi_phy0 = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data) { + .name = "mipi_csi_phy0", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &mipi_csi_phy0_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mipi_csi_phy1_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, + .mask = 0x7, + .shift = 25, + }, + .hw.init = &(struct clk_init_data){ + .name = "mipi_csi_phy1_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = mipi_csi_parents, + .num_parents = ARRAY_SIZE(mipi_csi_parents), + }, +}; + +static struct clk_regmap mipi_csi_phy1_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, + .shift = 16, + .width = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "mipi_csi_phy1_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &mipi_csi_phy1_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mipi_csi_phy1 = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, + .bit_idx = 24, + }, + .hw.init = &(struct clk_init_data) { + .name = "mipi_csi_phy1", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &mipi_csi_phy1_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mipi_csi_phy = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, + .mask = 0x1, + .shift = 31, + }, + .hw.init = &(struct clk_init_data){ + .name = "mipi_csi_phy", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &mipi_csi_phy0.hw, + &mipi_csi_phy1.hw + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data mipi_isp_parents[] = { + { .fw_name = "xtal", }, + { .fw_name = "fdiv4", }, + { .fw_name = "fdiv3", }, + { .fw_name = "fdiv5", }, + { .fw_name = "fdiv7", }, + { .fw_name = "mpll2", }, + { .fw_name = "mpll3", }, + { .fw_name = "gp1", }, +}; + +static struct clk_regmap mipi_isp_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_MIPI_ISP_CLK_CTRL, + .mask = 0x7, + .shift = 9, + }, + .hw.init = &(struct clk_init_data){ + .name = "mipi_isp_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = mipi_isp_parents, + .num_parents = ARRAY_SIZE(mipi_isp_parents), + }, +}; + +static struct clk_regmap mipi_isp_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_MIPI_ISP_CLK_CTRL, + .shift = 0, + .width = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "mipi_isp_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &mipi_isp_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mipi_isp = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_MIPI_ISP_CLK_CTRL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data) { + .name = "mipi_isp", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &mipi_isp_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap ts_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_TS_CLK_CTRL, + .shift = 0, + .width = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "ts_div", + .ops = &clk_regmap_divider_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap ts = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_TS_CLK_CTRL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "ts", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &ts_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +/* + * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) + * muxed by a glitch-free switch. + */ +static const struct clk_parent_data mali_parents[] = { + { .fw_name = "xtal", }, + { .fw_name = "gp0", }, + { .fw_name = "gp1", }, + { .fw_name = "fdiv2p5", }, + { .fw_name = "fdiv3", }, + { .fw_name = "fdiv4", }, + { .fw_name = "fdiv5", }, + { .fw_name = "fdiv7", }, +}; + +static struct clk_regmap mali_0_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_MALI_CLK_CTRL, + .mask = 0x7, + .shift = 9, + }, + .hw.init = &(struct clk_init_data){ + .name = "mali_0_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = mali_parents, + .num_parents = ARRAY_SIZE(mali_parents), + }, +}; + +static struct clk_regmap mali_0_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_MALI_CLK_CTRL, + .shift = 0, + .width = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "mali_0_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &mali_0_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mali_0 = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_MALI_CLK_CTRL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "mali_0", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &mali_0_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mali_1_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_MALI_CLK_CTRL, + .mask = 0x7, + .shift = 25, + }, + .hw.init = &(struct clk_init_data){ + .name = "mali_1_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = mali_parents, + .num_parents = ARRAY_SIZE(mali_parents), + }, +}; + +static struct clk_regmap mali_1_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_MALI_CLK_CTRL, + .shift = 16, + .width = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "mali_1_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &mali_1_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mali_1 = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_MALI_CLK_CTRL, + .bit_idx = 24, + }, + .hw.init = &(struct clk_init_data){ + .name = "mali_1", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &mali_1_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap mali = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_MALI_CLK_CTRL, + .mask = 1, + .shift = 31, + }, + .hw.init = &(struct clk_init_data){ + .name = "mali", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &mali_0.hw, + &mali_1.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static u32 eth_rmii_table[] = { 0, 7 }; + +static const struct clk_parent_data eth_rmii_parents[] = { + { .fw_name = "fdiv2", }, + { .fw_name = "rmii_pad", }, +}; + +static struct clk_regmap eth_rmii_sel = { + .data = &(struct clk_regmap_mux_data) { + .offset = CLKCTRL_ETH_CLK_CTRL, + .mask = 0x3, + .shift = 9, + .table = eth_rmii_table + }, + .hw.init = &(struct clk_init_data){ + .name = "eth_rmii_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = eth_rmii_parents, + .num_parents = ARRAY_SIZE(eth_rmii_parents), + .num_parents = 2 + }, +}; + +static struct clk_regmap eth_rmii_div = { + .data = &(struct clk_regmap_div_data) { + .offset = CLKCTRL_ETH_CLK_CTRL, + .shift = 0, + .width = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "eth_rmii_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + ð_rmii_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap eth_rmii = { + .data = &(struct clk_regmap_gate_data) { + .offset = CLKCTRL_ETH_CLK_CTRL, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "eth_rmii", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + ð_rmii_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_fixed_factor fdiv2_div8 = { + .mult = 1, + .div = 8, + .hw.init = &(struct clk_init_data){ + .name = "fdiv2_div8", + .ops = &clk_fixed_factor_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "fdiv2", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap eth_125m = { + .data = &(struct clk_regmap_gate_data) { + .offset = CLKCTRL_ETH_CLK_CTRL, + .bit_idx = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "eth_125m", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &fdiv2_div8.hw + }, + .num_parents = 1, + }, +}; + +static const struct clk_parent_data sd_emmc_parents[] = { + { .fw_name = "xtal", }, + { .fw_name = "fdiv2", }, + { .fw_name = "fdiv3", }, + { .fw_name = "hifi", }, + { .fw_name = "fdiv2p5", }, + { .fw_name = "mpll2", }, + { .fw_name = "mpll3", }, + { .fw_name = "gp0", }, +}; + +static struct clk_regmap sd_emmc_c_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_NAND_CLK_CTRL, + .mask = 0x7, + .shift = 9, + }, + .hw.init = &(struct clk_init_data) { + .name = "sd_emmc_c_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = sd_emmc_parents, + .num_parents = ARRAY_SIZE(sd_emmc_parents), + }, +}; + +static struct clk_regmap sd_emmc_c_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_NAND_CLK_CTRL, + .shift = 0, + .width = 7, + }, + .hw.init = &(struct clk_init_data) { + .name = "sd_emmc_c_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &sd_emmc_c_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap sd_emmc_c = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_NAND_CLK_CTRL, + .bit_idx = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "sd_emmc_c", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &sd_emmc_c_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap sd_emmc_a_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_SD_EMMC_CLK_CTRL, + .mask = 0x7, + .shift = 9, + }, + .hw.init = &(struct clk_init_data) { + .name = "sd_emmc_a_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = sd_emmc_parents, + .num_parents = ARRAY_SIZE(sd_emmc_parents), + }, +}; + +static struct clk_regmap sd_emmc_a_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_SD_EMMC_CLK_CTRL, + .shift = 0, + .width = 7, + }, + .hw.init = &(struct clk_init_data) { + .name = "sd_emmc_a_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &sd_emmc_a_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap sd_emmc_a = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_SD_EMMC_CLK_CTRL, + .bit_idx = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "sd_emmc_a", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &sd_emmc_a_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap sd_emmc_b_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = CLKCTRL_SD_EMMC_CLK_CTRL, + .mask = 0x7, + .shift = 25, + }, + .hw.init = &(struct clk_init_data) { + .name = "sd_emmc_b_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = sd_emmc_parents, + .num_parents = ARRAY_SIZE(sd_emmc_parents), + }, +}; + +static struct clk_regmap sd_emmc_b_div = { + .data = &(struct clk_regmap_div_data){ + .offset = CLKCTRL_SD_EMMC_CLK_CTRL, + .shift = 16, + .width = 7, + }, + .hw.init = &(struct clk_init_data) { + .name = "sd_emmc_b_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &sd_emmc_b_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap sd_emmc_b = { + .data = &(struct clk_regmap_gate_data){ + .offset = CLKCTRL_SD_EMMC_CLK_CTRL, + .bit_idx = 23, + }, + .hw.init = &(struct clk_init_data){ + .name = "sd_emmc_b", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &sd_emmc_b_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +#define SPI_PWM_CLK_MUX(_name, _reg, _mask, _shift, _parent_data) { \ + .data = &(struct clk_regmap_mux_data) { \ + .offset = _reg, \ + .mask = _mask, \ + .shift = _shift, \ + }, \ + .hw.init = &(struct clk_init_data) { \ + .name = #_name "_sel", \ + .ops = &clk_regmap_mux_ops, \ + .parent_data = _parent_data, \ + .num_parents = ARRAY_SIZE(_parent_data), \ + }, \ +} + +#define SPI_PWM_CLK_DIV(_name, _reg, _shift, _width, _parent) { \ + .data = &(struct clk_regmap_div_data) { \ + .offset = _reg, \ + .shift = _shift, \ + .width = _width, \ + }, \ + .hw.init = &(struct clk_init_data) { \ + .name = #_name "_div", \ + .ops = &clk_regmap_divider_ops, \ + .parent_hws = (const struct clk_hw *[]) { \ + &_parent.hw \ + }, \ + .num_parents = 1, \ + .flags = CLK_SET_RATE_PARENT, \ + }, \ +} + +#define SPI_PWM_CLK_GATE(_name, _reg, _bit, _parent) { \ + .data = &(struct clk_regmap_gate_data) { \ + .offset = _reg, \ + .bit_idx = _bit, \ + }, \ + .hw.init = &(struct clk_init_data) { \ + .name = #_name, \ + .ops = &clk_regmap_gate_ops, \ + .parent_hws = (const struct clk_hw *[]) { \ + &_parent.hw \ + }, \ + .num_parents = 1, \ + .flags = CLK_SET_RATE_PARENT, \ + }, \ +} + +static const struct clk_parent_data spicc_parents[] = { + { .fw_name = "xtal", }, + { .fw_name = "sys", }, + { .fw_name = "fdiv4", }, + { .fw_name = "fdiv3", }, + { .fw_name = "fdiv2", }, + { .fw_name = "fdiv5", }, + { .fw_name = "fdiv7", }, + { .fw_name = "gp1", }, +}; + +static struct clk_regmap spicc0_sel = + SPI_PWM_CLK_MUX(spicc0, CLKCTRL_SPICC_CLK_CTRL, 0x7, 7, spicc_parents); +static struct clk_regmap spicc0_div = SPI_PWM_CLK_DIV(spicc0, CLKCTRL_SPICC_CLK_CTRL, 0, 6, spicc0_sel); +static struct clk_regmap spicc0 = SPI_PWM_CLK_GATE(spicc0, CLKCTRL_SPICC_CLK_CTRL, 6, spicc0_div); + +static struct clk_regmap spicc1_sel = + SPI_PWM_CLK_MUX(spicc1, CLKCTRL_SPICC_CLK_CTRL, 0x7, 23, spicc_parents); +static struct clk_regmap spicc1_div = SPI_PWM_CLK_DIV(spicc1, CLKCTRL_SPICC_CLK_CTRL, 16, 6, spicc1_sel); +static struct clk_regmap spicc1 = SPI_PWM_CLK_GATE(spicc1, CLKCTRL_SPICC_CLK_CTRL, 22, spicc1_div); + +static struct clk_regmap spicc2_sel = + SPI_PWM_CLK_MUX(spicc2, CLKCTRL_SPICC_CLK_CTRL1, 0x7, 7, spicc_parents); +static struct clk_regmap spicc2_div = SPI_PWM_CLK_DIV(spicc2, CLKCTRL_SPICC_CLK_CTRL1, 0, 6, spicc2_sel); +static struct clk_regmap spicc2 = SPI_PWM_CLK_GATE(spicc2, CLKCTRL_SPICC_CLK_CTRL1, 6, spicc2_div); + +static struct clk_regmap spicc3_sel = + SPI_PWM_CLK_MUX(spicc3, CLKCTRL_SPICC_CLK_CTRL1, 0x7, 23, spicc_parents); +static struct clk_regmap spicc3_div = SPI_PWM_CLK_DIV(spicc3, CLKCTRL_SPICC_CLK_CTRL1, 16, 6, spicc3_sel); +static struct clk_regmap spicc3 = SPI_PWM_CLK_GATE(spicc3, CLKCTRL_SPICC_CLK_CTRL1, 22, spicc3_div); + +static struct clk_regmap spicc4_sel = + SPI_PWM_CLK_MUX(spicc4, CLKCTRL_SPICC_CLK_CTRL2, 0x7, 7, spicc_parents); +static struct clk_regmap spicc4_div = SPI_PWM_CLK_DIV(spicc4, CLKCTRL_SPICC_CLK_CTRL2, 0, 6, spicc4_sel); +static struct clk_regmap spicc4 = SPI_PWM_CLK_GATE(spicc4, CLKCTRL_SPICC_CLK_CTRL2, 6, spicc4_div); + +static struct clk_regmap spicc5_sel = + SPI_PWM_CLK_MUX(spicc5, CLKCTRL_SPICC_CLK_CTRL2, 0x7, 23, spicc_parents); +static struct clk_regmap spicc5_div = SPI_PWM_CLK_DIV(spicc5, CLKCTRL_SPICC_CLK_CTRL2, 16, 6, spicc5_sel); +static struct clk_regmap spicc5 = SPI_PWM_CLK_GATE(spicc5, CLKCTRL_SPICC_CLK_CTRL2, 22, spicc5_div); + +static struct clk_regmap saradc_sel = { + .data = &(struct clk_regmap_mux_data) { + .offset = CLKCTRL_SAR_CLK_CTRL0, + .mask = 0x1, + .shift = 9, + }, + .hw.init = &(struct clk_init_data){ + .name = "saradc_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .fw_name = "xtal", }, + { .fw_name = "sys", }, + }, + .num_parents = 2, + }, +}; + +static struct clk_regmap saradc_div = { + .data = &(struct clk_regmap_div_data) { + .offset = CLKCTRL_SAR_CLK_CTRL0, + .shift = 0, + .width = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "saradc_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &saradc_sel.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap saradc = { + .data = &(struct clk_regmap_gate_data) { + .offset = CLKCTRL_SAR_CLK_CTRL0, + .bit_idx = 8, + }, + .hw.init = &(struct clk_init_data){ + .name = "saradc", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &saradc_div.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data pwm_parents[] = { + { .fw_name = "xtal", }, + { .fw_name = "vid_pll0", }, + { .fw_name = "fdiv4", }, + { .fw_name = "fdiv3", }, +}; + +static struct clk_regmap pwm_a_sel = + SPI_PWM_CLK_MUX(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 0x3, 9, pwm_parents); +static struct clk_regmap pwm_a_div = SPI_PWM_CLK_DIV(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 0, 8, pwm_a_sel); +static struct clk_regmap pwm_a = SPI_PWM_CLK_GATE(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 8, pwm_a_div); + +static struct clk_regmap pwm_b_sel = + SPI_PWM_CLK_MUX(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 0x3, 25, pwm_parents); +static struct clk_regmap pwm_b_div = SPI_PWM_CLK_DIV(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 16, 8, pwm_b_sel); +static struct clk_regmap pwm_b = SPI_PWM_CLK_GATE(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 24, pwm_b_div); + +static struct clk_regmap pwm_c_sel = + SPI_PWM_CLK_MUX(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 0x3, 9, pwm_parents); +static struct clk_regmap pwm_c_div = SPI_PWM_CLK_DIV(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 0, 8, pwm_c_sel); +static struct clk_regmap pwm_c = SPI_PWM_CLK_GATE(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 8, pwm_c_div); + +static struct clk_regmap pwm_d_sel = + SPI_PWM_CLK_MUX(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 0x3, 25, pwm_parents); +static struct clk_regmap pwm_d_div = SPI_PWM_CLK_DIV(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 16, 8, pwm_d_sel); +static struct clk_regmap pwm_d = SPI_PWM_CLK_GATE(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 24, pwm_d_div); + +static struct clk_regmap pwm_e_sel = + SPI_PWM_CLK_MUX(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 0x3, 9, pwm_parents); +static struct clk_regmap pwm_e_div = SPI_PWM_CLK_DIV(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 0, 8, pwm_e_sel); +static struct clk_regmap pwm_e = SPI_PWM_CLK_GATE(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 8, pwm_e_div); + +static struct clk_regmap pwm_f_sel = + SPI_PWM_CLK_MUX(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 0x3, 25, pwm_parents); +static struct clk_regmap pwm_f_div = SPI_PWM_CLK_DIV(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 16, 8, pwm_f_sel); +static struct clk_regmap pwm_f = SPI_PWM_CLK_GATE(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 24, pwm_f_div); + +static struct clk_regmap pwm_ao_a_sel = + SPI_PWM_CLK_MUX(pwm_ao_a, CLKCTRL_PWM_CLK_AO_AB_CTRL, 0x3, 9, pwm_parents); +static struct clk_regmap pwm_ao_a_div = SPI_PWM_CLK_DIV(pwm_ao_a, CLKCTRL_PWM_CLK_AO_AB_CTRL, 0, 8, pwm_ao_a_sel); +static struct clk_regmap pwm_ao_a = SPI_PWM_CLK_GATE(pwm_ao_a, CLKCTRL_PWM_CLK_AO_AB_CTRL, 8, pwm_ao_a_div); + +static struct clk_regmap pwm_ao_b_sel = + SPI_PWM_CLK_MUX(pwm_ao_b, CLKCTRL_PWM_CLK_AO_AB_CTRL, 0x3, 25, pwm_parents); +static struct clk_regmap pwm_ao_b_div = SPI_PWM_CLK_DIV(pwm_ao_b, CLKCTRL_PWM_CLK_AO_AB_CTRL, 16, 8, pwm_ao_b_sel); +static struct clk_regmap pwm_ao_b = SPI_PWM_CLK_GATE(pwm_ao_b, CLKCTRL_PWM_CLK_AO_AB_CTRL, 24, pwm_ao_b_div); + +static struct clk_regmap pwm_ao_c_sel = + SPI_PWM_CLK_MUX(pwm_ao_c, CLKCTRL_PWM_CLK_AO_CD_CTRL, 0x3, 9, pwm_parents); +static struct clk_regmap pwm_ao_c_div = SPI_PWM_CLK_DIV(pwm_ao_c, CLKCTRL_PWM_CLK_AO_CD_CTRL, 0, 8, pwm_ao_c_sel); +static struct clk_regmap pwm_ao_c = SPI_PWM_CLK_GATE(pwm_ao_c, CLKCTRL_PWM_CLK_AO_CD_CTRL, 8, pwm_ao_c_div); + +static struct clk_regmap pwm_ao_d_sel = + SPI_PWM_CLK_MUX(pwm_ao_d, CLKCTRL_PWM_CLK_AO_CD_CTRL, 0x3, 25, pwm_parents); +static struct clk_regmap pwm_ao_d_div = SPI_PWM_CLK_DIV(pwm_ao_d, CLKCTRL_PWM_CLK_AO_CD_CTRL, 16, 8, pwm_ao_d_sel); +static struct clk_regmap pwm_ao_d = SPI_PWM_CLK_GATE(pwm_ao_d, CLKCTRL_PWM_CLK_AO_CD_CTRL, 24, pwm_ao_d_div); + +static struct clk_regmap pwm_ao_e_sel = + SPI_PWM_CLK_MUX(pwm_ao_e, CLKCTRL_PWM_CLK_AO_EF_CTRL, 0x3, 9, pwm_parents); +static struct clk_regmap pwm_ao_e_div = SPI_PWM_CLK_DIV(pwm_ao_e, CLKCTRL_PWM_CLK_AO_EF_CTRL, 0, 8, pwm_ao_e_sel); +static struct clk_regmap pwm_ao_e = SPI_PWM_CLK_GATE(pwm_ao_e, CLKCTRL_PWM_CLK_AO_EF_CTRL, 8, pwm_ao_e_div); + +static struct clk_regmap pwm_ao_f_sel = + SPI_PWM_CLK_MUX(pwm_ao_f, CLKCTRL_PWM_CLK_AO_EF_CTRL, 0x3, 25, pwm_parents); +static struct clk_regmap pwm_ao_f_div = SPI_PWM_CLK_DIV(pwm_ao_f, CLKCTRL_PWM_CLK_AO_EF_CTRL, 16, 8, pwm_ao_f_sel); +static struct clk_regmap pwm_ao_f = SPI_PWM_CLK_GATE(pwm_ao_f, CLKCTRL_PWM_CLK_AO_EF_CTRL, 24, pwm_ao_f_div); + +static struct clk_regmap pwm_ao_g_sel = + SPI_PWM_CLK_MUX(pwm_ao_g, CLKCTRL_PWM_CLK_AO_GH_CTRL, 0x3, 9, pwm_parents); +static struct clk_regmap pwm_ao_g_div = SPI_PWM_CLK_DIV(pwm_ao_g, CLKCTRL_PWM_CLK_AO_GH_CTRL, 0, 8, pwm_ao_g_sel); +static struct clk_regmap pwm_ao_g = SPI_PWM_CLK_GATE(pwm_ao_g, CLKCTRL_PWM_CLK_AO_GH_CTRL, 8, pwm_ao_g_div); + +static struct clk_regmap pwm_ao_h_sel = + SPI_PWM_CLK_MUX(pwm_ao_h, CLKCTRL_PWM_CLK_AO_GH_CTRL, 0x3, 25, pwm_parents); +static struct clk_regmap pwm_ao_h_div = SPI_PWM_CLK_DIV(pwm_ao_h, CLKCTRL_PWM_CLK_AO_GH_CTRL, 16, 8, pwm_ao_h_sel); +static struct clk_regmap pwm_ao_h = SPI_PWM_CLK_GATE(pwm_ao_h, CLKCTRL_PWM_CLK_AO_GH_CTRL, 24, pwm_ao_h_div); + +#define T7_CLK_GATE(_name, _reg, _bit, _fw_name, _flags) \ +struct clk_regmap _name = { \ + .data = &(struct clk_regmap_gate_data){ \ + .offset = (_reg), \ + .bit_idx = (_bit), \ + }, \ + .hw.init = &(struct clk_init_data) { \ + .name = #_name, \ + .ops = &clk_regmap_gate_ops, \ + .parent_data = &(const struct clk_parent_data) { \ + .fw_name = #_fw_name, \ + }, \ + .num_parents = 1, \ + .flags = (_flags), \ + }, \ +} + +#define T7_SYS_GATE(_name, _reg, _bit, _flags) \ + T7_CLK_GATE(_name, _reg, _bit, sys, _flags) + +static T7_SYS_GATE(sys_ddr, CLKCTRL_SYS_CLK_EN0_REG0, 0, 0); +static T7_SYS_GATE(sys_dos, CLKCTRL_SYS_CLK_EN0_REG0, 1, 0); +static T7_SYS_GATE(sys_mipi_dsi_a, CLKCTRL_SYS_CLK_EN0_REG0, 2, 0); +static T7_SYS_GATE(sys_mipi_dsi_b, CLKCTRL_SYS_CLK_EN0_REG0, 3, 0); +static T7_SYS_GATE(sys_ethphy, CLKCTRL_SYS_CLK_EN0_REG0, 4, 0); +static T7_SYS_GATE(sys_mali, CLKCTRL_SYS_CLK_EN0_REG0, 6, 0); +static T7_SYS_GATE(sys_aocpu, CLKCTRL_SYS_CLK_EN0_REG0, 13, 0); +static T7_SYS_GATE(sys_aucpu, CLKCTRL_SYS_CLK_EN0_REG0, 14, 0); +static T7_SYS_GATE(sys_cec, CLKCTRL_SYS_CLK_EN0_REG0, 16, 0); +static T7_SYS_GATE(sys_gdc, CLKCTRL_SYS_CLK_EN0_REG0, 17, 0); +static T7_SYS_GATE(sys_deswarp, CLKCTRL_SYS_CLK_EN0_REG0, 18, 0); +static T7_SYS_GATE(sys_ampipe_nand, CLKCTRL_SYS_CLK_EN0_REG0, 19, 0); +static T7_SYS_GATE(sys_ampipe_eth, CLKCTRL_SYS_CLK_EN0_REG0, 20, 0); +static T7_SYS_GATE(sys_am2axi0, CLKCTRL_SYS_CLK_EN0_REG0, 21, 0); +static T7_SYS_GATE(sys_am2axi1, CLKCTRL_SYS_CLK_EN0_REG0, 22, 0); +static T7_SYS_GATE(sys_am2axi2, CLKCTRL_SYS_CLK_EN0_REG0, 23, 0); +static T7_SYS_GATE(sys_sdemmca, CLKCTRL_SYS_CLK_EN0_REG0, 24, 0); +static T7_SYS_GATE(sys_sdemmcb, CLKCTRL_SYS_CLK_EN0_REG0, 25, 0); +static T7_SYS_GATE(sys_sdemmcc, CLKCTRL_SYS_CLK_EN0_REG0, 26, 0); +static T7_SYS_GATE(sys_smartcard, CLKCTRL_SYS_CLK_EN0_REG0, 27, 0); +static T7_SYS_GATE(sys_acodec, CLKCTRL_SYS_CLK_EN0_REG0, 28, 0); +static T7_SYS_GATE(sys_spifc, CLKCTRL_SYS_CLK_EN0_REG0, 29, 0); +static T7_SYS_GATE(sys_msr_clk, CLKCTRL_SYS_CLK_EN0_REG0, 30, 0); +static T7_SYS_GATE(sys_ir_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 31, 0); +static T7_SYS_GATE(sys_audio, CLKCTRL_SYS_CLK_EN0_REG1, 0, 0); +static T7_SYS_GATE(sys_eth, CLKCTRL_SYS_CLK_EN0_REG1, 3, 0); +static T7_SYS_GATE(sys_uart_a, CLKCTRL_SYS_CLK_EN0_REG1, 5, 0); +static T7_SYS_GATE(sys_uart_b, CLKCTRL_SYS_CLK_EN0_REG1, 6, 0); +static T7_SYS_GATE(sys_uart_c, CLKCTRL_SYS_CLK_EN0_REG1, 7, 0); +static T7_SYS_GATE(sys_uart_d, CLKCTRL_SYS_CLK_EN0_REG1, 8, 0); +static T7_SYS_GATE(sys_uart_e, CLKCTRL_SYS_CLK_EN0_REG1, 9, 0); +static T7_SYS_GATE(sys_uart_f, CLKCTRL_SYS_CLK_EN0_REG1, 10, 0); +static T7_SYS_GATE(sys_aififo, CLKCTRL_SYS_CLK_EN0_REG1, 11, 0); +static T7_SYS_GATE(sys_spicc2, CLKCTRL_SYS_CLK_EN0_REG1, 12, 0); +static T7_SYS_GATE(sys_spicc3, CLKCTRL_SYS_CLK_EN0_REG1, 13, 0); +static T7_SYS_GATE(sys_spicc4, CLKCTRL_SYS_CLK_EN0_REG1, 14, 0); +static T7_SYS_GATE(sys_ts_a73, CLKCTRL_SYS_CLK_EN0_REG1, 15, 0); +static T7_SYS_GATE(sys_ts_a53, CLKCTRL_SYS_CLK_EN0_REG1, 16, 0); +static T7_SYS_GATE(sys_spicc5, CLKCTRL_SYS_CLK_EN0_REG1, 17, 0); +static T7_SYS_GATE(sys_g2d, CLKCTRL_SYS_CLK_EN0_REG1, 20, 0); +static T7_SYS_GATE(sys_spicc0, CLKCTRL_SYS_CLK_EN0_REG1, 21, 0); +static T7_SYS_GATE(sys_spicc1, CLKCTRL_SYS_CLK_EN0_REG1, 22, 0); +static T7_SYS_GATE(sys_pcie, CLKCTRL_SYS_CLK_EN0_REG1, 24, 0); +static T7_SYS_GATE(sys_usb, CLKCTRL_SYS_CLK_EN0_REG1, 26, 0); +static T7_SYS_GATE(sys_pcie_phy, CLKCTRL_SYS_CLK_EN0_REG1, 27, 0); +static T7_SYS_GATE(sys_i2c_ao_a, CLKCTRL_SYS_CLK_EN0_REG1, 28, 0); +static T7_SYS_GATE(sys_i2c_ao_b, CLKCTRL_SYS_CLK_EN0_REG1, 29, 0); +static T7_SYS_GATE(sys_i2c_m_a, CLKCTRL_SYS_CLK_EN0_REG1, 30, 0); +static T7_SYS_GATE(sys_i2c_m_b, CLKCTRL_SYS_CLK_EN0_REG1, 31, 0); +static T7_SYS_GATE(sys_i2c_m_c, CLKCTRL_SYS_CLK_EN0_REG2, 0, 0); +static T7_SYS_GATE(sys_i2c_m_d, CLKCTRL_SYS_CLK_EN0_REG2, 1, 0); +static T7_SYS_GATE(sys_i2c_m_e, CLKCTRL_SYS_CLK_EN0_REG2, 2, 0); +static T7_SYS_GATE(sys_i2c_m_f, CLKCTRL_SYS_CLK_EN0_REG2, 3, 0); +static T7_SYS_GATE(sys_hdmitx_apb, CLKCTRL_SYS_CLK_EN0_REG2, 4, 0); +static T7_SYS_GATE(sys_i2c_s_a, CLKCTRL_SYS_CLK_EN0_REG2, 5, 0); +static T7_SYS_GATE(sys_hdmirx_pclk, CLKCTRL_SYS_CLK_EN0_REG2, 8, 0); +static T7_SYS_GATE(sys_mmc_apb, CLKCTRL_SYS_CLK_EN0_REG2, 11, 0); +static T7_SYS_GATE(sys_mipi_isp_pclk, CLKCTRL_SYS_CLK_EN0_REG2, 17, 0); +static T7_SYS_GATE(sys_rsa, CLKCTRL_SYS_CLK_EN0_REG2, 18, 0); +static T7_SYS_GATE(sys_pclk_sys_apb, CLKCTRL_SYS_CLK_EN0_REG2, 19, 0); +static T7_SYS_GATE(sys_a73pclk_apb, CLKCTRL_SYS_CLK_EN0_REG2, 20, 0); +static T7_SYS_GATE(sys_dspa, CLKCTRL_SYS_CLK_EN0_REG2, 21, 0); +static T7_SYS_GATE(sys_dspb, CLKCTRL_SYS_CLK_EN0_REG2, 22, 0); +static T7_SYS_GATE(sys_vpu_intr, CLKCTRL_SYS_CLK_EN0_REG2, 25, 0); +static T7_SYS_GATE(sys_sar_adc, CLKCTRL_SYS_CLK_EN0_REG2, 28, 0); +/* + * sys_gic provides the clock for GIC(Generic Interrupt Controller). + * After clock is disabled, The GIC cannot work properly. At present, the driver + * used by our GIC is the public driver in kernel, and there is no management + * clock in the driver. + */ +static T7_SYS_GATE(sys_gic, CLKCTRL_SYS_CLK_EN0_REG2, 30, CLK_IS_CRITICAL); +static T7_SYS_GATE(sys_ts_gpu, CLKCTRL_SYS_CLK_EN0_REG2, 31, 0); +static T7_SYS_GATE(sys_ts_nna, CLKCTRL_SYS_CLK_EN0_REG3, 0, 0); +static T7_SYS_GATE(sys_ts_vpu, CLKCTRL_SYS_CLK_EN0_REG3, 1, 0); +static T7_SYS_GATE(sys_ts_hevc, CLKCTRL_SYS_CLK_EN0_REG3, 2, 0); +static T7_SYS_GATE(sys_pwm_ao_ab, CLKCTRL_SYS_CLK_EN0_REG3, 3, 0); +static T7_SYS_GATE(sys_pwm_ao_cd, CLKCTRL_SYS_CLK_EN0_REG3, 4, 0); +static T7_SYS_GATE(sys_pwm_ao_ef, CLKCTRL_SYS_CLK_EN0_REG3, 5, 0); +static T7_SYS_GATE(sys_pwm_ao_gh, CLKCTRL_SYS_CLK_EN0_REG3, 6, 0); +static T7_SYS_GATE(sys_pwm_ab, CLKCTRL_SYS_CLK_EN0_REG3, 7, 0); +static T7_SYS_GATE(sys_pwm_cd, CLKCTRL_SYS_CLK_EN0_REG3, 8, 0); +static T7_SYS_GATE(sys_pwm_ef, CLKCTRL_SYS_CLK_EN0_REG3, 9, 0); + +/* Array of all clocks registered by this provider */ +static struct clk_hw *t7_periphs_hw_clks[] = { + [CLKID_RTC_32K_IN] = &rtc_32k_in.hw, + [CLKID_RTC_32K_DIV] = &rtc_32k_div.hw, + [CLKID_RTC_32K_FORCE_SEL] = &rtc_32k_force_sel.hw, + [CLKID_RTC_32K_OUT] = &rtc_32k_out.hw, + [CLKID_RTC_32K_MUX0_0] = &rtc_32k_mux0_0.hw, + [CLKID_RTC_32K_MUX0_1] = &rtc_32k_mux0_1.hw, + [CLKID_RTC] = &rtc.hw, + [CLKID_CECB_32K_IN] = &cecb_32k_in.hw, + [CLKID_CECB_32K_DIV] = &cecb_32k_div.hw, + [CLKID_CECB_32K_SEL_PRE] = &cecb_32k_sel_pre.hw, + [CLKID_CECB_32K_SEL] = &cecb_32k_sel.hw, + [CLKID_CECA_32K_IN] = &ceca_32k_in.hw, + [CLKID_CECA_32K_DIV] = &ceca_32k_div.hw, + [CLKID_CECA_32K_SEL_PRE] = &ceca_32k_sel_pre.hw, + [CLKID_CECA_32K_SEL] = &ceca_32k_sel.hw, + [CLKID_CECA_32K] = &ceca_32k_out.hw, + [CLKID_CECB_32K] = &cecb_32k_out.hw, + [CLKID_SC_SEL] = &sc_sel.hw, + [CLKID_SC_DIV] = &sc_div.hw, + [CLKID_SC] = &sc.hw, + [CLKID_DSPA_A_SEL] = &dspa_a_sel.hw, + [CLKID_DSPA_A_DIV] = &dspa_a_div.hw, + [CLKID_DSPA_A] = &dspa_a.hw, + [CLKID_DSPA_B_SEL] = &dspa_b_sel.hw, + [CLKID_DSPA_B_DIV] = &dspa_b_div.hw, + [CLKID_DSPA_B] = &dspa_b.hw, + [CLKID_DSPA] = &dspa.hw, + [CLKID_DSPB_A_SEL] = &dspb_a_sel.hw, + [CLKID_DSPB_A_DIV] = &dspb_a_div.hw, + [CLKID_DSPB_A] = &dspb_a.hw, + [CLKID_DSPB_B_SEL] = &dspb_b_sel.hw, + [CLKID_DSPB_B_DIV] = &dspb_b_div.hw, + [CLKID_DSPB_B] = &dspb_b.hw, + [CLKID_DSPB] = &dspb.hw, + [CLKID_CLK_24M] = &clk_24m.hw, + [CLKID_CLK_24M_DIV2] = &clk_24m_div2.hw, + [CLKID_CLK_12M] = &clk_12m.hw, + [CLKID_ANAKIN_0_SEL] = &anakin_0_sel.hw, + [CLKID_ANAKIN_0_DIV] = &anakin_0_div.hw, + [CLKID_ANAKIN_0] = &anakin_0.hw, + [CLKID_ANAKIN_1_SEL] = &anakin_1_sel.hw, + [CLKID_ANAKIN_1_DIV] = &anakin_1_div.hw, + [CLKID_ANAKIN_1] = &anakin_1.hw, + [CLKID_ANAKIN] = &anakin.hw, + [CLKID_ANAKIN_CLK] = &anakin_clk.hw, + [CLKID_FCLK_DIV2_DIVN_PRE] = &fdiv2_divn_pre.hw, + [CLKID_FCLK_DIV2_DIVN] = &fdiv2_divn.hw, + [CLKID_MIPI_CSI_PHY_0_SEL] = &mipi_csi_phy0_sel.hw, + [CLKID_MIPI_CSI_PHY_0_DIV] = &mipi_csi_phy0_div.hw, + [CLKID_MIPI_CSI_PHY_0] = &mipi_csi_phy0.hw, + [CLKID_MIPI_CSI_PHY_1_SEL] = &mipi_csi_phy1_sel.hw, + [CLKID_MIPI_CSI_PHY_1_DIV] = &mipi_csi_phy1_div.hw, + [CLKID_MIPI_CSI_PHY_1] = &mipi_csi_phy1.hw, + [CLKID_MIPI_CSI_PHY] = &mipi_csi_phy.hw, + [CLKID_MIPI_ISP_SEL] = &mipi_isp_sel.hw, + [CLKID_MIPI_ISP_DIV] = &mipi_isp_div.hw, + [CLKID_MIPI_ISP] = &mipi_isp.hw, + [CLKID_TS_DIV] = &ts_div.hw, + [CLKID_TS] = &ts.hw, + [CLKID_MALI_0_SEL] = &mali_0_sel.hw, + [CLKID_MALI_0_DIV] = &mali_0_div.hw, + [CLKID_MALI_0] = &mali_0.hw, + [CLKID_MALI_1_SEL] = &mali_1_sel.hw, + [CLKID_MALI_1_DIV] = &mali_1_div.hw, + [CLKID_MALI_1] = &mali_1.hw, + [CLKID_MALI] = &mali.hw, + [CLKID_ETH_RMII_SEL] = ð_rmii_sel.hw, + [CLKID_ETH_RMII_DIV] = ð_rmii_div.hw, + [CLKID_ETH_RMII] = ð_rmii.hw, + [CLKID_FCLK_DIV2_DIV8] = &fdiv2_div8.hw, + [CLKID_ETH_125M] = ð_125m.hw, + [CLKID_SD_EMMC_C_SEL] = &sd_emmc_c_sel.hw, + [CLKID_SD_EMMC_C_DIV] = &sd_emmc_c_div.hw, + [CLKID_SD_EMMC_C] = &sd_emmc_c.hw, + [CLKID_SD_EMMC_A_SEL] = &sd_emmc_a_sel.hw, + [CLKID_SD_EMMC_A_DIV] = &sd_emmc_a_div.hw, + [CLKID_SD_EMMC_A] = &sd_emmc_a.hw, + [CLKID_SD_EMMC_B_SEL] = &sd_emmc_b_sel.hw, + [CLKID_SD_EMMC_B_DIV] = &sd_emmc_b_div.hw, + [CLKID_SD_EMMC_B] = &sd_emmc_b.hw, + [CLKID_SPICC0_SEL] = &spicc0_sel.hw, + [CLKID_SPICC0_DIV] = &spicc0_div.hw, + [CLKID_SPICC0] = &spicc0.hw, + [CLKID_SPICC1_SEL] = &spicc1_sel.hw, + [CLKID_SPICC1_DIV] = &spicc1_div.hw, + [CLKID_SPICC1] = &spicc1.hw, + [CLKID_SPICC2_SEL] = &spicc2_sel.hw, + [CLKID_SPICC2_DIV] = &spicc2_div.hw, + [CLKID_SPICC2] = &spicc2.hw, + [CLKID_SPICC3_SEL] = &spicc3_sel.hw, + [CLKID_SPICC3_DIV] = &spicc3_div.hw, + [CLKID_SPICC3] = &spicc3.hw, + [CLKID_SPICC4_SEL] = &spicc4_sel.hw, + [CLKID_SPICC4_DIV] = &spicc4_div.hw, + [CLKID_SPICC4] = &spicc4.hw, + [CLKID_SPICC5_SEL] = &spicc5_sel.hw, + [CLKID_SPICC5_DIV] = &spicc5_div.hw, + [CLKID_SPICC5] = &spicc5.hw, + [CLKID_SARADC_SEL] = &saradc_sel.hw, + [CLKID_SARADC_DIV] = &saradc_div.hw, + [CLKID_SARADC] = &saradc.hw, + [CLKID_PWM_A_SEL] = &pwm_a_sel.hw, + [CLKID_PWM_A_DIV] = &pwm_a_div.hw, + [CLKID_PWM_A] = &pwm_a.hw, + [CLKID_PWM_B_SEL] = &pwm_b_sel.hw, + [CLKID_PWM_B_DIV] = &pwm_b_div.hw, + [CLKID_PWM_B] = &pwm_b.hw, + [CLKID_PWM_C_SEL] = &pwm_c_sel.hw, + [CLKID_PWM_C_DIV] = &pwm_c_div.hw, + [CLKID_PWM_C] = &pwm_c.hw, + [CLKID_PWM_D_SEL] = &pwm_d_sel.hw, + [CLKID_PWM_D_DIV] = &pwm_d_div.hw, + [CLKID_PWM_D] = &pwm_d.hw, + [CLKID_PWM_E_SEL] = &pwm_e_sel.hw, + [CLKID_PWM_E_DIV] = &pwm_e_div.hw, + [CLKID_PWM_E] = &pwm_e.hw, + [CLKID_PWM_F_SEL] = &pwm_f_sel.hw, + [CLKID_PWM_F_DIV] = &pwm_f_div.hw, + [CLKID_PWM_F] = &pwm_f.hw, + [CLKID_PWM_AO_A_SEL] = &pwm_ao_a_sel.hw, + [CLKID_PWM_AO_A_DIV] = &pwm_ao_a_div.hw, + [CLKID_PWM_AO_A] = &pwm_ao_a.hw, + [CLKID_PWM_AO_B_SEL] = &pwm_ao_b_sel.hw, + [CLKID_PWM_AO_B_DIV] = &pwm_ao_b_div.hw, + [CLKID_PWM_AO_B] = &pwm_ao_b.hw, + [CLKID_PWM_AO_C_SEL] = &pwm_ao_c_sel.hw, + [CLKID_PWM_AO_C_DIV] = &pwm_ao_c_div.hw, + [CLKID_PWM_AO_C] = &pwm_ao_c.hw, + [CLKID_PWM_AO_D_SEL] = &pwm_ao_d_sel.hw, + [CLKID_PWM_AO_D_DIV] = &pwm_ao_d_div.hw, + [CLKID_PWM_AO_D] = &pwm_ao_d.hw, + [CLKID_PWM_AO_E_SEL] = &pwm_ao_e_sel.hw, + [CLKID_PWM_AO_E_DIV] = &pwm_ao_e_div.hw, + [CLKID_PWM_AO_E] = &pwm_ao_e.hw, + [CLKID_PWM_AO_F_SEL] = &pwm_ao_f_sel.hw, + [CLKID_PWM_AO_F_DIV] = &pwm_ao_f_div.hw, + [CLKID_PWM_AO_F] = &pwm_ao_f.hw, + [CLKID_PWM_AO_G_SEL] = &pwm_ao_g_sel.hw, + [CLKID_PWM_AO_G_DIV] = &pwm_ao_g_div.hw, + [CLKID_PWM_AO_G] = &pwm_ao_g.hw, + [CLKID_PWM_AO_H_SEL] = &pwm_ao_h_sel.hw, + [CLKID_PWM_AO_H_DIV] = &pwm_ao_h_div.hw, + [CLKID_PWM_AO_H] = &pwm_ao_h.hw, + [CLKID_SYS_DDR] = &sys_ddr.hw, + [CLKID_SYS_DOS] = &sys_dos.hw, + [CLKID_SYS_MIPI_DSI_A] = &sys_mipi_dsi_a.hw, + [CLKID_SYS_MIPI_DSI_B] = &sys_mipi_dsi_b.hw, + [CLKID_SYS_ETHPHY] = &sys_ethphy.hw, + [CLKID_SYS_MALI] = &sys_mali.hw, + [CLKID_SYS_AOCPU] = &sys_aocpu.hw, + [CLKID_SYS_AUCPU] = &sys_aucpu.hw, + [CLKID_SYS_CEC] = &sys_cec.hw, + [CLKID_SYS_GDC] = &sys_gdc.hw, + [CLKID_SYS_DESWARP] = &sys_deswarp.hw, + [CLKID_SYS_AMPIPE_NAND] = &sys_ampipe_nand.hw, + [CLKID_SYS_AMPIPE_ETH] = &sys_ampipe_eth.hw, + [CLKID_SYS_AM2AXI0] = &sys_am2axi0.hw, + [CLKID_SYS_AM2AXI1] = &sys_am2axi1.hw, + [CLKID_SYS_AM2AXI2] = &sys_am2axi2.hw, + [CLKID_SYS_SD_EMMC_A] = &sys_sdemmca.hw, + [CLKID_SYS_SD_EMMC_B] = &sys_sdemmcb.hw, + [CLKID_SYS_SD_EMMC_C] = &sys_sdemmcc.hw, + [CLKID_SYS_SMARTCARD] = &sys_smartcard.hw, + [CLKID_SYS_ACODEC] = &sys_acodec.hw, + [CLKID_SYS_SPIFC] = &sys_spifc.hw, + [CLKID_SYS_MSR_CLK] = &sys_msr_clk.hw, + [CLKID_SYS_IR_CTRL] = &sys_ir_ctrl.hw, + [CLKID_SYS_AUDIO] = &sys_audio.hw, + [CLKID_SYS_ETH] = &sys_eth.hw, + [CLKID_SYS_UART_A] = &sys_uart_a.hw, + [CLKID_SYS_UART_B] = &sys_uart_b.hw, + [CLKID_SYS_UART_C] = &sys_uart_c.hw, + [CLKID_SYS_UART_D] = &sys_uart_d.hw, + [CLKID_SYS_UART_E] = &sys_uart_e.hw, + [CLKID_SYS_UART_F] = &sys_uart_f.hw, + [CLKID_SYS_AIFIFO] = &sys_aififo.hw, + [CLKID_SYS_SPICC2] = &sys_spicc2.hw, + [CLKID_SYS_SPICC3] = &sys_spicc3.hw, + [CLKID_SYS_SPICC4] = &sys_spicc4.hw, + [CLKID_SYS_TS_A73] = &sys_ts_a73.hw, + [CLKID_SYS_TS_A53] = &sys_ts_a53.hw, + [CLKID_SYS_SPICC5] = &sys_spicc5.hw, + [CLKID_SYS_G2D] = &sys_g2d.hw, + [CLKID_SYS_SPICC0] = &sys_spicc0.hw, + [CLKID_SYS_SPICC1] = &sys_spicc1.hw, + [CLKID_SYS_PCIE] = &sys_pcie.hw, + [CLKID_SYS_USB] = &sys_usb.hw, + [CLKID_SYS_PCIE_PHY] = &sys_pcie_phy.hw, + [CLKID_SYS_I2C_AO_A] = &sys_i2c_ao_a.hw, + [CLKID_SYS_I2C_AO_B] = &sys_i2c_ao_b.hw, + [CLKID_SYS_I2C_M_A] = &sys_i2c_m_a.hw, + [CLKID_SYS_I2C_M_B] = &sys_i2c_m_b.hw, + [CLKID_SYS_I2C_M_C] = &sys_i2c_m_c.hw, + [CLKID_SYS_I2C_M_D] = &sys_i2c_m_d.hw, + [CLKID_SYS_I2C_M_E] = &sys_i2c_m_e.hw, + [CLKID_SYS_I2C_M_F] = &sys_i2c_m_f.hw, + [CLKID_SYS_HDMITX_APB] = &sys_hdmitx_apb.hw, + [CLKID_SYS_I2C_S_A] = &sys_i2c_s_a.hw, + [CLKID_SYS_HDMIRX_PCLK] = &sys_hdmirx_pclk.hw, + [CLKID_SYS_MMC_APB] = &sys_mmc_apb.hw, + [CLKID_SYS_MIPI_ISP_PCLK] = &sys_mipi_isp_pclk.hw, + [CLKID_SYS_RSA] = &sys_rsa.hw, + [CLKID_SYS_PCLK_SYS_APB] = &sys_pclk_sys_apb.hw, + [CLKID_SYS_A73PCLK_APB] = &sys_a73pclk_apb.hw, + [CLKID_SYS_DSPA] = &sys_dspa.hw, + [CLKID_SYS_DSPB] = &sys_dspb.hw, + [CLKID_SYS_VPU_INTR] = &sys_vpu_intr.hw, + [CLKID_SYS_SAR_ADC] = &sys_sar_adc.hw, + [CLKID_SYS_GIC] = &sys_gic.hw, + [CLKID_SYS_TS_GPU] = &sys_ts_gpu.hw, + [CLKID_SYS_TS_NNA] = &sys_ts_nna.hw, + [CLKID_SYS_TS_VPU] = &sys_ts_vpu.hw, + [CLKID_SYS_TS_HEVC] = &sys_ts_hevc.hw, + [CLKID_SYS_PWM_AB] = &sys_pwm_ab.hw, + [CLKID_SYS_PWM_CD] = &sys_pwm_cd.hw, + [CLKID_SYS_PWM_EF] = &sys_pwm_ef.hw, + [CLKID_SYS_PWM_AO_AB] = &sys_pwm_ao_ab.hw, + [CLKID_SYS_PWM_AO_CD] = &sys_pwm_ao_cd.hw, + [CLKID_SYS_PWM_AO_EF] = &sys_pwm_ao_ef.hw, + [CLKID_SYS_PWM_AO_GH] = &sys_pwm_ao_gh.hw, +}; + +/* Convenience table to populate regmap in .probe */ +static struct clk_regmap *const t7_periphs_regmaps[] = { + &rtc_32k_in, + &rtc_32k_div, + &rtc_32k_force_sel, + &rtc_32k_out, + &rtc_32k_mux0_0, + &rtc_32k_mux0_1, + &rtc, + &cecb_32k_in, + &cecb_32k_div, + &cecb_32k_sel_pre, + &cecb_32k_sel, + &ceca_32k_in, + &ceca_32k_div, + &ceca_32k_sel_pre, + &ceca_32k_sel, + &ceca_32k_out, + &cecb_32k_out, + &sc_sel, + &sc_div, + &sc, + &dspa_a_sel, + &dspa_a_div, + &dspa_a, + &dspa_b_sel, + &dspa_b_div, + &dspa_b, + &dspa, + &dspb_a_sel, + &dspb_a_div, + &dspb_a, + &dspb_b_sel, + &dspb_b_div, + &dspb_b, + &dspb, + &clk_24m, + &clk_12m, + &anakin_0_sel, + &anakin_0_div, + &anakin_0, + &anakin_1_sel, + &anakin_1_div, + &anakin_1, + &anakin, + &anakin_clk, + &fdiv2_divn_pre, + &fdiv2_divn, + &mipi_csi_phy0_sel, + &mipi_csi_phy0_div, + &mipi_csi_phy0, + &mipi_csi_phy1_sel, + &mipi_csi_phy1_div, + &mipi_csi_phy1, + &mipi_csi_phy, + &mipi_isp_sel, + &mipi_isp_div, + &mipi_isp, + &ts_div, + &ts, + &mali_0_sel, + &mali_0_div, + &mali_0, + &mali_1_sel, + &mali_1_div, + &mali_1, + &mali, + ð_rmii_sel, + ð_rmii_div, + ð_rmii, + ð_125m, + &sd_emmc_c_sel, + &sd_emmc_c_div, + &sd_emmc_c, + &sd_emmc_a_sel, + &sd_emmc_a_div, + &sd_emmc_a, + &sd_emmc_b_sel, + &sd_emmc_b_div, + &sd_emmc_b, + &spicc0_sel, + &spicc0_div, + &spicc0, + &spicc1_sel, + &spicc1_div, + &spicc1, + &spicc2_sel, + &spicc2_div, + &spicc2, + &spicc3_sel, + &spicc3_div, + &spicc3, + &spicc4_sel, + &spicc4_div, + &spicc4, + &spicc5_sel, + &spicc5_div, + &spicc5, + &saradc_sel, + &saradc_div, + &saradc, + &pwm_a_sel, + &pwm_a_div, + &pwm_a, + &pwm_b_sel, + &pwm_b_div, + &pwm_b, + &pwm_c_sel, + &pwm_c_div, + &pwm_c, + &pwm_d_sel, + &pwm_d_div, + &pwm_d, + &pwm_e_sel, + &pwm_e_div, + &pwm_e, + &pwm_f_sel, + &pwm_f_div, + &pwm_f, + &pwm_ao_a_sel, + &pwm_ao_a_div, + &pwm_ao_a, + &pwm_ao_b_sel, + &pwm_ao_b_div, + &pwm_ao_b, + &pwm_ao_c_sel, + &pwm_ao_c_div, + &pwm_ao_c, + &pwm_ao_d_sel, + &pwm_ao_d_div, + &pwm_ao_d, + &pwm_ao_e_sel, + &pwm_ao_e_div, + &pwm_ao_e, + &pwm_ao_f_sel, + &pwm_ao_f_div, + &pwm_ao_f, + &pwm_ao_g_sel, + &pwm_ao_g_div, + &pwm_ao_g, + &pwm_ao_h_sel, + &pwm_ao_h_div, + &pwm_ao_h, + &pwm_ao_h, + &sys_ddr, + &sys_dos, + &sys_mipi_dsi_a, + &sys_mipi_dsi_b, + &sys_ethphy, + &sys_mali, + &sys_aocpu, + &sys_aucpu, + &sys_cec, + &sys_gdc, + &sys_deswarp, + &sys_ampipe_nand, + &sys_ampipe_eth, + &sys_am2axi0, + &sys_am2axi1, + &sys_am2axi2, + &sys_sdemmca, + &sys_sdemmcb, + &sys_sdemmcc, + &sys_smartcard, + &sys_acodec, + &sys_spifc, + &sys_msr_clk, + &sys_ir_ctrl, + &sys_audio, + &sys_eth, + &sys_uart_a, + &sys_uart_b, + &sys_uart_c, + &sys_uart_d, + &sys_uart_e, + &sys_uart_f, + &sys_aififo, + &sys_spicc2, + &sys_spicc3, + &sys_spicc4, + &sys_ts_a73, + &sys_ts_a53, + &sys_spicc5, + &sys_g2d, + &sys_spicc0, + &sys_spicc1, + &sys_pcie, + &sys_usb, + &sys_pcie_phy, + &sys_i2c_ao_a, + &sys_i2c_ao_b, + &sys_i2c_m_a, + &sys_i2c_m_b, + &sys_i2c_m_c, + &sys_i2c_m_d, + &sys_i2c_m_e, + &sys_i2c_m_f, + &sys_hdmitx_apb, + &sys_i2c_s_a, + &sys_hdmirx_pclk, + &sys_mmc_apb, + &sys_mipi_isp_pclk, + &sys_rsa, + &sys_pclk_sys_apb, + &sys_a73pclk_apb, + &sys_dspa, + &sys_dspb, + &sys_vpu_intr, + &sys_sar_adc, + &sys_gic, + &sys_ts_gpu, + &sys_ts_nna, + &sys_ts_vpu, + &sys_ts_hevc, + &sys_pwm_ab, + &sys_pwm_cd, + &sys_pwm_ef, + &sys_pwm_ao_ab, + &sys_pwm_ao_cd, + &sys_pwm_ao_ef, + &sys_pwm_ao_gh, +}; + +static const struct regmap_config t7_periphs_regmap_cfg = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = CLKCTRL_SPICC_CLK_CTRL2 +}; + +static struct meson_clk_hw_data t7_periphs_clks = { + .hws = t7_periphs_hw_clks, + .num = ARRAY_SIZE(t7_periphs_hw_clks), +}; + +static int amlogic_t7_periphs_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + void __iomem *base; + struct regmap *map; + int i, ret; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + map = devm_regmap_init_mmio(dev, base, &t7_periphs_regmap_cfg); + if (IS_ERR(map)) + return PTR_ERR(map); + + /* Populate regmap for the regmap backed clocks */ + for (i = 0; i < ARRAY_SIZE(t7_periphs_regmaps); i++) + t7_periphs_regmaps[i]->map = map; + + for (i = 0; i < t7_periphs_clks.num; i++) { + ret = devm_clk_hw_register(dev, t7_periphs_clks.hws[i]); + if (ret) + return ret; + } + + return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &t7_periphs_clks); +} + +static const struct of_device_id t7_periphs_clkc_match_table[] = { + { .compatible = "amlogic,t7-peripherals-clkc", }, + {} +}; +MODULE_DEVICE_TABLE(of, t7_periphs_clkc_match_table); + +static struct platform_driver t7_periphs_clkc_driver = { + .probe = amlogic_t7_periphs_probe, + .driver = { + .name = "t7-peripherals-clkc", + .of_match_table = t7_periphs_clkc_match_table, + }, +}; + +MODULE_DESCRIPTION("Amlogic T7 Peripherals Clock Controller driver"); +module_platform_driver(t7_periphs_clkc_driver); +MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(CLK_MESON); -- 2.47.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 5/5] clk: meson: t7: add t7 clock peripherals controller driver 2025-01-08 9:40 ` [PATCH v2 5/5] clk: meson: t7: add t7 clock peripherals controller driver Jian Hu @ 2025-01-13 18:18 ` Jerome Brunet 2025-01-17 10:36 ` Jian Hu 0 siblings, 1 reply; 14+ messages in thread From: Jerome Brunet @ 2025-01-13 18:18 UTC (permalink / raw) To: Jian Hu Cc: Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel On Wed 08 Jan 2025 at 17:40, Jian Hu <jian.hu@amlogic.com> wrote: > Add Peripheral clock controller driver for the Amlogic T7 SoC family. > > Signed-off-by: Jian Hu <jian.hu@amlogic.com> > --- > drivers/clk/meson/Kconfig | 13 + > drivers/clk/meson/Makefile | 1 + > drivers/clk/meson/t7-peripherals.c | 2323 ++++++++++++++++++++++++++++ > 3 files changed, 2337 insertions(+) > create mode 100644 drivers/clk/meson/t7-peripherals.c > > diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig > index 6878b035a7ac..1f5fd4c0f79f 100644 > --- a/drivers/clk/meson/Kconfig > +++ b/drivers/clk/meson/Kconfig > @@ -215,4 +215,17 @@ config COMMON_CLK_T7_PLL > device, AKA T7. PLLs are required by most peripheral to operate > Say Y if you are a T7 based device. > > +config COMMON_CLK_T7_PERIPHERALS > + tristate "Amlogic T7 SoC peripherals clock controller support" > + depends on ARM64 > + default y > + select COMMON_CLK_MESON_REGMAP > + select COMMON_CLK_MESON_CLKC_UTILS > + select COMMON_CLK_MESON_DUALDIV > + imply COMMON_CLK_SCMI > + imply COMMON_CLK_T7_PLL > + help > + Support for the Peripherals clock controller on Amlogic A311D2 based > + device, AKA T7. Peripherals are required by most peripheral to operate > + Say Y if you are a T7 based device. > endmenu > diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile > index 646257694c34..6fef3188af30 100644 > --- a/drivers/clk/meson/Makefile > +++ b/drivers/clk/meson/Makefile > @@ -28,3 +28,4 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o > obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o > obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) += s4-peripherals.o > obj-$(CONFIG_COMMON_CLK_T7_PLL) += t7-pll.o > +obj-$(CONFIG_COMMON_CLK_T7_PERIPHERALS) += t7-peripherals.o > diff --git a/drivers/clk/meson/t7-peripherals.c b/drivers/clk/meson/t7-peripherals.c > new file mode 100644 > index 000000000000..4b9c4061ab39 > --- /dev/null > +++ b/drivers/clk/meson/t7-peripherals.c > @@ -0,0 +1,2323 @@ > +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) > +/* > + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. > + * Author: Jian Hu <jian.hu@amlogic.com> > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/platform_device.h> > +#include "clk-dualdiv.h" > +#include "clk-regmap.h" > +#include "meson-clkc-utils.h" > +#include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h> > + > +#define CLKCTRL_RTC_BY_OSCIN_CTRL0 0x8 > +#define CLKCTRL_RTC_BY_OSCIN_CTRL1 0xc > +#define CLKCTRL_RTC_CTRL 0x10 > +#define CLKCTRL_SYS_CLK_CTRL0 0x40 > +#define CLKCTRL_SYS_CLK_EN0_REG0 0x44 > +#define CLKCTRL_SYS_CLK_EN0_REG1 0x48 > +#define CLKCTRL_SYS_CLK_EN0_REG2 0x4c > +#define CLKCTRL_SYS_CLK_EN0_REG3 0x50 > +#define CLKCTRL_CECA_CTRL0 0x88 > +#define CLKCTRL_CECA_CTRL1 0x8c > +#define CLKCTRL_CECB_CTRL0 0x90 > +#define CLKCTRL_CECB_CTRL1 0x94 > +#define CLKCTRL_SC_CLK_CTRL 0x98 > +#define CLKCTRL_DSPA_CLK_CTRL0 0x9c > +#define CLKCTRL_DSPB_CLK_CTRL0 0xa0 > +#define CLKCTRL_CLK12_24_CTRL 0xa8 > +#define CLKCTRL_ANAKIN_CLK_CTRL 0xac > +#define CLKCTRL_MIPI_CSI_PHY_CLK_CTRL 0x10c > +#define CLKCTRL_MIPI_ISP_CLK_CTRL 0x110 > +#define CLKCTRL_TS_CLK_CTRL 0x158 > +#define CLKCTRL_MALI_CLK_CTRL 0x15c > +#define CLKCTRL_ETH_CLK_CTRL 0x164 > +#define CLKCTRL_NAND_CLK_CTRL 0x168 > +#define CLKCTRL_SD_EMMC_CLK_CTRL 0x16c > +#define CLKCTRL_SPICC_CLK_CTRL 0x174 > +#define CLKCTRL_SAR_CLK_CTRL0 0x17c > +#define CLKCTRL_PWM_CLK_AB_CTRL 0x180 > +#define CLKCTRL_PWM_CLK_CD_CTRL 0x184 > +#define CLKCTRL_PWM_CLK_EF_CTRL 0x188 > +#define CLKCTRL_PWM_CLK_AO_AB_CTRL 0x1a0 > +#define CLKCTRL_PWM_CLK_AO_CD_CTRL 0x1a4 > +#define CLKCTRL_PWM_CLK_AO_EF_CTRL 0x1a8 > +#define CLKCTRL_PWM_CLK_AO_GH_CTRL 0x1ac > +#define CLKCTRL_SPICC_CLK_CTRL1 0x1c0 > +#define CLKCTRL_SPICC_CLK_CTRL2 0x1c4 > + > +static struct clk_regmap rtc_32k_in = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_RTC_BY_OSCIN_CTRL0, > + .bit_idx = 31, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "rtc_32k_in", > + .ops = &clk_regmap_gate_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "xtal", > + }, > + .num_parents = 1, > + }, > +}; > + > +static const struct meson_clk_dualdiv_param clk_32k_div_table[] = { > + { > + .n1 = 733, .m1 = 8, > + .n2 = 732, .m2 = 11, > + .dual = 1, > + }, > + {} > +}; > + > +static struct clk_regmap rtc_32k_div = { > + .data = &(struct meson_clk_dualdiv_data){ > + .n1 = { > + .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0, > + .shift = 0, > + .width = 12, > + }, > + .n2 = { > + .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0, > + .shift = 12, > + .width = 12, > + }, > + .m1 = { > + .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL1, > + .shift = 0, > + .width = 12, > + }, > + .m2 = { > + .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL1, > + .shift = 12, > + .width = 12, > + }, > + .dual = { > + .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0, > + .shift = 28, > + .width = 1, > + }, > + .table = clk_32k_div_table, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "rtc_32k_div", > + .ops = &meson_clk_dualdiv_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &rtc_32k_in.hw > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap rtc_32k_force_sel = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_RTC_BY_OSCIN_CTRL1, > + .mask = 0x1, > + .shift = 24, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "rtc_32k_force_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &rtc_32k_div.hw, > + &rtc_32k_in.hw, > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap rtc_32k_out = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_RTC_BY_OSCIN_CTRL0, > + .bit_idx = 30, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "rtc_32k_out", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &rtc_32k_force_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap rtc_32k_mux0_0 = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_RTC_CTRL, > + .mask = 0x1, > + .shift = 0, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "rtc_32k_mux0_0", > + .ops = &clk_regmap_mux_ops, > + .parent_data = (const struct clk_parent_data []) { > + { .fw_name = "xtal", }, > + { .hw = &rtc_32k_out.hw }, > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap rtc_32k_mux0_1 = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_RTC_CTRL, > + .mask = 0x1, > + .shift = 0, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "rtc_32k_mux0_1", > + .ops = &clk_regmap_mux_ops, > + .parent_data = (const struct clk_parent_data []) { > + { .fw_name = "pad", }, > + { .fw_name = "xtal", }, > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap rtc = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_RTC_CTRL, > + .mask = 0x1, > + .shift = 1, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "rtc", > + .ops = &clk_regmap_mux_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &rtc_32k_mux0_0.hw, > + &rtc_32k_mux0_1.hw, > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap ceca_32k_in = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_CECA_CTRL0, > + .bit_idx = 31, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "ceca_32k_in", > + .ops = &clk_regmap_gate_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "xtal", > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap ceca_32k_div = { > + .data = &(struct meson_clk_dualdiv_data){ > + .n1 = { > + .reg_off = CLKCTRL_CECA_CTRL0, > + .shift = 0, > + .width = 12, > + }, > + .n2 = { > + .reg_off = CLKCTRL_CECA_CTRL0, > + .shift = 12, > + .width = 12, > + }, > + .m1 = { > + .reg_off = CLKCTRL_CECA_CTRL1, > + .shift = 0, > + .width = 12, > + }, > + .m2 = { > + .reg_off = CLKCTRL_CECA_CTRL1, > + .shift = 12, > + .width = 12, > + }, > + .dual = { > + .reg_off = CLKCTRL_CECA_CTRL0, > + .shift = 28, > + .width = 1, > + }, > + .table = clk_32k_div_table, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "ceca_32k_div", > + .ops = &meson_clk_dualdiv_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &ceca_32k_in.hw > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap ceca_32k_sel_pre = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_CECA_CTRL1, > + .mask = 0x1, > + .shift = 24, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "ceca_32k_sel_pre", > + .ops = &clk_regmap_mux_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &ceca_32k_div.hw, > + &ceca_32k_in.hw, > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap ceca_32k_sel = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_CECA_CTRL1, > + .mask = 0x1, > + .shift = 31, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "ceca_32k_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &ceca_32k_sel_pre.hw, > + &rtc.hw, > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap ceca_32k_out = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_CECA_CTRL0, > + .bit_idx = 30, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "ceca_32k_out", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &ceca_32k_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap cecb_32k_in = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_CECB_CTRL0, > + .bit_idx = 31, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "cecb_32k_in", > + .ops = &clk_regmap_gate_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "xtal", > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap cecb_32k_div = { > + .data = &(struct meson_clk_dualdiv_data){ > + .n1 = { > + .reg_off = CLKCTRL_CECB_CTRL0, > + .shift = 0, > + .width = 12, > + }, > + .n2 = { > + .reg_off = CLKCTRL_CECB_CTRL0, > + .shift = 12, > + .width = 12, > + }, > + .m1 = { > + .reg_off = CLKCTRL_CECB_CTRL1, > + .shift = 0, > + .width = 12, > + }, > + .m2 = { > + .reg_off = CLKCTRL_CECB_CTRL1, > + .shift = 12, > + .width = 12, > + }, > + .dual = { > + .reg_off = CLKCTRL_CECB_CTRL0, > + .shift = 28, > + .width = 1, > + }, > + .table = clk_32k_div_table, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "cecb_32k_div", > + .ops = &meson_clk_dualdiv_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &cecb_32k_in.hw > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap cecb_32k_sel_pre = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_CECB_CTRL1, > + .mask = 0x1, > + .shift = 24, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "cecb_32k_sel_pre", > + .ops = &clk_regmap_mux_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &cecb_32k_div.hw, > + &cecb_32k_in.hw, > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap cecb_32k_sel = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_CECB_CTRL1, > + .mask = 0x1, > + .shift = 31, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "cecb_32k_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &cecb_32k_sel_pre.hw, > + &rtc.hw, > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap cecb_32k_out = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_CECB_CTRL0, > + .bit_idx = 30, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "cecb_32k_out", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &cecb_32k_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +/* Smartcard Clock */ > +static const struct clk_parent_data sc_parents[] = { > + { .fw_name = "fdiv4", }, > + { .fw_name = "fdiv3", }, > + { .fw_name = "fdiv5", }, > + { .fw_name = "xtal", }, > +}; > + > +static struct clk_regmap sc_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_SC_CLK_CTRL, > + .mask = 0x3, > + .shift = 9, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "sc_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = sc_parents, > + .num_parents = ARRAY_SIZE(sc_parents), > + }, > +}; > + > +static struct clk_regmap sc_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_SC_CLK_CTRL, > + .shift = 0, > + .width = 8, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "sc_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &sc_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap sc = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_SC_CLK_CTRL, > + .bit_idx = 8, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "sc", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &sc_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +/* > + * The DSPA/B IP is clocked by two identical clocks (dspa/b_a and dspa/b_b) > + * muxed by a glitch-free switch. > + */ > +static const struct clk_parent_data dsp_ab_parent_data[] = { > + { .fw_name = "xtal", }, > + { .fw_name = "fdiv2p5", }, > + { .fw_name = "fdiv3", }, > + { .fw_name = "fdiv5", }, > + { .fw_name = "hifi", }, > + { .fw_name = "fdiv4", }, > + { .fw_name = "fdiv7", }, > + { .hw = &rtc.hw }, > +}; > + > +static struct clk_regmap dspa_a_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_DSPA_CLK_CTRL0, > + .mask = 0x7, > + .shift = 10, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "dspa_a_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = dsp_ab_parent_data, > + .num_parents = ARRAY_SIZE(dsp_ab_parent_data), > + }, > +}; > + > +static struct clk_regmap dspa_a_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_DSPA_CLK_CTRL0, > + .shift = 0, > + .width = 10, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "dspa_a_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &dspa_a_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap dspa_a = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_DSPA_CLK_CTRL0, > + .bit_idx = 13, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "dspa_a", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &dspa_a_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap dspa_b_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_DSPA_CLK_CTRL0, > + .mask = 0x7, > + .shift = 26, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "dspa_b_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = dsp_ab_parent_data, > + .num_parents = ARRAY_SIZE(dsp_ab_parent_data), > + }, > +}; > + > +static struct clk_regmap dspa_b_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_DSPA_CLK_CTRL0, > + .shift = 16, > + .width = 10, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "dspa_b_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &dspa_b_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap dspa_b = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_DSPA_CLK_CTRL0, > + .bit_idx = 29, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "dspa_b", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &dspa_b_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap dspa = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_DSPA_CLK_CTRL0, > + .mask = 0x1, > + .shift = 15, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "dspa", > + .ops = &clk_regmap_mux_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &dspa_a.hw, > + &dspa_b.hw, > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap dspb_a_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_DSPB_CLK_CTRL0, > + .mask = 0x7, > + .shift = 10, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "dspb_a_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = dsp_ab_parent_data, > + .num_parents = ARRAY_SIZE(dsp_ab_parent_data), > + }, > +}; > + > +static struct clk_regmap dspb_a_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_DSPB_CLK_CTRL0, > + .shift = 0, > + .width = 10, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "dspb_a_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &dspb_a_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap dspb_a = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_DSPB_CLK_CTRL0, > + .bit_idx = 13, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "dspb_a", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &dspb_a_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap dspb_b_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_DSPB_CLK_CTRL0, > + .mask = 0x7, > + .shift = 26, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "dspb_b_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = dsp_ab_parent_data, > + .num_parents = ARRAY_SIZE(dsp_ab_parent_data), > + }, > +}; > + > +static struct clk_regmap dspb_b_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_DSPB_CLK_CTRL0, > + .shift = 16, > + .width = 10, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "dspb_b_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &dspb_b_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap dspb_b = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_DSPB_CLK_CTRL0, > + .bit_idx = 29, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "dspb_b", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &dspb_b_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap dspb = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_DSPB_CLK_CTRL0, > + .mask = 0x1, > + .shift = 15, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "dspb", > + .ops = &clk_regmap_mux_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &dspb_a.hw, > + &dspb_b.hw, > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap clk_24m = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_CLK12_24_CTRL, > + .bit_idx = 11, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "24m", > + .ops = &clk_regmap_gate_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "xtal", > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_fixed_factor clk_24m_div2 = { > + .mult = 1, > + .div = 2, > + .hw.init = &(struct clk_init_data){ > + .name = "24m_div2", > + .ops = &clk_fixed_factor_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &clk_24m.hw > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap clk_12m = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_CLK12_24_CTRL, > + .bit_idx = 10, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "12m", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &clk_24m_div2.hw > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap fdiv2_divn_pre = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_CLK12_24_CTRL, > + .shift = 0, > + .width = 8, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "fdiv2_divn_pre", > + .ops = &clk_regmap_divider_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "fdiv2", > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap fdiv2_divn = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_CLK12_24_CTRL, > + .bit_idx = 12, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "fdiv2_divn", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &fdiv2_divn_pre.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +/* > + * The NNA IP is clocked by two identical clocks (anakin_0 and anakin_1) > + * muxed by a glitch-free switch. > + */ > +static const struct clk_parent_data anakin_parent_data[] = { > + { .fw_name = "fdiv4", }, > + { .fw_name = "fdiv3", }, > + { .fw_name = "fdiv5", }, > + { .fw_name = "fdiv2", }, > + { .fw_name = "vid_pll0", }, > + { .fw_name = "mpll1", }, > + { .fw_name = "mpll2", }, > + { .fw_name = "fdiv2p5", }, > +}; > + > +static struct clk_regmap anakin_0_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_ANAKIN_CLK_CTRL, > + .mask = 0x7, > + .shift = 9, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "anakin_0_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = anakin_parent_data, > + .num_parents = ARRAY_SIZE(anakin_parent_data), > + }, > +}; > + > +static struct clk_regmap anakin_0_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_ANAKIN_CLK_CTRL, > + .shift = 0, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "anakin_0_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &anakin_0_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap anakin_0 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_ANAKIN_CLK_CTRL, > + .bit_idx = 8, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "anakin_0", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { &anakin_0_div.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap anakin_1_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_ANAKIN_CLK_CTRL, > + .mask = 0x7, > + .shift = 25, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "anakin_1_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = anakin_parent_data, > + .num_parents = ARRAY_SIZE(anakin_parent_data), > + }, > +}; > + > +static struct clk_regmap anakin_1_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_ANAKIN_CLK_CTRL, > + .shift = 16, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "anakin_1_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &anakin_1_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap anakin_1 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_ANAKIN_CLK_CTRL, > + .bit_idx = 24, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "anakin_1", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &anakin_1_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap anakin = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_ANAKIN_CLK_CTRL, > + .mask = 1, > + .shift = 31, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "anakin_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &anakin_0.hw, > + &anakin_1.hw > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT > + }, > +}; > + > +static struct clk_regmap anakin_clk = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_ANAKIN_CLK_CTRL, > + .bit_idx = 30, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "anakin_clk", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &anakin.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT > + }, > +}; > + > +static const struct clk_parent_data mipi_csi_parents[] = { > + { .fw_name = "xtal", }, > + { .fw_name = "gp1", }, > + { .fw_name = "mpll1", }, > + { .fw_name = "mpll2", }, > + { .fw_name = "fdiv3", }, > + { .fw_name = "fdiv4", }, > + { .fw_name = "fdiv5", }, > + { .fw_name = "fdiv7", }, > +}; > + > +static struct clk_regmap mipi_csi_phy0_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, > + .mask = 0x7, > + .shift = 9, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mipi_csi_phy0_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = mipi_csi_parents, > + .num_parents = ARRAY_SIZE(mipi_csi_parents), > + }, > +}; > + > +static struct clk_regmap mipi_csi_phy0_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, > + .shift = 0, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mipi_csi_phy0_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &mipi_csi_phy0_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap mipi_csi_phy0 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, > + .bit_idx = 8, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "mipi_csi_phy0", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &mipi_csi_phy0_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap mipi_csi_phy1_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, > + .mask = 0x7, > + .shift = 25, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mipi_csi_phy1_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = mipi_csi_parents, > + .num_parents = ARRAY_SIZE(mipi_csi_parents), > + }, > +}; > + > +static struct clk_regmap mipi_csi_phy1_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, > + .shift = 16, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mipi_csi_phy1_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &mipi_csi_phy1_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap mipi_csi_phy1 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, > + .bit_idx = 24, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "mipi_csi_phy1", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &mipi_csi_phy1_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap mipi_csi_phy = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_MIPI_CSI_PHY_CLK_CTRL, > + .mask = 0x1, > + .shift = 31, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mipi_csi_phy", > + .ops = &clk_regmap_mux_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &mipi_csi_phy0.hw, > + &mipi_csi_phy1.hw > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static const struct clk_parent_data mipi_isp_parents[] = { > + { .fw_name = "xtal", }, > + { .fw_name = "fdiv4", }, > + { .fw_name = "fdiv3", }, > + { .fw_name = "fdiv5", }, > + { .fw_name = "fdiv7", }, > + { .fw_name = "mpll2", }, > + { .fw_name = "mpll3", }, > + { .fw_name = "gp1", }, > +}; > + > +static struct clk_regmap mipi_isp_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_MIPI_ISP_CLK_CTRL, > + .mask = 0x7, > + .shift = 9, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mipi_isp_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = mipi_isp_parents, > + .num_parents = ARRAY_SIZE(mipi_isp_parents), > + }, > +}; > + > +static struct clk_regmap mipi_isp_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_MIPI_ISP_CLK_CTRL, > + .shift = 0, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mipi_isp_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &mipi_isp_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap mipi_isp = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_MIPI_ISP_CLK_CTRL, > + .bit_idx = 8, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "mipi_isp", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &mipi_isp_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap ts_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_TS_CLK_CTRL, > + .shift = 0, > + .width = 8, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "ts_div", > + .ops = &clk_regmap_divider_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "xtal", > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap ts = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_TS_CLK_CTRL, > + .bit_idx = 8, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "ts", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &ts_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +/* > + * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) > + * muxed by a glitch-free switch. > + */ > +static const struct clk_parent_data mali_parents[] = { > + { .fw_name = "xtal", }, > + { .fw_name = "gp0", }, > + { .fw_name = "gp1", }, > + { .fw_name = "fdiv2p5", }, > + { .fw_name = "fdiv3", }, > + { .fw_name = "fdiv4", }, > + { .fw_name = "fdiv5", }, > + { .fw_name = "fdiv7", }, > +}; > + > +static struct clk_regmap mali_0_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_MALI_CLK_CTRL, > + .mask = 0x7, > + .shift = 9, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mali_0_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = mali_parents, > + .num_parents = ARRAY_SIZE(mali_parents), > + }, > +}; > + > +static struct clk_regmap mali_0_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_MALI_CLK_CTRL, > + .shift = 0, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mali_0_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &mali_0_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap mali_0 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_MALI_CLK_CTRL, > + .bit_idx = 8, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mali_0", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &mali_0_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap mali_1_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_MALI_CLK_CTRL, > + .mask = 0x7, > + .shift = 25, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mali_1_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = mali_parents, > + .num_parents = ARRAY_SIZE(mali_parents), > + }, > +}; > + > +static struct clk_regmap mali_1_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_MALI_CLK_CTRL, > + .shift = 16, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mali_1_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &mali_1_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap mali_1 = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_MALI_CLK_CTRL, > + .bit_idx = 24, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mali_1", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &mali_1_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap mali = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_MALI_CLK_CTRL, > + .mask = 1, > + .shift = 31, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "mali", > + .ops = &clk_regmap_mux_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &mali_0.hw, > + &mali_1.hw, > + }, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static u32 eth_rmii_table[] = { 0, 7 }; > + > +static const struct clk_parent_data eth_rmii_parents[] = { > + { .fw_name = "fdiv2", }, > + { .fw_name = "rmii_pad", }, > +}; > + > +static struct clk_regmap eth_rmii_sel = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_ETH_CLK_CTRL, > + .mask = 0x3, > + .shift = 9, > + .table = eth_rmii_table > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "eth_rmii_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = eth_rmii_parents, > + .num_parents = ARRAY_SIZE(eth_rmii_parents), > + .num_parents = 2 > + }, > +}; > + > +static struct clk_regmap eth_rmii_div = { > + .data = &(struct clk_regmap_div_data) { > + .offset = CLKCTRL_ETH_CLK_CTRL, > + .shift = 0, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "eth_rmii_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + ð_rmii_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap eth_rmii = { > + .data = &(struct clk_regmap_gate_data) { > + .offset = CLKCTRL_ETH_CLK_CTRL, > + .bit_idx = 8, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "eth_rmii", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + ð_rmii_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_fixed_factor fdiv2_div8 = { > + .mult = 1, > + .div = 8, > + .hw.init = &(struct clk_init_data){ > + .name = "fdiv2_div8", > + .ops = &clk_fixed_factor_ops, > + .parent_data = &(const struct clk_parent_data) { > + .fw_name = "fdiv2", > + }, > + .num_parents = 1, > + }, > +}; > + > +static struct clk_regmap eth_125m = { > + .data = &(struct clk_regmap_gate_data) { > + .offset = CLKCTRL_ETH_CLK_CTRL, > + .bit_idx = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "eth_125m", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &fdiv2_div8.hw > + }, > + .num_parents = 1, > + }, > +}; > + > +static const struct clk_parent_data sd_emmc_parents[] = { > + { .fw_name = "xtal", }, > + { .fw_name = "fdiv2", }, > + { .fw_name = "fdiv3", }, > + { .fw_name = "hifi", }, > + { .fw_name = "fdiv2p5", }, > + { .fw_name = "mpll2", }, > + { .fw_name = "mpll3", }, > + { .fw_name = "gp0", }, > +}; > + > +static struct clk_regmap sd_emmc_c_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_NAND_CLK_CTRL, > + .mask = 0x7, > + .shift = 9, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "sd_emmc_c_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = sd_emmc_parents, > + .num_parents = ARRAY_SIZE(sd_emmc_parents), > + }, > +}; > + > +static struct clk_regmap sd_emmc_c_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_NAND_CLK_CTRL, > + .shift = 0, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "sd_emmc_c_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &sd_emmc_c_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap sd_emmc_c = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_NAND_CLK_CTRL, > + .bit_idx = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "sd_emmc_c", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &sd_emmc_c_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap sd_emmc_a_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_SD_EMMC_CLK_CTRL, > + .mask = 0x7, > + .shift = 9, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "sd_emmc_a_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = sd_emmc_parents, > + .num_parents = ARRAY_SIZE(sd_emmc_parents), > + }, > +}; > + > +static struct clk_regmap sd_emmc_a_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_SD_EMMC_CLK_CTRL, > + .shift = 0, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "sd_emmc_a_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &sd_emmc_a_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap sd_emmc_a = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_SD_EMMC_CLK_CTRL, > + .bit_idx = 7, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "sd_emmc_a", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &sd_emmc_a_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap sd_emmc_b_sel = { > + .data = &(struct clk_regmap_mux_data){ > + .offset = CLKCTRL_SD_EMMC_CLK_CTRL, > + .mask = 0x7, > + .shift = 25, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "sd_emmc_b_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = sd_emmc_parents, > + .num_parents = ARRAY_SIZE(sd_emmc_parents), > + }, > +}; > + > +static struct clk_regmap sd_emmc_b_div = { > + .data = &(struct clk_regmap_div_data){ > + .offset = CLKCTRL_SD_EMMC_CLK_CTRL, > + .shift = 16, > + .width = 7, > + }, > + .hw.init = &(struct clk_init_data) { > + .name = "sd_emmc_b_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &sd_emmc_b_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap sd_emmc_b = { > + .data = &(struct clk_regmap_gate_data){ > + .offset = CLKCTRL_SD_EMMC_CLK_CTRL, > + .bit_idx = 23, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "sd_emmc_b", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &sd_emmc_b_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +#define SPI_PWM_CLK_MUX(_name, _reg, _mask, _shift, _parent_data) { \ The same macros keeps getting defined again and again. This has been going on for too long now. I'm addressing the problem it will take a bit of time and I guess it will delay t7 and a5 a bit. > + .data = &(struct clk_regmap_mux_data) { \ > + .offset = _reg, \ > + .mask = _mask, \ > + .shift = _shift, \ > + }, \ > + .hw.init = &(struct clk_init_data) { \ > + .name = #_name "_sel", \ > + .ops = &clk_regmap_mux_ops, \ > + .parent_data = _parent_data, \ > + .num_parents = ARRAY_SIZE(_parent_data), \ > + }, \ > +} > + > +#define SPI_PWM_CLK_DIV(_name, _reg, _shift, _width, _parent) { \ > + .data = &(struct clk_regmap_div_data) { \ > + .offset = _reg, \ > + .shift = _shift, \ > + .width = _width, \ > + }, \ > + .hw.init = &(struct clk_init_data) { \ > + .name = #_name "_div", \ > + .ops = &clk_regmap_divider_ops, \ > + .parent_hws = (const struct clk_hw *[]) { \ > + &_parent.hw \ > + }, \ > + .num_parents = 1, \ > + .flags = CLK_SET_RATE_PARENT, \ > + }, \ > +} > + > +#define SPI_PWM_CLK_GATE(_name, _reg, _bit, _parent) { \ > + .data = &(struct clk_regmap_gate_data) { \ > + .offset = _reg, \ > + .bit_idx = _bit, \ > + }, \ > + .hw.init = &(struct clk_init_data) { \ > + .name = #_name, \ > + .ops = &clk_regmap_gate_ops, \ > + .parent_hws = (const struct clk_hw *[]) { \ > + &_parent.hw \ > + }, \ > + .num_parents = 1, \ > + .flags = CLK_SET_RATE_PARENT, \ > + }, \ > +} > + > +static const struct clk_parent_data spicc_parents[] = { > + { .fw_name = "xtal", }, > + { .fw_name = "sys", }, > + { .fw_name = "fdiv4", }, > + { .fw_name = "fdiv3", }, > + { .fw_name = "fdiv2", }, > + { .fw_name = "fdiv5", }, > + { .fw_name = "fdiv7", }, > + { .fw_name = "gp1", }, > +}; > + > +static struct clk_regmap spicc0_sel = > + SPI_PWM_CLK_MUX(spicc0, CLKCTRL_SPICC_CLK_CTRL, 0x7, 7, spicc_parents); > +static struct clk_regmap spicc0_div = SPI_PWM_CLK_DIV(spicc0, CLKCTRL_SPICC_CLK_CTRL, 0, 6, spicc0_sel); > +static struct clk_regmap spicc0 = SPI_PWM_CLK_GATE(spicc0, CLKCTRL_SPICC_CLK_CTRL, 6, spicc0_div); > + > +static struct clk_regmap spicc1_sel = > + SPI_PWM_CLK_MUX(spicc1, CLKCTRL_SPICC_CLK_CTRL, 0x7, 23, spicc_parents); > +static struct clk_regmap spicc1_div = SPI_PWM_CLK_DIV(spicc1, CLKCTRL_SPICC_CLK_CTRL, 16, 6, spicc1_sel); > +static struct clk_regmap spicc1 = SPI_PWM_CLK_GATE(spicc1, CLKCTRL_SPICC_CLK_CTRL, 22, spicc1_div); > + > +static struct clk_regmap spicc2_sel = > + SPI_PWM_CLK_MUX(spicc2, CLKCTRL_SPICC_CLK_CTRL1, 0x7, 7, spicc_parents); > +static struct clk_regmap spicc2_div = SPI_PWM_CLK_DIV(spicc2, CLKCTRL_SPICC_CLK_CTRL1, 0, 6, spicc2_sel); > +static struct clk_regmap spicc2 = SPI_PWM_CLK_GATE(spicc2, CLKCTRL_SPICC_CLK_CTRL1, 6, spicc2_div); > + > +static struct clk_regmap spicc3_sel = > + SPI_PWM_CLK_MUX(spicc3, CLKCTRL_SPICC_CLK_CTRL1, 0x7, 23, spicc_parents); > +static struct clk_regmap spicc3_div = SPI_PWM_CLK_DIV(spicc3, CLKCTRL_SPICC_CLK_CTRL1, 16, 6, spicc3_sel); > +static struct clk_regmap spicc3 = SPI_PWM_CLK_GATE(spicc3, CLKCTRL_SPICC_CLK_CTRL1, 22, spicc3_div); > + > +static struct clk_regmap spicc4_sel = > + SPI_PWM_CLK_MUX(spicc4, CLKCTRL_SPICC_CLK_CTRL2, 0x7, 7, spicc_parents); > +static struct clk_regmap spicc4_div = SPI_PWM_CLK_DIV(spicc4, CLKCTRL_SPICC_CLK_CTRL2, 0, 6, spicc4_sel); > +static struct clk_regmap spicc4 = SPI_PWM_CLK_GATE(spicc4, CLKCTRL_SPICC_CLK_CTRL2, 6, spicc4_div); > + > +static struct clk_regmap spicc5_sel = > + SPI_PWM_CLK_MUX(spicc5, CLKCTRL_SPICC_CLK_CTRL2, 0x7, 23, spicc_parents); > +static struct clk_regmap spicc5_div = SPI_PWM_CLK_DIV(spicc5, CLKCTRL_SPICC_CLK_CTRL2, 16, 6, spicc5_sel); > +static struct clk_regmap spicc5 = SPI_PWM_CLK_GATE(spicc5, CLKCTRL_SPICC_CLK_CTRL2, 22, spicc5_div); > + > +static struct clk_regmap saradc_sel = { > + .data = &(struct clk_regmap_mux_data) { > + .offset = CLKCTRL_SAR_CLK_CTRL0, > + .mask = 0x1, > + .shift = 9, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "saradc_sel", > + .ops = &clk_regmap_mux_ops, > + .parent_data = (const struct clk_parent_data []) { > + { .fw_name = "xtal", }, > + { .fw_name = "sys", }, > + }, > + .num_parents = 2, > + }, > +}; > + > +static struct clk_regmap saradc_div = { > + .data = &(struct clk_regmap_div_data) { > + .offset = CLKCTRL_SAR_CLK_CTRL0, > + .shift = 0, > + .width = 8, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "saradc_div", > + .ops = &clk_regmap_divider_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &saradc_sel.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static struct clk_regmap saradc = { > + .data = &(struct clk_regmap_gate_data) { > + .offset = CLKCTRL_SAR_CLK_CTRL0, > + .bit_idx = 8, > + }, > + .hw.init = &(struct clk_init_data){ > + .name = "saradc", > + .ops = &clk_regmap_gate_ops, > + .parent_hws = (const struct clk_hw *[]) { > + &saradc_div.hw > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + }, > +}; > + > +static const struct clk_parent_data pwm_parents[] = { > + { .fw_name = "xtal", }, > + { .fw_name = "vid_pll0", }, > + { .fw_name = "fdiv4", }, > + { .fw_name = "fdiv3", }, > +}; > + > +static struct clk_regmap pwm_a_sel = > + SPI_PWM_CLK_MUX(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 0x3, 9, pwm_parents); > +static struct clk_regmap pwm_a_div = SPI_PWM_CLK_DIV(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 0, 8, pwm_a_sel); > +static struct clk_regmap pwm_a = SPI_PWM_CLK_GATE(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 8, pwm_a_div); > + > +static struct clk_regmap pwm_b_sel = > + SPI_PWM_CLK_MUX(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 0x3, 25, pwm_parents); > +static struct clk_regmap pwm_b_div = SPI_PWM_CLK_DIV(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 16, 8, pwm_b_sel); > +static struct clk_regmap pwm_b = SPI_PWM_CLK_GATE(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 24, pwm_b_div); > + > +static struct clk_regmap pwm_c_sel = > + SPI_PWM_CLK_MUX(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 0x3, 9, pwm_parents); > +static struct clk_regmap pwm_c_div = SPI_PWM_CLK_DIV(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 0, 8, pwm_c_sel); > +static struct clk_regmap pwm_c = SPI_PWM_CLK_GATE(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 8, pwm_c_div); > + > +static struct clk_regmap pwm_d_sel = > + SPI_PWM_CLK_MUX(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 0x3, 25, pwm_parents); > +static struct clk_regmap pwm_d_div = SPI_PWM_CLK_DIV(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 16, 8, pwm_d_sel); > +static struct clk_regmap pwm_d = SPI_PWM_CLK_GATE(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 24, pwm_d_div); > + > +static struct clk_regmap pwm_e_sel = > + SPI_PWM_CLK_MUX(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 0x3, 9, pwm_parents); > +static struct clk_regmap pwm_e_div = SPI_PWM_CLK_DIV(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 0, 8, pwm_e_sel); > +static struct clk_regmap pwm_e = SPI_PWM_CLK_GATE(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 8, pwm_e_div); > + > +static struct clk_regmap pwm_f_sel = > + SPI_PWM_CLK_MUX(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 0x3, 25, pwm_parents); > +static struct clk_regmap pwm_f_div = SPI_PWM_CLK_DIV(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 16, 8, pwm_f_sel); > +static struct clk_regmap pwm_f = SPI_PWM_CLK_GATE(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 24, pwm_f_div); > + > +static struct clk_regmap pwm_ao_a_sel = > + SPI_PWM_CLK_MUX(pwm_ao_a, CLKCTRL_PWM_CLK_AO_AB_CTRL, 0x3, 9, pwm_parents); > +static struct clk_regmap pwm_ao_a_div = SPI_PWM_CLK_DIV(pwm_ao_a, CLKCTRL_PWM_CLK_AO_AB_CTRL, 0, 8, pwm_ao_a_sel); > +static struct clk_regmap pwm_ao_a = SPI_PWM_CLK_GATE(pwm_ao_a, CLKCTRL_PWM_CLK_AO_AB_CTRL, 8, pwm_ao_a_div); > + > +static struct clk_regmap pwm_ao_b_sel = > + SPI_PWM_CLK_MUX(pwm_ao_b, CLKCTRL_PWM_CLK_AO_AB_CTRL, 0x3, 25, pwm_parents); > +static struct clk_regmap pwm_ao_b_div = SPI_PWM_CLK_DIV(pwm_ao_b, CLKCTRL_PWM_CLK_AO_AB_CTRL, 16, 8, pwm_ao_b_sel); > +static struct clk_regmap pwm_ao_b = SPI_PWM_CLK_GATE(pwm_ao_b, CLKCTRL_PWM_CLK_AO_AB_CTRL, 24, pwm_ao_b_div); > + > +static struct clk_regmap pwm_ao_c_sel = > + SPI_PWM_CLK_MUX(pwm_ao_c, CLKCTRL_PWM_CLK_AO_CD_CTRL, 0x3, 9, pwm_parents); > +static struct clk_regmap pwm_ao_c_div = SPI_PWM_CLK_DIV(pwm_ao_c, CLKCTRL_PWM_CLK_AO_CD_CTRL, 0, 8, pwm_ao_c_sel); > +static struct clk_regmap pwm_ao_c = SPI_PWM_CLK_GATE(pwm_ao_c, CLKCTRL_PWM_CLK_AO_CD_CTRL, 8, pwm_ao_c_div); > + > +static struct clk_regmap pwm_ao_d_sel = > + SPI_PWM_CLK_MUX(pwm_ao_d, CLKCTRL_PWM_CLK_AO_CD_CTRL, 0x3, 25, pwm_parents); > +static struct clk_regmap pwm_ao_d_div = SPI_PWM_CLK_DIV(pwm_ao_d, CLKCTRL_PWM_CLK_AO_CD_CTRL, 16, 8, pwm_ao_d_sel); > +static struct clk_regmap pwm_ao_d = SPI_PWM_CLK_GATE(pwm_ao_d, CLKCTRL_PWM_CLK_AO_CD_CTRL, 24, pwm_ao_d_div); > + > +static struct clk_regmap pwm_ao_e_sel = > + SPI_PWM_CLK_MUX(pwm_ao_e, CLKCTRL_PWM_CLK_AO_EF_CTRL, 0x3, 9, pwm_parents); > +static struct clk_regmap pwm_ao_e_div = SPI_PWM_CLK_DIV(pwm_ao_e, CLKCTRL_PWM_CLK_AO_EF_CTRL, 0, 8, pwm_ao_e_sel); > +static struct clk_regmap pwm_ao_e = SPI_PWM_CLK_GATE(pwm_ao_e, CLKCTRL_PWM_CLK_AO_EF_CTRL, 8, pwm_ao_e_div); > + > +static struct clk_regmap pwm_ao_f_sel = > + SPI_PWM_CLK_MUX(pwm_ao_f, CLKCTRL_PWM_CLK_AO_EF_CTRL, 0x3, 25, pwm_parents); > +static struct clk_regmap pwm_ao_f_div = SPI_PWM_CLK_DIV(pwm_ao_f, CLKCTRL_PWM_CLK_AO_EF_CTRL, 16, 8, pwm_ao_f_sel); > +static struct clk_regmap pwm_ao_f = SPI_PWM_CLK_GATE(pwm_ao_f, CLKCTRL_PWM_CLK_AO_EF_CTRL, 24, pwm_ao_f_div); > + > +static struct clk_regmap pwm_ao_g_sel = > + SPI_PWM_CLK_MUX(pwm_ao_g, CLKCTRL_PWM_CLK_AO_GH_CTRL, 0x3, 9, pwm_parents); > +static struct clk_regmap pwm_ao_g_div = SPI_PWM_CLK_DIV(pwm_ao_g, CLKCTRL_PWM_CLK_AO_GH_CTRL, 0, 8, pwm_ao_g_sel); > +static struct clk_regmap pwm_ao_g = SPI_PWM_CLK_GATE(pwm_ao_g, CLKCTRL_PWM_CLK_AO_GH_CTRL, 8, pwm_ao_g_div); > + > +static struct clk_regmap pwm_ao_h_sel = > + SPI_PWM_CLK_MUX(pwm_ao_h, CLKCTRL_PWM_CLK_AO_GH_CTRL, 0x3, 25, pwm_parents); > +static struct clk_regmap pwm_ao_h_div = SPI_PWM_CLK_DIV(pwm_ao_h, CLKCTRL_PWM_CLK_AO_GH_CTRL, 16, 8, pwm_ao_h_sel); > +static struct clk_regmap pwm_ao_h = SPI_PWM_CLK_GATE(pwm_ao_h, CLKCTRL_PWM_CLK_AO_GH_CTRL, 24, pwm_ao_h_div); > + > +#define T7_CLK_GATE(_name, _reg, _bit, _fw_name, _flags) \ See, redefining the peripheral once again ... something all the SoCs uses with minor variation. > +struct clk_regmap _name = { \ > + .data = &(struct clk_regmap_gate_data){ \ > + .offset = (_reg), \ > + .bit_idx = (_bit), \ > + }, \ > + .hw.init = &(struct clk_init_data) { \ > + .name = #_name, \ There is an exception in the naming convention for peripheral clocks. The name is soc id prefixed in most SoC. It is these pointless minor diff that makes factorisation difficult. > + .ops = &clk_regmap_gate_ops, \ > + .parent_data = &(const struct clk_parent_data) { \ > + .fw_name = #_fw_name, \ > + }, \ > + .num_parents = 1, \ > + .flags = (_flags), \ > + }, \ > +} > + > +#define T7_SYS_GATE(_name, _reg, _bit, _flags) \ > + T7_CLK_GATE(_name, _reg, _bit, sys, _flags) > + > +static T7_SYS_GATE(sys_ddr, CLKCTRL_SYS_CLK_EN0_REG0, 0, 0); > +static T7_SYS_GATE(sys_dos, CLKCTRL_SYS_CLK_EN0_REG0, 1, 0); > +static T7_SYS_GATE(sys_mipi_dsi_a, CLKCTRL_SYS_CLK_EN0_REG0, 2, 0); > +static T7_SYS_GATE(sys_mipi_dsi_b, CLKCTRL_SYS_CLK_EN0_REG0, 3, 0); > +static T7_SYS_GATE(sys_ethphy, CLKCTRL_SYS_CLK_EN0_REG0, 4, 0); > +static T7_SYS_GATE(sys_mali, CLKCTRL_SYS_CLK_EN0_REG0, 6, 0); > +static T7_SYS_GATE(sys_aocpu, CLKCTRL_SYS_CLK_EN0_REG0, 13, 0); > +static T7_SYS_GATE(sys_aucpu, CLKCTRL_SYS_CLK_EN0_REG0, 14, 0); > +static T7_SYS_GATE(sys_cec, CLKCTRL_SYS_CLK_EN0_REG0, 16, 0); > +static T7_SYS_GATE(sys_gdc, CLKCTRL_SYS_CLK_EN0_REG0, 17, 0); > +static T7_SYS_GATE(sys_deswarp, CLKCTRL_SYS_CLK_EN0_REG0, 18, 0); > +static T7_SYS_GATE(sys_ampipe_nand, CLKCTRL_SYS_CLK_EN0_REG0, 19, 0); > +static T7_SYS_GATE(sys_ampipe_eth, CLKCTRL_SYS_CLK_EN0_REG0, 20, 0); > +static T7_SYS_GATE(sys_am2axi0, CLKCTRL_SYS_CLK_EN0_REG0, 21, 0); > +static T7_SYS_GATE(sys_am2axi1, CLKCTRL_SYS_CLK_EN0_REG0, 22, 0); > +static T7_SYS_GATE(sys_am2axi2, CLKCTRL_SYS_CLK_EN0_REG0, 23, 0); > +static T7_SYS_GATE(sys_sdemmca, CLKCTRL_SYS_CLK_EN0_REG0, 24, 0); > +static T7_SYS_GATE(sys_sdemmcb, CLKCTRL_SYS_CLK_EN0_REG0, 25, 0); > +static T7_SYS_GATE(sys_sdemmcc, CLKCTRL_SYS_CLK_EN0_REG0, 26, 0); > +static T7_SYS_GATE(sys_smartcard, CLKCTRL_SYS_CLK_EN0_REG0, 27, 0); > +static T7_SYS_GATE(sys_acodec, CLKCTRL_SYS_CLK_EN0_REG0, 28, 0); > +static T7_SYS_GATE(sys_spifc, CLKCTRL_SYS_CLK_EN0_REG0, 29, 0); > +static T7_SYS_GATE(sys_msr_clk, CLKCTRL_SYS_CLK_EN0_REG0, 30, 0); > +static T7_SYS_GATE(sys_ir_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 31, 0); > +static T7_SYS_GATE(sys_audio, CLKCTRL_SYS_CLK_EN0_REG1, 0, 0); > +static T7_SYS_GATE(sys_eth, CLKCTRL_SYS_CLK_EN0_REG1, 3, 0); > +static T7_SYS_GATE(sys_uart_a, CLKCTRL_SYS_CLK_EN0_REG1, 5, 0); > +static T7_SYS_GATE(sys_uart_b, CLKCTRL_SYS_CLK_EN0_REG1, 6, 0); > +static T7_SYS_GATE(sys_uart_c, CLKCTRL_SYS_CLK_EN0_REG1, 7, 0); > +static T7_SYS_GATE(sys_uart_d, CLKCTRL_SYS_CLK_EN0_REG1, 8, 0); > +static T7_SYS_GATE(sys_uart_e, CLKCTRL_SYS_CLK_EN0_REG1, 9, 0); > +static T7_SYS_GATE(sys_uart_f, CLKCTRL_SYS_CLK_EN0_REG1, 10, 0); > +static T7_SYS_GATE(sys_aififo, CLKCTRL_SYS_CLK_EN0_REG1, 11, 0); > +static T7_SYS_GATE(sys_spicc2, CLKCTRL_SYS_CLK_EN0_REG1, 12, 0); > +static T7_SYS_GATE(sys_spicc3, CLKCTRL_SYS_CLK_EN0_REG1, 13, 0); > +static T7_SYS_GATE(sys_spicc4, CLKCTRL_SYS_CLK_EN0_REG1, 14, 0); > +static T7_SYS_GATE(sys_ts_a73, CLKCTRL_SYS_CLK_EN0_REG1, 15, 0); > +static T7_SYS_GATE(sys_ts_a53, CLKCTRL_SYS_CLK_EN0_REG1, 16, 0); > +static T7_SYS_GATE(sys_spicc5, CLKCTRL_SYS_CLK_EN0_REG1, 17, 0); > +static T7_SYS_GATE(sys_g2d, CLKCTRL_SYS_CLK_EN0_REG1, 20, 0); > +static T7_SYS_GATE(sys_spicc0, CLKCTRL_SYS_CLK_EN0_REG1, 21, 0); > +static T7_SYS_GATE(sys_spicc1, CLKCTRL_SYS_CLK_EN0_REG1, 22, 0); > +static T7_SYS_GATE(sys_pcie, CLKCTRL_SYS_CLK_EN0_REG1, 24, 0); > +static T7_SYS_GATE(sys_usb, CLKCTRL_SYS_CLK_EN0_REG1, 26, 0); > +static T7_SYS_GATE(sys_pcie_phy, CLKCTRL_SYS_CLK_EN0_REG1, 27, 0); > +static T7_SYS_GATE(sys_i2c_ao_a, CLKCTRL_SYS_CLK_EN0_REG1, 28, 0); > +static T7_SYS_GATE(sys_i2c_ao_b, CLKCTRL_SYS_CLK_EN0_REG1, 29, 0); > +static T7_SYS_GATE(sys_i2c_m_a, CLKCTRL_SYS_CLK_EN0_REG1, 30, 0); > +static T7_SYS_GATE(sys_i2c_m_b, CLKCTRL_SYS_CLK_EN0_REG1, 31, 0); > +static T7_SYS_GATE(sys_i2c_m_c, CLKCTRL_SYS_CLK_EN0_REG2, 0, 0); > +static T7_SYS_GATE(sys_i2c_m_d, CLKCTRL_SYS_CLK_EN0_REG2, 1, 0); > +static T7_SYS_GATE(sys_i2c_m_e, CLKCTRL_SYS_CLK_EN0_REG2, 2, 0); > +static T7_SYS_GATE(sys_i2c_m_f, CLKCTRL_SYS_CLK_EN0_REG2, 3, 0); > +static T7_SYS_GATE(sys_hdmitx_apb, CLKCTRL_SYS_CLK_EN0_REG2, 4, 0); > +static T7_SYS_GATE(sys_i2c_s_a, CLKCTRL_SYS_CLK_EN0_REG2, 5, 0); > +static T7_SYS_GATE(sys_hdmirx_pclk, CLKCTRL_SYS_CLK_EN0_REG2, 8, 0); > +static T7_SYS_GATE(sys_mmc_apb, CLKCTRL_SYS_CLK_EN0_REG2, 11, 0); > +static T7_SYS_GATE(sys_mipi_isp_pclk, CLKCTRL_SYS_CLK_EN0_REG2, 17, 0); > +static T7_SYS_GATE(sys_rsa, CLKCTRL_SYS_CLK_EN0_REG2, 18, 0); > +static T7_SYS_GATE(sys_pclk_sys_apb, CLKCTRL_SYS_CLK_EN0_REG2, 19, 0); > +static T7_SYS_GATE(sys_a73pclk_apb, CLKCTRL_SYS_CLK_EN0_REG2, 20, 0); > +static T7_SYS_GATE(sys_dspa, CLKCTRL_SYS_CLK_EN0_REG2, 21, 0); > +static T7_SYS_GATE(sys_dspb, CLKCTRL_SYS_CLK_EN0_REG2, 22, 0); > +static T7_SYS_GATE(sys_vpu_intr, CLKCTRL_SYS_CLK_EN0_REG2, 25, 0); > +static T7_SYS_GATE(sys_sar_adc, CLKCTRL_SYS_CLK_EN0_REG2, 28, 0); > +/* > + * sys_gic provides the clock for GIC(Generic Interrupt Controller). > + * After clock is disabled, The GIC cannot work properly. At present, the driver > + * used by our GIC is the public driver in kernel, and there is no management > + * clock in the driver. > + */ > +static T7_SYS_GATE(sys_gic, CLKCTRL_SYS_CLK_EN0_REG2, 30, CLK_IS_CRITICAL); > +static T7_SYS_GATE(sys_ts_gpu, CLKCTRL_SYS_CLK_EN0_REG2, 31, 0); > +static T7_SYS_GATE(sys_ts_nna, CLKCTRL_SYS_CLK_EN0_REG3, 0, 0); > +static T7_SYS_GATE(sys_ts_vpu, CLKCTRL_SYS_CLK_EN0_REG3, 1, 0); > +static T7_SYS_GATE(sys_ts_hevc, CLKCTRL_SYS_CLK_EN0_REG3, 2, 0); > +static T7_SYS_GATE(sys_pwm_ao_ab, CLKCTRL_SYS_CLK_EN0_REG3, 3, 0); > +static T7_SYS_GATE(sys_pwm_ao_cd, CLKCTRL_SYS_CLK_EN0_REG3, 4, 0); > +static T7_SYS_GATE(sys_pwm_ao_ef, CLKCTRL_SYS_CLK_EN0_REG3, 5, 0); > +static T7_SYS_GATE(sys_pwm_ao_gh, CLKCTRL_SYS_CLK_EN0_REG3, 6, 0); > +static T7_SYS_GATE(sys_pwm_ab, CLKCTRL_SYS_CLK_EN0_REG3, 7, 0); > +static T7_SYS_GATE(sys_pwm_cd, CLKCTRL_SYS_CLK_EN0_REG3, 8, 0); > +static T7_SYS_GATE(sys_pwm_ef, CLKCTRL_SYS_CLK_EN0_REG3, 9, 0); > + > +/* Array of all clocks registered by this provider */ > +static struct clk_hw *t7_periphs_hw_clks[] = { > + [CLKID_RTC_32K_IN] = &rtc_32k_in.hw, > + [CLKID_RTC_32K_DIV] = &rtc_32k_div.hw, > + [CLKID_RTC_32K_FORCE_SEL] = &rtc_32k_force_sel.hw, > + [CLKID_RTC_32K_OUT] = &rtc_32k_out.hw, > + [CLKID_RTC_32K_MUX0_0] = &rtc_32k_mux0_0.hw, > + [CLKID_RTC_32K_MUX0_1] = &rtc_32k_mux0_1.hw, > + [CLKID_RTC] = &rtc.hw, > + [CLKID_CECB_32K_IN] = &cecb_32k_in.hw, > + [CLKID_CECB_32K_DIV] = &cecb_32k_div.hw, > + [CLKID_CECB_32K_SEL_PRE] = &cecb_32k_sel_pre.hw, > + [CLKID_CECB_32K_SEL] = &cecb_32k_sel.hw, > + [CLKID_CECA_32K_IN] = &ceca_32k_in.hw, > + [CLKID_CECA_32K_DIV] = &ceca_32k_div.hw, > + [CLKID_CECA_32K_SEL_PRE] = &ceca_32k_sel_pre.hw, > + [CLKID_CECA_32K_SEL] = &ceca_32k_sel.hw, > + [CLKID_CECA_32K] = &ceca_32k_out.hw, > + [CLKID_CECB_32K] = &cecb_32k_out.hw, > + [CLKID_SC_SEL] = &sc_sel.hw, > + [CLKID_SC_DIV] = &sc_div.hw, > + [CLKID_SC] = &sc.hw, > + [CLKID_DSPA_A_SEL] = &dspa_a_sel.hw, > + [CLKID_DSPA_A_DIV] = &dspa_a_div.hw, > + [CLKID_DSPA_A] = &dspa_a.hw, > + [CLKID_DSPA_B_SEL] = &dspa_b_sel.hw, > + [CLKID_DSPA_B_DIV] = &dspa_b_div.hw, > + [CLKID_DSPA_B] = &dspa_b.hw, > + [CLKID_DSPA] = &dspa.hw, > + [CLKID_DSPB_A_SEL] = &dspb_a_sel.hw, > + [CLKID_DSPB_A_DIV] = &dspb_a_div.hw, > + [CLKID_DSPB_A] = &dspb_a.hw, > + [CLKID_DSPB_B_SEL] = &dspb_b_sel.hw, > + [CLKID_DSPB_B_DIV] = &dspb_b_div.hw, > + [CLKID_DSPB_B] = &dspb_b.hw, > + [CLKID_DSPB] = &dspb.hw, > + [CLKID_CLK_24M] = &clk_24m.hw, > + [CLKID_CLK_24M_DIV2] = &clk_24m_div2.hw, > + [CLKID_CLK_12M] = &clk_12m.hw, > + [CLKID_ANAKIN_0_SEL] = &anakin_0_sel.hw, > + [CLKID_ANAKIN_0_DIV] = &anakin_0_div.hw, > + [CLKID_ANAKIN_0] = &anakin_0.hw, > + [CLKID_ANAKIN_1_SEL] = &anakin_1_sel.hw, > + [CLKID_ANAKIN_1_DIV] = &anakin_1_div.hw, > + [CLKID_ANAKIN_1] = &anakin_1.hw, > + [CLKID_ANAKIN] = &anakin.hw, > + [CLKID_ANAKIN_CLK] = &anakin_clk.hw, > + [CLKID_FCLK_DIV2_DIVN_PRE] = &fdiv2_divn_pre.hw, > + [CLKID_FCLK_DIV2_DIVN] = &fdiv2_divn.hw, > + [CLKID_MIPI_CSI_PHY_0_SEL] = &mipi_csi_phy0_sel.hw, > + [CLKID_MIPI_CSI_PHY_0_DIV] = &mipi_csi_phy0_div.hw, > + [CLKID_MIPI_CSI_PHY_0] = &mipi_csi_phy0.hw, > + [CLKID_MIPI_CSI_PHY_1_SEL] = &mipi_csi_phy1_sel.hw, > + [CLKID_MIPI_CSI_PHY_1_DIV] = &mipi_csi_phy1_div.hw, > + [CLKID_MIPI_CSI_PHY_1] = &mipi_csi_phy1.hw, > + [CLKID_MIPI_CSI_PHY] = &mipi_csi_phy.hw, > + [CLKID_MIPI_ISP_SEL] = &mipi_isp_sel.hw, > + [CLKID_MIPI_ISP_DIV] = &mipi_isp_div.hw, > + [CLKID_MIPI_ISP] = &mipi_isp.hw, > + [CLKID_TS_DIV] = &ts_div.hw, > + [CLKID_TS] = &ts.hw, > + [CLKID_MALI_0_SEL] = &mali_0_sel.hw, > + [CLKID_MALI_0_DIV] = &mali_0_div.hw, > + [CLKID_MALI_0] = &mali_0.hw, > + [CLKID_MALI_1_SEL] = &mali_1_sel.hw, > + [CLKID_MALI_1_DIV] = &mali_1_div.hw, > + [CLKID_MALI_1] = &mali_1.hw, > + [CLKID_MALI] = &mali.hw, > + [CLKID_ETH_RMII_SEL] = ð_rmii_sel.hw, > + [CLKID_ETH_RMII_DIV] = ð_rmii_div.hw, > + [CLKID_ETH_RMII] = ð_rmii.hw, > + [CLKID_FCLK_DIV2_DIV8] = &fdiv2_div8.hw, > + [CLKID_ETH_125M] = ð_125m.hw, > + [CLKID_SD_EMMC_C_SEL] = &sd_emmc_c_sel.hw, > + [CLKID_SD_EMMC_C_DIV] = &sd_emmc_c_div.hw, > + [CLKID_SD_EMMC_C] = &sd_emmc_c.hw, > + [CLKID_SD_EMMC_A_SEL] = &sd_emmc_a_sel.hw, > + [CLKID_SD_EMMC_A_DIV] = &sd_emmc_a_div.hw, > + [CLKID_SD_EMMC_A] = &sd_emmc_a.hw, > + [CLKID_SD_EMMC_B_SEL] = &sd_emmc_b_sel.hw, > + [CLKID_SD_EMMC_B_DIV] = &sd_emmc_b_div.hw, > + [CLKID_SD_EMMC_B] = &sd_emmc_b.hw, > + [CLKID_SPICC0_SEL] = &spicc0_sel.hw, > + [CLKID_SPICC0_DIV] = &spicc0_div.hw, > + [CLKID_SPICC0] = &spicc0.hw, > + [CLKID_SPICC1_SEL] = &spicc1_sel.hw, > + [CLKID_SPICC1_DIV] = &spicc1_div.hw, > + [CLKID_SPICC1] = &spicc1.hw, > + [CLKID_SPICC2_SEL] = &spicc2_sel.hw, > + [CLKID_SPICC2_DIV] = &spicc2_div.hw, > + [CLKID_SPICC2] = &spicc2.hw, > + [CLKID_SPICC3_SEL] = &spicc3_sel.hw, > + [CLKID_SPICC3_DIV] = &spicc3_div.hw, > + [CLKID_SPICC3] = &spicc3.hw, > + [CLKID_SPICC4_SEL] = &spicc4_sel.hw, > + [CLKID_SPICC4_DIV] = &spicc4_div.hw, > + [CLKID_SPICC4] = &spicc4.hw, > + [CLKID_SPICC5_SEL] = &spicc5_sel.hw, > + [CLKID_SPICC5_DIV] = &spicc5_div.hw, > + [CLKID_SPICC5] = &spicc5.hw, > + [CLKID_SARADC_SEL] = &saradc_sel.hw, > + [CLKID_SARADC_DIV] = &saradc_div.hw, > + [CLKID_SARADC] = &saradc.hw, > + [CLKID_PWM_A_SEL] = &pwm_a_sel.hw, > + [CLKID_PWM_A_DIV] = &pwm_a_div.hw, > + [CLKID_PWM_A] = &pwm_a.hw, > + [CLKID_PWM_B_SEL] = &pwm_b_sel.hw, > + [CLKID_PWM_B_DIV] = &pwm_b_div.hw, > + [CLKID_PWM_B] = &pwm_b.hw, > + [CLKID_PWM_C_SEL] = &pwm_c_sel.hw, > + [CLKID_PWM_C_DIV] = &pwm_c_div.hw, > + [CLKID_PWM_C] = &pwm_c.hw, > + [CLKID_PWM_D_SEL] = &pwm_d_sel.hw, > + [CLKID_PWM_D_DIV] = &pwm_d_div.hw, > + [CLKID_PWM_D] = &pwm_d.hw, > + [CLKID_PWM_E_SEL] = &pwm_e_sel.hw, > + [CLKID_PWM_E_DIV] = &pwm_e_div.hw, > + [CLKID_PWM_E] = &pwm_e.hw, > + [CLKID_PWM_F_SEL] = &pwm_f_sel.hw, > + [CLKID_PWM_F_DIV] = &pwm_f_div.hw, > + [CLKID_PWM_F] = &pwm_f.hw, > + [CLKID_PWM_AO_A_SEL] = &pwm_ao_a_sel.hw, > + [CLKID_PWM_AO_A_DIV] = &pwm_ao_a_div.hw, > + [CLKID_PWM_AO_A] = &pwm_ao_a.hw, > + [CLKID_PWM_AO_B_SEL] = &pwm_ao_b_sel.hw, > + [CLKID_PWM_AO_B_DIV] = &pwm_ao_b_div.hw, > + [CLKID_PWM_AO_B] = &pwm_ao_b.hw, > + [CLKID_PWM_AO_C_SEL] = &pwm_ao_c_sel.hw, > + [CLKID_PWM_AO_C_DIV] = &pwm_ao_c_div.hw, > + [CLKID_PWM_AO_C] = &pwm_ao_c.hw, > + [CLKID_PWM_AO_D_SEL] = &pwm_ao_d_sel.hw, > + [CLKID_PWM_AO_D_DIV] = &pwm_ao_d_div.hw, > + [CLKID_PWM_AO_D] = &pwm_ao_d.hw, > + [CLKID_PWM_AO_E_SEL] = &pwm_ao_e_sel.hw, > + [CLKID_PWM_AO_E_DIV] = &pwm_ao_e_div.hw, > + [CLKID_PWM_AO_E] = &pwm_ao_e.hw, > + [CLKID_PWM_AO_F_SEL] = &pwm_ao_f_sel.hw, > + [CLKID_PWM_AO_F_DIV] = &pwm_ao_f_div.hw, > + [CLKID_PWM_AO_F] = &pwm_ao_f.hw, > + [CLKID_PWM_AO_G_SEL] = &pwm_ao_g_sel.hw, > + [CLKID_PWM_AO_G_DIV] = &pwm_ao_g_div.hw, > + [CLKID_PWM_AO_G] = &pwm_ao_g.hw, > + [CLKID_PWM_AO_H_SEL] = &pwm_ao_h_sel.hw, > + [CLKID_PWM_AO_H_DIV] = &pwm_ao_h_div.hw, > + [CLKID_PWM_AO_H] = &pwm_ao_h.hw, > + [CLKID_SYS_DDR] = &sys_ddr.hw, > + [CLKID_SYS_DOS] = &sys_dos.hw, > + [CLKID_SYS_MIPI_DSI_A] = &sys_mipi_dsi_a.hw, > + [CLKID_SYS_MIPI_DSI_B] = &sys_mipi_dsi_b.hw, > + [CLKID_SYS_ETHPHY] = &sys_ethphy.hw, > + [CLKID_SYS_MALI] = &sys_mali.hw, > + [CLKID_SYS_AOCPU] = &sys_aocpu.hw, > + [CLKID_SYS_AUCPU] = &sys_aucpu.hw, > + [CLKID_SYS_CEC] = &sys_cec.hw, > + [CLKID_SYS_GDC] = &sys_gdc.hw, > + [CLKID_SYS_DESWARP] = &sys_deswarp.hw, > + [CLKID_SYS_AMPIPE_NAND] = &sys_ampipe_nand.hw, > + [CLKID_SYS_AMPIPE_ETH] = &sys_ampipe_eth.hw, > + [CLKID_SYS_AM2AXI0] = &sys_am2axi0.hw, > + [CLKID_SYS_AM2AXI1] = &sys_am2axi1.hw, > + [CLKID_SYS_AM2AXI2] = &sys_am2axi2.hw, > + [CLKID_SYS_SD_EMMC_A] = &sys_sdemmca.hw, > + [CLKID_SYS_SD_EMMC_B] = &sys_sdemmcb.hw, > + [CLKID_SYS_SD_EMMC_C] = &sys_sdemmcc.hw, > + [CLKID_SYS_SMARTCARD] = &sys_smartcard.hw, > + [CLKID_SYS_ACODEC] = &sys_acodec.hw, > + [CLKID_SYS_SPIFC] = &sys_spifc.hw, > + [CLKID_SYS_MSR_CLK] = &sys_msr_clk.hw, > + [CLKID_SYS_IR_CTRL] = &sys_ir_ctrl.hw, > + [CLKID_SYS_AUDIO] = &sys_audio.hw, > + [CLKID_SYS_ETH] = &sys_eth.hw, > + [CLKID_SYS_UART_A] = &sys_uart_a.hw, > + [CLKID_SYS_UART_B] = &sys_uart_b.hw, > + [CLKID_SYS_UART_C] = &sys_uart_c.hw, > + [CLKID_SYS_UART_D] = &sys_uart_d.hw, > + [CLKID_SYS_UART_E] = &sys_uart_e.hw, > + [CLKID_SYS_UART_F] = &sys_uart_f.hw, > + [CLKID_SYS_AIFIFO] = &sys_aififo.hw, > + [CLKID_SYS_SPICC2] = &sys_spicc2.hw, > + [CLKID_SYS_SPICC3] = &sys_spicc3.hw, > + [CLKID_SYS_SPICC4] = &sys_spicc4.hw, > + [CLKID_SYS_TS_A73] = &sys_ts_a73.hw, > + [CLKID_SYS_TS_A53] = &sys_ts_a53.hw, > + [CLKID_SYS_SPICC5] = &sys_spicc5.hw, > + [CLKID_SYS_G2D] = &sys_g2d.hw, > + [CLKID_SYS_SPICC0] = &sys_spicc0.hw, > + [CLKID_SYS_SPICC1] = &sys_spicc1.hw, > + [CLKID_SYS_PCIE] = &sys_pcie.hw, > + [CLKID_SYS_USB] = &sys_usb.hw, > + [CLKID_SYS_PCIE_PHY] = &sys_pcie_phy.hw, > + [CLKID_SYS_I2C_AO_A] = &sys_i2c_ao_a.hw, > + [CLKID_SYS_I2C_AO_B] = &sys_i2c_ao_b.hw, > + [CLKID_SYS_I2C_M_A] = &sys_i2c_m_a.hw, > + [CLKID_SYS_I2C_M_B] = &sys_i2c_m_b.hw, > + [CLKID_SYS_I2C_M_C] = &sys_i2c_m_c.hw, > + [CLKID_SYS_I2C_M_D] = &sys_i2c_m_d.hw, > + [CLKID_SYS_I2C_M_E] = &sys_i2c_m_e.hw, > + [CLKID_SYS_I2C_M_F] = &sys_i2c_m_f.hw, > + [CLKID_SYS_HDMITX_APB] = &sys_hdmitx_apb.hw, > + [CLKID_SYS_I2C_S_A] = &sys_i2c_s_a.hw, > + [CLKID_SYS_HDMIRX_PCLK] = &sys_hdmirx_pclk.hw, > + [CLKID_SYS_MMC_APB] = &sys_mmc_apb.hw, > + [CLKID_SYS_MIPI_ISP_PCLK] = &sys_mipi_isp_pclk.hw, > + [CLKID_SYS_RSA] = &sys_rsa.hw, > + [CLKID_SYS_PCLK_SYS_APB] = &sys_pclk_sys_apb.hw, > + [CLKID_SYS_A73PCLK_APB] = &sys_a73pclk_apb.hw, > + [CLKID_SYS_DSPA] = &sys_dspa.hw, > + [CLKID_SYS_DSPB] = &sys_dspb.hw, > + [CLKID_SYS_VPU_INTR] = &sys_vpu_intr.hw, > + [CLKID_SYS_SAR_ADC] = &sys_sar_adc.hw, > + [CLKID_SYS_GIC] = &sys_gic.hw, > + [CLKID_SYS_TS_GPU] = &sys_ts_gpu.hw, > + [CLKID_SYS_TS_NNA] = &sys_ts_nna.hw, > + [CLKID_SYS_TS_VPU] = &sys_ts_vpu.hw, > + [CLKID_SYS_TS_HEVC] = &sys_ts_hevc.hw, > + [CLKID_SYS_PWM_AB] = &sys_pwm_ab.hw, > + [CLKID_SYS_PWM_CD] = &sys_pwm_cd.hw, > + [CLKID_SYS_PWM_EF] = &sys_pwm_ef.hw, > + [CLKID_SYS_PWM_AO_AB] = &sys_pwm_ao_ab.hw, > + [CLKID_SYS_PWM_AO_CD] = &sys_pwm_ao_cd.hw, > + [CLKID_SYS_PWM_AO_EF] = &sys_pwm_ao_ef.hw, > + [CLKID_SYS_PWM_AO_GH] = &sys_pwm_ao_gh.hw, > +}; > + > +/* Convenience table to populate regmap in .probe */ > +static struct clk_regmap *const t7_periphs_regmaps[] = { > + &rtc_32k_in, > + &rtc_32k_div, > + &rtc_32k_force_sel, > + &rtc_32k_out, > + &rtc_32k_mux0_0, > + &rtc_32k_mux0_1, > + &rtc, > + &cecb_32k_in, > + &cecb_32k_div, > + &cecb_32k_sel_pre, > + &cecb_32k_sel, > + &ceca_32k_in, > + &ceca_32k_div, > + &ceca_32k_sel_pre, > + &ceca_32k_sel, > + &ceca_32k_out, > + &cecb_32k_out, > + &sc_sel, > + &sc_div, > + &sc, > + &dspa_a_sel, > + &dspa_a_div, > + &dspa_a, > + &dspa_b_sel, > + &dspa_b_div, > + &dspa_b, > + &dspa, > + &dspb_a_sel, > + &dspb_a_div, > + &dspb_a, > + &dspb_b_sel, > + &dspb_b_div, > + &dspb_b, > + &dspb, > + &clk_24m, > + &clk_12m, > + &anakin_0_sel, > + &anakin_0_div, > + &anakin_0, > + &anakin_1_sel, > + &anakin_1_div, > + &anakin_1, > + &anakin, > + &anakin_clk, > + &fdiv2_divn_pre, > + &fdiv2_divn, > + &mipi_csi_phy0_sel, > + &mipi_csi_phy0_div, > + &mipi_csi_phy0, > + &mipi_csi_phy1_sel, > + &mipi_csi_phy1_div, > + &mipi_csi_phy1, > + &mipi_csi_phy, > + &mipi_isp_sel, > + &mipi_isp_div, > + &mipi_isp, > + &ts_div, > + &ts, > + &mali_0_sel, > + &mali_0_div, > + &mali_0, > + &mali_1_sel, > + &mali_1_div, > + &mali_1, > + &mali, > + ð_rmii_sel, > + ð_rmii_div, > + ð_rmii, > + ð_125m, > + &sd_emmc_c_sel, > + &sd_emmc_c_div, > + &sd_emmc_c, > + &sd_emmc_a_sel, > + &sd_emmc_a_div, > + &sd_emmc_a, > + &sd_emmc_b_sel, > + &sd_emmc_b_div, > + &sd_emmc_b, > + &spicc0_sel, > + &spicc0_div, > + &spicc0, > + &spicc1_sel, > + &spicc1_div, > + &spicc1, > + &spicc2_sel, > + &spicc2_div, > + &spicc2, > + &spicc3_sel, > + &spicc3_div, > + &spicc3, > + &spicc4_sel, > + &spicc4_div, > + &spicc4, > + &spicc5_sel, > + &spicc5_div, > + &spicc5, > + &saradc_sel, > + &saradc_div, > + &saradc, > + &pwm_a_sel, > + &pwm_a_div, > + &pwm_a, > + &pwm_b_sel, > + &pwm_b_div, > + &pwm_b, > + &pwm_c_sel, > + &pwm_c_div, > + &pwm_c, > + &pwm_d_sel, > + &pwm_d_div, > + &pwm_d, > + &pwm_e_sel, > + &pwm_e_div, > + &pwm_e, > + &pwm_f_sel, > + &pwm_f_div, > + &pwm_f, > + &pwm_ao_a_sel, > + &pwm_ao_a_div, > + &pwm_ao_a, > + &pwm_ao_b_sel, > + &pwm_ao_b_div, > + &pwm_ao_b, > + &pwm_ao_c_sel, > + &pwm_ao_c_div, > + &pwm_ao_c, > + &pwm_ao_d_sel, > + &pwm_ao_d_div, > + &pwm_ao_d, > + &pwm_ao_e_sel, > + &pwm_ao_e_div, > + &pwm_ao_e, > + &pwm_ao_f_sel, > + &pwm_ao_f_div, > + &pwm_ao_f, > + &pwm_ao_g_sel, > + &pwm_ao_g_div, > + &pwm_ao_g, > + &pwm_ao_h_sel, > + &pwm_ao_h_div, > + &pwm_ao_h, > + &pwm_ao_h, > + &sys_ddr, > + &sys_dos, > + &sys_mipi_dsi_a, > + &sys_mipi_dsi_b, > + &sys_ethphy, > + &sys_mali, > + &sys_aocpu, > + &sys_aucpu, > + &sys_cec, > + &sys_gdc, > + &sys_deswarp, > + &sys_ampipe_nand, > + &sys_ampipe_eth, > + &sys_am2axi0, > + &sys_am2axi1, > + &sys_am2axi2, > + &sys_sdemmca, > + &sys_sdemmcb, > + &sys_sdemmcc, > + &sys_smartcard, > + &sys_acodec, > + &sys_spifc, > + &sys_msr_clk, > + &sys_ir_ctrl, > + &sys_audio, > + &sys_eth, > + &sys_uart_a, > + &sys_uart_b, > + &sys_uart_c, > + &sys_uart_d, > + &sys_uart_e, > + &sys_uart_f, > + &sys_aififo, > + &sys_spicc2, > + &sys_spicc3, > + &sys_spicc4, > + &sys_ts_a73, > + &sys_ts_a53, > + &sys_spicc5, > + &sys_g2d, > + &sys_spicc0, > + &sys_spicc1, > + &sys_pcie, > + &sys_usb, > + &sys_pcie_phy, > + &sys_i2c_ao_a, > + &sys_i2c_ao_b, > + &sys_i2c_m_a, > + &sys_i2c_m_b, > + &sys_i2c_m_c, > + &sys_i2c_m_d, > + &sys_i2c_m_e, > + &sys_i2c_m_f, > + &sys_hdmitx_apb, > + &sys_i2c_s_a, > + &sys_hdmirx_pclk, > + &sys_mmc_apb, > + &sys_mipi_isp_pclk, > + &sys_rsa, > + &sys_pclk_sys_apb, > + &sys_a73pclk_apb, > + &sys_dspa, > + &sys_dspb, > + &sys_vpu_intr, > + &sys_sar_adc, > + &sys_gic, > + &sys_ts_gpu, > + &sys_ts_nna, > + &sys_ts_vpu, > + &sys_ts_hevc, > + &sys_pwm_ab, > + &sys_pwm_cd, > + &sys_pwm_ef, > + &sys_pwm_ao_ab, > + &sys_pwm_ao_cd, > + &sys_pwm_ao_ef, > + &sys_pwm_ao_gh, > +}; > + > +static const struct regmap_config t7_periphs_regmap_cfg = { > + .reg_bits = 32, > + .val_bits = 32, > + .reg_stride = 4, > + .max_register = CLKCTRL_SPICC_CLK_CTRL2 > +}; > + > +static struct meson_clk_hw_data t7_periphs_clks = { > + .hws = t7_periphs_hw_clks, > + .num = ARRAY_SIZE(t7_periphs_hw_clks), > +}; > + > +static int amlogic_t7_periphs_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + void __iomem *base; > + struct regmap *map; > + int i, ret; > + > + base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(base)) > + return PTR_ERR(base); > + > + map = devm_regmap_init_mmio(dev, base, &t7_periphs_regmap_cfg); > + if (IS_ERR(map)) > + return PTR_ERR(map); > + > + /* Populate regmap for the regmap backed clocks */ > + for (i = 0; i < ARRAY_SIZE(t7_periphs_regmaps); i++) > + t7_periphs_regmaps[i]->map = map; > + > + for (i = 0; i < t7_periphs_clks.num; i++) { > + ret = devm_clk_hw_register(dev, t7_periphs_clks.hws[i]); > + if (ret) > + return ret; > + } > + > + return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &t7_periphs_clks); > +} > + > +static const struct of_device_id t7_periphs_clkc_match_table[] = { > + { .compatible = "amlogic,t7-peripherals-clkc", }, > + {} > +}; > +MODULE_DEVICE_TABLE(of, t7_periphs_clkc_match_table); > + > +static struct platform_driver t7_periphs_clkc_driver = { > + .probe = amlogic_t7_periphs_probe, > + .driver = { > + .name = "t7-peripherals-clkc", > + .of_match_table = t7_periphs_clkc_match_table, > + }, > +}; > + > +MODULE_DESCRIPTION("Amlogic T7 Peripherals Clock Controller driver"); > +module_platform_driver(t7_periphs_clkc_driver); > +MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>"); > +MODULE_LICENSE("GPL"); > +MODULE_IMPORT_NS(CLK_MESON); -- Jerome ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 5/5] clk: meson: t7: add t7 clock peripherals controller driver 2025-01-13 18:18 ` Jerome Brunet @ 2025-01-17 10:36 ` Jian Hu 0 siblings, 0 replies; 14+ messages in thread From: Jian Hu @ 2025-01-17 10:36 UTC (permalink / raw) To: Jerome Brunet Cc: Xianwei Zhao, Chuan Liu, Neil Armstrong, Kevin Hilman, Stephen Boyd, Michael Turquette, Dmitry Rokosov, robh+dt, Rob Herring, devicetree, linux-clk, linux-amlogic, linux-kernel, linux-arm-kernel On 2025/1/14 2:18, Jerome Brunet wrote: > [ EXTERNAL EMAIL ] > > On Wed 08 Jan 2025 at 17:40, Jian Hu <jian.hu@amlogic.com> wrote: > >> Add Peripheral clock controller driver for the Amlogic T7 SoC family. >> >> Signed-off-by: Jian Hu <jian.hu@amlogic.com> >> --- >> drivers/clk/meson/Kconfig | 13 + >> drivers/clk/meson/Makefile | 1 + >> drivers/clk/meson/t7-peripherals.c | 2323 ++++++++++++++++++++++++++++ >> 3 files changed, 2337 insertions(+) >> create mode 100644 drivers/clk/meson/t7-peripherals.c >> >> ...... >> + >> +#define SPI_PWM_CLK_MUX(_name, _reg, _mask, _shift, _parent_data) { \ > The same macros keeps getting defined again and again. > This has been going on for too long now. > > I'm addressing the problem it will take a bit of time and I guess it > will delay t7 and a5 a bit. Great, a common macro can be applied to c3/t7/a5. Wait for your good news. >> + .data = &(struct clk_regmap_mux_data) { \ >> + .offset = _reg, \ >> + .mask = _mask, \ >> + .shift = _shift, \ >> + }, \ >> + .hw.init = &(struct clk_init_data) { \ >> + .name = #_name "_sel", \ >> + .ops = &clk_regmap_mux_ops, \ >> + .parent_data = _parent_data, \ >> + .num_parents = ARRAY_SIZE(_parent_data), \ >> + }, \ >> +} >> + >> +#define SPI_PWM_CLK_DIV(_name, _reg, _shift, _width, _parent) { \ >> + .data = &(struct clk_regmap_div_data) { \ >> + .offset = _reg, \ >> + .shift = _shift, \ >> + .width = _width, \ >> + }, \ >> + .hw.init = &(struct clk_init_data) { \ >> + .name = #_name "_div", \ >> + .ops = &clk_regmap_divider_ops, \ >> + .parent_hws = (const struct clk_hw *[]) { \ >> + &_parent.hw \ >> + }, \ >> + .num_parents = 1, \ >> + .flags = CLK_SET_RATE_PARENT, \ >> + }, \ >> +} >> + >> +#define SPI_PWM_CLK_GATE(_name, _reg, _bit, _parent) { \ >> + .data = &(struct clk_regmap_gate_data) { \ >> + .offset = _reg, \ >> + .bit_idx = _bit, \ >> + }, \ >> + .hw.init = &(struct clk_init_data) { \ >> + .name = #_name, \ >> + .ops = &clk_regmap_gate_ops, \ >> + .parent_hws = (const struct clk_hw *[]) { \ >> + &_parent.hw \ >> + }, \ >> + .num_parents = 1, \ >> + .flags = CLK_SET_RATE_PARENT, \ >> + }, \ >> +} >> + >> +static const struct clk_parent_data spicc_parents[] = { >> + { .fw_name = "xtal", }, >> + { .fw_name = "sys", }, >> + { .fw_name = "fdiv4", }, >> + { .fw_name = "fdiv3", }, >> + { .fw_name = "fdiv2", }, >> + { .fw_name = "fdiv5", }, >> + { .fw_name = "fdiv7", }, >> + { .fw_name = "gp1", }, >> +}; >> + >> +static struct clk_regmap spicc0_sel = >> + SPI_PWM_CLK_MUX(spicc0, CLKCTRL_SPICC_CLK_CTRL, 0x7, 7, spicc_parents); >> +static struct clk_regmap spicc0_div = SPI_PWM_CLK_DIV(spicc0, CLKCTRL_SPICC_CLK_CTRL, 0, 6, spicc0_sel); >> +static struct clk_regmap spicc0 = SPI_PWM_CLK_GATE(spicc0, CLKCTRL_SPICC_CLK_CTRL, 6, spicc0_div); >> + >> ...... >> + >> +#define T7_CLK_GATE(_name, _reg, _bit, _fw_name, _flags) \ > See, redefining the peripheral once again ... something all the SoCs > uses with minor variation. A common macro is better for it. there is common macro in clk/meson/clk-regmap.h, but CLK_IGNORE_UNUSED flag is added. it can not be used here. maybe we can rework the macro or new one for it. >> +struct clk_regmap _name = { \ >> + .data = &(struct clk_regmap_gate_data){ \ >> + .offset = (_reg), \ >> + .bit_idx = (_bit), \ >> + }, \ >> + .hw.init = &(struct clk_init_data) { \ >> + .name = #_name, \ > There is an exception in the naming convention for peripheral clocks. > > The name is soc id prefixed in most SoC. It is these pointless minor > diff that makes factorisation difficult. Yes. I think a common MESON_GATE or AMLOGIC_GATE is okay for it. And how about this change for it? it remove the old defination and add new one 'MESON_GATE' in clk-regmap.h : --- a/drivers/clk/meson/clk-regmap.h +++ b/drivers/clk/meson/clk-regmap.h @@ -114,7 +114,7 @@ clk_get_regmap_mux_data(struct clk_regmap *clk) extern const struct clk_ops clk_regmap_mux_ops; extern const struct clk_ops clk_regmap_mux_ro_ops; -#define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ +#define __MESON_PCLK(_name, _reg, _bit, _ops, _pname, _flag) \ struct clk_regmap _name = { \ .data = &(struct clk_regmap_gate_data){ \ .offset = (_reg), \ @@ -125,13 +125,19 @@ struct clk_regmap _name = { \ .ops = _ops, \ .parent_hws = (const struct clk_hw *[]) { _pname }, \ .num_parents = 1, \ - .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ + .flags = (CLK_SET_RATE_PARENT | flag), \ }, \ } #define MESON_PCLK(_name, _reg, _bit, _pname) \ - __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname) + __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname, CLK_IGNORE_UNUSED) #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ - __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname) + __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname, CLK_IGNORE_UNUSED) + +#define MESON_GATE(_name, _reg, _bit, _pname, _flag) \ + __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname, _flag) + +#define MESON_GATE_RO(_name, _reg, _bit, _pname, _flag) \ + __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname, _flag) #endif /* __CLK_REGMAP_H */ diff --git a/drivers/clk/meson/t7-peripherals.c b/drivers/clk/meson/t7-peripherals.c index 362000fe4a7f..3a1aec703618 100644 --- a/drivers/clk/meson/t7-peripherals.c +++ b/drivers/clk/meson/t7-peripherals.c @@ -1750,25 +1750,10 @@ static struct clk_regmap t7_pwm_ao_h_div = static struct clk_regmap t7_pwm_ao_h = SPI_PWM_CLK_GATE(t7_pwm_ao_h, CLKCTRL_PWM_CLK_AO_GH_CTRL, 24, t7_pwm_ao_h_div); -#define T7_CLK_GATE(_name, _reg, _bit, _fw_name, _flags) \ -struct clk_regmap _name = { \ - .data = &(struct clk_regmap_gate_data){ \ - .offset = (_reg), \ - .bit_idx = (_bit), \ - }, \ - .hw.init = &(struct clk_init_data) { \ - .name = #_name, \ - .ops = &clk_regmap_gate_ops, \ - .parent_data = &(const struct clk_parent_data) { \ - .fw_name = #_fw_name, \ - }, \ - .num_parents = 1, \ - .flags = (_flags), \ - }, \ -} +#define T7_SYS_GATE(_name, _reg, _bit, _flag) \ + MESON_GATE(_name, _reg, _bit, &sys.hw, _flag) -#define T7_SYS_GATE(_name, _reg, _bit, _flags) \ - T7_CLK_GATE(_name, _reg, _bit, sys, _flags) +static T7_SYS_GATE(t7_sys_ddr, CLKCTRL_SYS_CLK_EN0_REG0, 0, 0); or another patch based above. T7_SYS_GATE macro is not necessary, and '&sys.hw' is needed for each sys clock. and we can define the clocks like: -#define T7_SYS_GATE(_name, _reg, _bit, _flag) \ - MESON_GATE(_name, _reg, _bit, &sys.hw, _flag) +static MESON_GATE(t7_sys_ddr, CLKCTRL_SYS_CLK_EN0_REG0, 0, &sys.hw, 0); +static MESON_GATE(t7_sys_dos, CLKCTRL_SYS_CLK_EN0_REG0, 0, &sys.hw, 1); Please help to review it, >> + .ops = &clk_regmap_gate_ops, \ >> + .parent_data = &(const struct clk_parent_data) { \ >> + .fw_name = #_fw_name, \ >> + }, \ >> + .num_parents = 1, \ >> + .flags = (_flags), \ >> + }, \ >> +} >> + >> +#define T7_SYS_GATE(_name, _reg, _bit, _flags) \ >> + T7_CLK_GATE(_name, _reg, _bit, sys, _flags) >> + >> +static T7_SYS_GATE(sys_ddr, CLKCTRL_SYS_CLK_EN0_REG0, 0, 0); >> >> ...... > -- > Jerome ^ permalink raw reply related [flat|nested] 14+ messages in thread
end of thread, other threads:[~2025-01-17 10:39 UTC | newest] Thread overview: 14+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-01-08 9:40 [PATCH v2 0/5] add support for T7 family clock controller Jian Hu 2025-01-08 9:40 ` [PATCH v2 1/5] dt-bindings: clock: add Amlogic T7 PLL " Jian Hu 2025-01-10 15:54 ` Rob Herring 2025-01-13 17:50 ` Jerome Brunet 2025-01-17 8:04 ` Jian Hu 2025-01-17 8:01 ` Jian Hu 2025-01-08 9:40 ` [PATCH v2 2/5] dt-bindings: clock: add Amlogic T7 SCMI " Jian Hu 2025-01-08 9:40 ` [PATCH v2 3/5] dt-bindings: clock: add Amlogic T7 peripherals " Jian Hu 2025-01-08 9:40 ` [PATCH v2 4/5] clk: meson: t7: add support for the T7 SoC PLL clock Jian Hu 2025-01-13 18:05 ` Jerome Brunet 2025-01-17 8:14 ` Jian Hu 2025-01-08 9:40 ` [PATCH v2 5/5] clk: meson: t7: add t7 clock peripherals controller driver Jian Hu 2025-01-13 18:18 ` Jerome Brunet 2025-01-17 10:36 ` Jian Hu
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