From: Fabio Estevam <festevam@gmail.com>
To: shawnguo@kernel.org
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
kernel@pengutronix.de, devicetree@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
Fabio Estevam <festevam@denx.de>
Subject: [PATCH v2 2/2] dt-bindings: clock: imx5: Fix the CCM interrupts description
Date: Sun, 12 Jan 2025 12:27:45 -0300 [thread overview]
Message-ID: <20250112152745.1079880-2-festevam@gmail.com> (raw)
In-Reply-To: <20250112152745.1079880-1-festevam@gmail.com>
From: Fabio Estevam <festevam@denx.de>
On the i.MX5 chips the peripheral interrupts are represented directly only
by their interrupt numbers.
Make the CCM nodes to follow this format.
Signed-off-by: Fabio Estevam <festevam@denx.de>
---
Changes since v1:
- Use interrupts = <71>, <72>;
Documentation/devicetree/bindings/clock/imx5-clock.yaml | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.yaml b/Documentation/devicetree/bindings/clock/imx5-clock.yaml
index 423c0142c1d3..ad03c0a13e64 100644
--- a/Documentation/devicetree/bindings/clock/imx5-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.yaml
@@ -46,13 +46,11 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx5-clock.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
clock-controller@53fd4000{
compatible = "fsl,imx53-ccm";
reg = <0x53fd4000 0x4000>;
- interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>,
- <0 72 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <71>, <72>;
#clock-cells = <1>;
};
...
--
2.34.1
next prev parent reply other threads:[~2025-01-12 15:31 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-12 15:27 [PATCH v2 1/2] ARM: dts: imx5: Fix the CCM interrupts description Fabio Estevam
2025-01-12 15:27 ` Fabio Estevam [this message]
2025-01-13 9:16 ` [PATCH v2 2/2] dt-bindings: clock: " Krzysztof Kozlowski
2025-01-13 15:26 ` [PATCH v2 1/2] ARM: dts: " Rob Herring (Arm)
2025-02-18 10:02 ` Shawn Guo
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