Re: [PATCH v2 1/5] dt-bindings: PCI: Add STM32MP25 PCIe root complex bindings

Christian Bruel
2024-12-03T18:14:06Z

On 12/3/24 14:34, Manivannan Sadhasivam wrote:
> On Tue, Nov 26, 2024 at 04:51:15PM +0100, Christian Bruel wrote:
>> Document the bindings for STM32MP25 PCIe Controller configured in
>> root complex mode.
>>
>> Supports 4 legacy interrupts and MSI interrupts from the ARM
>> GICv2m controller.
>>
>> STM32 PCIe may be in a power domain which is the case for the STM32MP25
>> based boards.
>>
>> Supports wake# from wake-gpios
>>
>> Signed-off-by: Christian Bruel <christian.bruel@foss.st.com>
>> ---
>> .../bindings/pci/st,stm32-pcie-common.yaml | 45 +++++++++
>> .../bindings/pci/st,stm32-pcie-host.yaml | 99 +++++++++++++++++++
>> 2 files changed, 144 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml
>> create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml b/Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml
>> new file mode 100644
>> index 000000000000..479c03134da3
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml
>> @@ -0,0 +1,45 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pci/st,stm32-pcie-common.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: STM32MP25 PCIe RC/EP controller
>> +
>> +maintainers:
>> + - Christian Bruel <christian.bruel@foss.st.com>
>> +
>> +description:
>> + STM32MP25 PCIe RC/EP common properties
>> +
>> +properties:
>> + clocks:
>> + maxItems: 1
>> + description: PCIe system clock
>> +
>> + resets:
>> + maxItems: 1
>> +
>> + phys:
>> + maxItems: 1
>> +
>> + phy-names:
>> + const: pcie-phy
>> +
>> + power-domains:
>> + maxItems: 1
>> +
>> + access-controllers:
>> + maxItems: 1
>> +
>> + reset-gpios:
>> + description: GPIO controlled connection to PERST# signal
>> + maxItems: 1
>> +
>> +required:
>> + - clocks
>> + - resets
>> + - phys
>> + - phy-names
>> +
>> +additionalProperties: true
>> diff --git a/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml b/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml
>> new file mode 100644
>> index 000000000000..18083cc69024
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml
>> @@ -0,0 +1,99 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pci/st,stm32-pcie-host.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: STM32MP25 PCIe root complex driver
>> +
>> +maintainers:
>> + - Christian Bruel <christian.bruel@foss.st.com>
>> +
>> +description:
>> + PCIe root complex controller based on the Synopsys DesignWare PCIe core.
>> +
>> +allOf:
>> + - $ref: /schemas/pci/snps,dw-pcie.yaml#
>> + - $ref: /schemas/pci/st,stm32-pcie-common.yaml#
>> +
>> +select:
>> + properties:
>> + compatible:
>> + const: st,stm32mp25-pcie-rc
>> + required:
>> + - compatible
>> +
>> +properties:
>> + compatible:
>> + const: st,stm32mp25-pcie-rc
>> +
>> + reg:
>> + items:
>> + - description: Data Bus Interface (DBI) registers.
>> + - description: PCIe configuration registers.
>> +
>> + reg-names:
>> + items:
>> + - const: dbi
>> + - const: config
>> +
>> + num-lanes:
>> + const: 1
>> +
>> + msi-parent:
>> + maxItems: 1
>> +
>> + wake-gpios:
>> + description: GPIO controlled connection to WAKE# input signal
>> + maxItems: 1
>> +
>> + wakeup-source: true
>> +
>> +dependentRequired:
>> + wakeup-source: [ wake-gpios ]
>> +
>> +required:
>> + - interrupt-map
>> + - interrupt-map-mask
>> + - ranges
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/st,stm32mp25-rcc.h>
>> + #include <dt-bindings/gpio/gpio.h>
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> + #include <dt-bindings/phy/phy.h>
>> + #include <dt-bindings/reset/st,stm32mp25-rcc.h>
>> +
>> + pcie@48400000 {
>> + compatible = "st,stm32mp25-pcie-rc";
>> + device_type = "pci";
>> + num-lanes = <1>;
>> + reg = <0x48400000 0x400000>,
>> + <0x10000000 0x10000>;
>> + reg-names = "dbi", "config";
>> + #interrupt-cells = <1>;
>> + interrupt-map-mask = <0 0 0 7>;
>> + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
>> + <0 0 0 2 &intc 0 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
>> + <0 0 0 3 &intc 0 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
>> + <0 0 0 4 &intc 0 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + ranges = <0x01000000 0 0x10010000 0x10010000 0 0x10000>,
>
> PCI address of I/O region should start from address 0x00000000.
>
ok, thanks !

> Also use hex notation for all values.
>
> - Mani
>