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[209.17.68.221]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21a9f21e279sm81344075ad.134.2025.01.15.03.43.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jan 2025 03:43:01 -0800 (PST) Date: Wed, 15 Jan 2025 20:42:59 +0900 From: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= To: Frank Li Cc: Rob Herring , Saravana Kannan , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , Bjorn Helgaas , Richard Zhu , Lucas Stach , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, Conor Dooley Subject: Re: [PATCH v8 0/7] PCI: dwc: opitimaze RC Host/EP pci_fixup_addr() Message-ID: <20250115114259.GP4176564@rocinante> References: <20241119-pci_fixup_addr-v8-0-c4bfa5193288@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20241119-pci_fixup_addr-v8-0-c4bfa5193288@nxp.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250115_034302_686923_A3532E8D X-CRM114-Status: GOOD ( 18.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello, > == RC side: > > ┌─────────┐ ┌────────────┐ > ┌─────┐ │ │ IA: 0x8ff8_0000 │ │ > │ CPU ├───►│ ┌────►├─────────────────┐ │ PCI │ > └─────┘ │ │ │ IA: 0x8ff0_0000 │ │ │ > CPU Addr │ │ ┌─►├─────────────┐ │ │ Controller │ > 0x7ff8_0000─┼───┘ │ │ │ │ │ │ > │ │ │ │ │ │ │ PCI Addr > 0x7ff0_0000─┼──────┘ │ │ └──► IOSpace ─┼────────────► > │ │ │ │ │ 0 > 0x7000_0000─┼────────►├─────────┐ │ │ │ > └─────────┘ │ └──────► CfgSpace ─┼────────────► > BUS Fabric │ │ │ 0 > │ │ │ > └──────────► MemSpace ─┼────────────► > IA: 0x8000_0000 │ │ 0x8000_0000 > └────────────┘ > > Current dwc implimemnt, pci_fixup_addr() call back is needed when bus > fabric convert cpu address before send to PCIe controller. > > bus@5f000000 { > compatible = "simple-bus"; > #address-cells = <1>; > #size-cells = <1>; > ranges = <0x80000000 0x0 0x70000000 0x10000000>; > > pcie@5f010000 { > compatible = "fsl,imx8q-pcie"; > reg = <0x5f010000 0x10000>, <0x8ff00000 0x80000>; > reg-names = "dbi", "config"; > #address-cells = <3>; > #size-cells = <2>; > device_type = "pci"; > bus-range = <0x00 0xff>; > ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>, > <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>; > ... > }; > }; > > Device tree already can descript all address translate. Some hardware > driver implement fixup function by mask some bits of cpu address. Last > pci-imx6.c are little bit better by fetch memory resource's offset to do > fixup. > > static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr) > { > ... > entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); > return cpu_addr - entry->offset; > } > > But it is not good by using IORESOURCE_MEM to fix up io/cfg address map > although address translate is the same as IORESOURCE_MEM. > > This patches to fetch untranslate range information for PCIe controller > (pcie@5f010000: ranges). So current config ATU without cpu_fixup_addr(). > > == EP side: > > Endpoint > ┌───────────────────────────────────────────────┐ > │ pcie-ep@5f010000 │ > │ ┌────────────────┐│ > │ │ Endpoint ││ > │ │ PCIe ││ > │ │ Controller ││ > │ bus@5f000000 │ ││ > │ ┌──────────┐ │ ││ > │ │ │ Outbound Transfer ││ > │┌─────┐ │ Bus ┼─────►│ ATU ──────────┬┬─────► > ││ │ │ Fabric │Bus │ ││PCI Addr > ││ CPU ├───►│ │Addr │ ││0xA000_0000 > ││ │CPU │ │0x8000_0000 ││ > │└─────┘Addr└──────────┘ │ ││ > │ 0x7000_0000 └────────────────┘│ > └───────────────────────────────────────────────┘ > > bus@5f000000 { > compatible = "simple-bus"; > ranges = <0x80000000 0x0 0x70000000 0x10000000>; > > pcie-ep@5f010000 { > reg = <0x5f010000 0x00010000>, > <0x80000000 0x10000000>; > reg-names = "dbi", "addr_space"; > ... ^^^^ > }; > ... > }; > > Add `bus_addr_base` to configure the outbound window address for CPU write. > The BUS fabric generally passes the same address to the PCIe EP controller, > but some BUS fabrics convert the address before sending it to the PCIe EP > controller. > > Above diagram, CPU write data to outbound windows address 0x7000_0000, > Bus fabric convert it to 0x8000_0000. ATU should use BUS address > 0x8000_0000 as input address and convert to PCI address 0xA000_0000. > > Previously, `cpu_addr_fixup()` was used to handle address conversion. Now, > the device tree provides this information. > > The both pave the road to eliminate ugle cpu_fixup_addr() callback function. Applied to controller/dwc for v6.14, thank you! Krzysztof