From: Sean Anderson <sean.anderson@linux.dev>
To: Mark Brown <broonie@kernel.org>,
Michal Simek <michal.simek@amd.com>,
linux-spi@vger.kernel.org
Cc: Jinjie Ruan <ruanjinjie@huawei.com>,
linux-arm-kernel@lists.infradead.org,
Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>,
linux-kernel@vger.kernel.org,
Miquel Raynal <miquel.raynal@bootlin.com>,
Sean Anderson <sean.anderson@linux.dev>
Subject: [PATCH 4/7] spi: zynqmp-gqspi: Refactor out controller initialization
Date: Thu, 16 Jan 2025 18:21:14 -0500 [thread overview]
Message-ID: <20250116232118.2694169-5-sean.anderson@linux.dev> (raw)
In-Reply-To: <20250116232118.2694169-1-sean.anderson@linux.dev>
In preparation for having multiple SPI busses, refactor out the
controller initialization into a separate function. No functional change
intended.
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
---
drivers/spi/spi-zynqmp-gqspi.c | 42 +++++++++++++++++++++-------------
1 file changed, 26 insertions(+), 16 deletions(-)
diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c
index a1233897dc88..d78e114e17e0 100644
--- a/drivers/spi/spi-zynqmp-gqspi.c
+++ b/drivers/spi/spi-zynqmp-gqspi.c
@@ -1253,6 +1253,29 @@ static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = {
.exec_op = zynqmp_qspi_exec_op,
};
+static int zynqmp_qspi_register_ctlr(struct zynqmp_qspi *xqspi,
+ struct spi_controller *ctlr)
+{
+ int ret;
+
+ if (!ctlr)
+ return 0;
+
+ ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
+ SPI_TX_DUAL | SPI_TX_QUAD;
+ ctlr->max_speed_hz = xqspi->speed_hz;
+ ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
+ ctlr->mem_ops = &zynqmp_qspi_mem_ops;
+ ctlr->setup = zynqmp_qspi_setup_op;
+ ctlr->auto_runtime_pm = true;
+
+ ret = devm_spi_register_controller(xqspi->dev, ctlr);
+ if (ret)
+ dev_err_probe(xqspi->dev, ret, "could not register %pOF\n",
+ ctlr->dev.of_node);
+ return ret;
+}
+
/**
* zynqmp_qspi_probe - Probe method for the QSPI driver
* @pdev: Pointer to the platform_device structure
@@ -1329,12 +1352,8 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
goto clk_dis_all;
}
- ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
- SPI_TX_DUAL | SPI_TX_QUAD;
- ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
- xqspi->speed_hz = ctlr->max_speed_hz;
-
/* QSPI controller initializations */
+ xqspi->speed_hz = clk_get_rate(xqspi->refclk) / 2;
ret = zynqmp_qspi_init_hw(xqspi);
if (ret)
goto clk_dis_all;
@@ -1368,18 +1387,9 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
ctlr->num_chipselect = num_cs;
}
- ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
- ctlr->mem_ops = &zynqmp_qspi_mem_ops;
- ctlr->setup = zynqmp_qspi_setup_op;
- ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
- ctlr->dev.of_node = np;
- ctlr->auto_runtime_pm = true;
-
- ret = devm_spi_register_controller(&pdev->dev, ctlr);
- if (ret) {
- dev_err(&pdev->dev, "spi_register_controller failed\n");
+ ret = zynqmp_qspi_register_ctlr(xqspi, ctlr);
+ if (ret)
goto clk_dis_all;
- }
pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_put_autosuspend(&pdev->dev);
--
2.35.1.1320.gc452695387.dirty
next prev parent reply other threads:[~2025-01-16 23:26 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-16 23:21 [PATCH 0/7] spi: zynqmp-gqspi: Split the bus and add GPIO support Sean Anderson
2025-01-16 23:21 ` [PATCH 1/7] dt-bindings: spi: zynqmp-qspi: Split the bus Sean Anderson
2025-01-22 0:16 ` David Lechner
2025-01-23 16:24 ` Sean Anderson
2025-01-23 21:59 ` David Lechner
2025-01-23 22:37 ` Sean Anderson
2025-01-24 13:35 ` Mark Brown
2025-06-12 23:44 ` Sean Anderson
2025-06-13 14:20 ` David Lechner
2025-06-13 15:57 ` Sean Anderson
2025-06-13 16:44 ` Sean Anderson
2025-06-13 16:53 ` David Lechner
2025-01-16 23:21 ` [PATCH 2/7] spi: zynqmp-gqspi: Pass speed/mode directly to config_op Sean Anderson
2025-01-16 23:21 ` [PATCH 3/7] spi: zynqmp-gqspi: Configure SPI mode dynamically Sean Anderson
2025-01-16 23:21 ` Sean Anderson [this message]
2025-01-16 23:21 ` [PATCH 5/7] spi: zynqmp-gqspi: Split the bus Sean Anderson
2025-01-21 13:19 ` Mahapatra, Amit Kumar
2025-01-21 15:53 ` Sean Anderson
2025-01-21 16:01 ` Mark Brown
2025-01-21 16:17 ` Sean Anderson
2025-01-16 23:21 ` [PATCH 6/7] spi: zynqmp-gqspi: Support GPIO chip selects Sean Anderson
2025-01-16 23:21 ` [PATCH 7/7] ARM64: xilinx: zynqmp: Convert to split QSPI bus Sean Anderson
2025-01-16 23:24 ` [PATCH 0/7] spi: zynqmp-gqspi: Split the bus and add GPIO support Sean Anderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250116232118.2694169-5-sean.anderson@linux.dev \
--to=sean.anderson@linux.dev \
--cc=amit.kumar-mahapatra@amd.com \
--cc=broonie@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-spi@vger.kernel.org \
--cc=michal.simek@amd.com \
--cc=miquel.raynal@bootlin.com \
--cc=ruanjinjie@huawei.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).