From: Conor Dooley <conor@kernel.org>
To: Atish Patra <atishp@rivosinc.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
weilin.wang@intel.com, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-perf-users@vger.kernel.org
Subject: Re: [PATCH v3 08/21] dt-bindings: riscv: add Counter delegation ISA extensions description
Date: Tue, 28 Jan 2025 18:13:30 +0000 [thread overview]
Message-ID: <20250128-crazed-crudeness-f7b1fbc87f1d@spud> (raw)
In-Reply-To: <20250127-counter_delegation-v3-8-64894d7e16d5@rivosinc.com>
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On Mon, Jan 27, 2025 at 08:59:49PM -0800, Atish Patra wrote:
> Add description for the Smcdeleg/Ssccfg extension.
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
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next prev parent reply other threads:[~2025-01-28 18:16 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-28 4:59 [PATCH v3 00/21] Add Counter delegation ISA extension support Atish Patra
2025-01-28 4:59 ` [PATCH v3 01/21] perf pmu-events: Add functions in jevent.py to parse counter and event info for hardware aware grouping Atish Patra
2025-01-28 4:59 ` [PATCH v3 02/21] RISC-V: Add Sxcsrind ISA extension CSR definitions Atish Patra
2025-01-28 4:59 ` [PATCH v3 03/21] RISC-V: Add Sxcsrind ISA extension definition and parsing Atish Patra
2025-01-28 4:59 ` [PATCH v3 04/21] dt-bindings: riscv: add Sxcsrind ISA extension description Atish Patra
2025-01-28 18:13 ` Conor Dooley
2025-01-28 4:59 ` [PATCH v3 05/21] RISC-V: Define indirect CSR access helpers Atish Patra
2025-01-28 4:59 ` [PATCH v3 06/21] RISC-V: Add Sscfg extension CSR definition Atish Patra
2025-01-28 4:59 ` [PATCH v3 07/21] RISC-V: Add Ssccfg ISA extension definition and parsing Atish Patra
2025-01-28 4:59 ` [PATCH v3 08/21] dt-bindings: riscv: add Counter delegation ISA extensions description Atish Patra
2025-01-28 18:13 ` Conor Dooley [this message]
2025-01-28 18:15 ` Conor Dooley
2025-01-28 4:59 ` [PATCH v3 09/21] RISC-V: Add Smcntrpmf extension parsing Atish Patra
2025-01-28 18:10 ` Conor Dooley
2025-02-04 6:35 ` Atish Kumar Patra
2025-01-28 4:59 ` [PATCH v3 10/21] dt-bindings: riscv: add Smcntrpmf ISA extension description Atish Patra
2025-01-28 18:16 ` Conor Dooley
2025-01-28 4:59 ` [PATCH v3 11/21] RISC-V: perf: Restructure the SBI PMU code Atish Patra
2025-01-28 4:59 ` [PATCH v3 12/21] RISC-V: perf: Modify the counter discovery mechanism Atish Patra
2025-01-28 4:59 ` [PATCH v3 13/21] RISC-V: perf: Add a mechanism to defined legacy event encoding Atish Patra
2025-01-28 4:59 ` [PATCH v3 14/21] RISC-V: perf: Implement supervisor counter delegation support Atish Patra
2025-01-28 4:59 ` [PATCH v3 15/21] RISC-V: perf: Skip PMU SBI extension when not implemented Atish Patra
2025-01-28 4:59 ` [PATCH v3 16/21] RISC-V: perf: Use config2/vendor table for event to counter mapping Atish Patra
2025-01-28 4:59 ` [PATCH v3 17/21] RISC-V: perf: Add legacy event encodings via sysfs Atish Patra
2025-01-28 4:59 ` [PATCH v3 18/21] RISC-V: perf: Add Qemu virt machine events Atish Patra
2025-01-28 5:00 ` [PATCH v3 19/21] tools/perf: Support event code for arch standard events Atish Patra
2025-01-28 5:00 ` [PATCH v3 20/21] tools/perf: Pass the Counter constraint values in the pmu events Atish Patra
2025-01-28 5:00 ` [PATCH v3 21/21] Sync empty-pmu-events.c with autogenerated one Atish Patra
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