From: Oliver Upton <oliver.upton@linux.dev>
To: kvmarm@lists.linux.dev
Cc: Marc Zyngier <maz@kernel.org>, Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>,
Mingwei Zhang <mizhang@google.com>,
Colton Lewis <coltonlewis@google.com>,
Raghavendra Rao Ananta <rananta@google.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Oliver Upton <oliver.upton@linux.dev>,
Janne Grunau <j@jannau.net>
Subject: [PATCH v2 02/14] drivers/perf: apple_m1: Support host/guest event filtering
Date: Mon, 3 Feb 2025 10:30:59 -0800 [thread overview]
Message-ID: <20250203183111.191519-3-oliver.upton@linux.dev> (raw)
In-Reply-To: <20250203183111.191519-1-oliver.upton@linux.dev>
The PMU appears to have a separate register for filtering 'guest'
exception levels (i.e. EL1 and !ELIsInHost(EL0)) which has the same
layout as PMCR1_EL1. Conveniently, there exists a VHE register alias
(PMCR1_EL12) that can be used to configure it.
Support guest events by programming the EL12 register with the intended
guest kernel/userspace filters. Limit support for guest events to VHE
(i.e. kernel running at EL2), as it avoids involving KVM to context
switch PMU registers. VHE is the only supported mode on M* parts anyway,
so this isn't an actual feature limitation.
Tested-by: Janne Grunau <j@jannau.net>
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
---
drivers/perf/apple_m1_cpu_pmu.c | 20 ++++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c
index cea80afd1253..d6d4ff6da862 100644
--- a/drivers/perf/apple_m1_cpu_pmu.c
+++ b/drivers/perf/apple_m1_cpu_pmu.c
@@ -120,6 +120,8 @@ enum m1_pmu_events {
*/
M1_PMU_CFG_COUNT_USER = BIT(8),
M1_PMU_CFG_COUNT_KERNEL = BIT(9),
+ M1_PMU_CFG_COUNT_HOST = BIT(10),
+ M1_PMU_CFG_COUNT_GUEST = BIT(11),
};
/*
@@ -328,7 +330,7 @@ static void m1_pmu_disable_counter_interrupt(unsigned int index)
}
static void __m1_pmu_configure_event_filter(unsigned int index, bool user,
- bool kernel)
+ bool kernel, bool host)
{
u64 clear, set, user_bit, kernel_bit;
@@ -356,7 +358,10 @@ static void __m1_pmu_configure_event_filter(unsigned int index, bool user,
else
clear |= kernel_bit;
- sysreg_clear_set_s(SYS_IMP_APL_PMCR1_EL1, clear, set);
+ if (host)
+ sysreg_clear_set_s(SYS_IMP_APL_PMCR1_EL1, clear, set);
+ else if (is_kernel_in_hyp_mode())
+ sysreg_clear_set_s(SYS_IMP_APL_PMCR1_EL12, clear, set);
}
static void __m1_pmu_configure_eventsel(unsigned int index, u8 event)
@@ -391,10 +396,13 @@ static void __m1_pmu_configure_eventsel(unsigned int index, u8 event)
static void m1_pmu_configure_counter(unsigned int index, unsigned long config_base)
{
bool kernel = config_base & M1_PMU_CFG_COUNT_KERNEL;
+ bool guest = config_base & M1_PMU_CFG_COUNT_GUEST;
+ bool host = config_base & M1_PMU_CFG_COUNT_HOST;
bool user = config_base & M1_PMU_CFG_COUNT_USER;
u8 evt = config_base & M1_PMU_CFG_EVENT;
- __m1_pmu_configure_event_filter(index, user, kernel);
+ __m1_pmu_configure_event_filter(index, user && host, kernel && host, true);
+ __m1_pmu_configure_event_filter(index, user && guest, kernel && guest, false);
__m1_pmu_configure_eventsel(index, evt);
}
@@ -570,7 +578,7 @@ static int m1_pmu_set_event_filter(struct hw_perf_event *event,
{
unsigned long config_base = 0;
- if (!attr->exclude_guest) {
+ if (!attr->exclude_guest && !is_kernel_in_hyp_mode()) {
pr_debug("ARM performance counters do not support mode exclusion\n");
return -EOPNOTSUPP;
}
@@ -578,6 +586,10 @@ static int m1_pmu_set_event_filter(struct hw_perf_event *event,
config_base |= M1_PMU_CFG_COUNT_KERNEL;
if (!attr->exclude_user)
config_base |= M1_PMU_CFG_COUNT_USER;
+ if (!attr->exclude_host)
+ config_base |= M1_PMU_CFG_COUNT_HOST;
+ if (!attr->exclude_guest)
+ config_base |= M1_PMU_CFG_COUNT_GUEST;
event->config_base = config_base;
--
2.39.5
next prev parent reply other threads:[~2025-02-03 18:39 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-03 18:30 [PATCH v2 00/14] KVM: arm64: Support FEAT_PMUv3 on Apple hardware Oliver Upton
2025-02-03 18:30 ` [PATCH v2 01/14] drivers/perf: apple_m1: Refactor event select/filter configuration Oliver Upton
2025-02-19 16:22 ` Marc Zyngier
2025-02-03 18:30 ` Oliver Upton [this message]
2025-02-03 18:31 ` [PATCH v2 03/14] drivers/perf: apple_m1: Provide helper for mapping PMUv3 events Oliver Upton
2025-02-19 16:37 ` Marc Zyngier
2025-02-03 18:31 ` [PATCH v2 04/14] KVM: arm64: Compute PMCEID from arm_pmu's event bitmaps Oliver Upton
2025-02-03 18:31 ` [PATCH v2 05/14] KVM: arm64: Always support SW_INCR PMU event Oliver Upton
2025-02-03 18:31 ` [PATCH v2 06/14] KVM: arm64: Remap PMUv3 events onto hardware Oliver Upton
2025-02-19 16:45 ` Marc Zyngier
2025-02-19 19:25 ` Oliver Upton
2025-02-03 18:31 ` [PATCH v2 07/14] KVM: arm64: Use a cpucap to determine if system supports FEAT_PMUv3 Oliver Upton
2025-02-19 17:44 ` Marc Zyngier
2025-02-19 19:22 ` Oliver Upton
2025-02-19 19:35 ` Marc Zyngier
2025-02-03 18:31 ` [PATCH v2 08/14] KVM: arm64: Drop kvm_arm_pmu_available static key Oliver Upton
2025-02-03 18:31 ` [PATCH v2 09/14] KVM: arm64: Use guard() to cleanup usage of arm_pmus_lock Oliver Upton
2025-02-03 18:31 ` [PATCH v2 10/14] KVM: arm64: Move PMUVer filtering into KVM code Oliver Upton
2025-02-19 18:17 ` Marc Zyngier
2025-02-03 18:31 ` [PATCH v2 11/14] KVM: arm64: Compute synthetic sysreg ESR for Apple PMUv3 traps Oliver Upton
2025-02-03 18:31 ` [PATCH v2 12/14] KVM: arm64: Advertise PMUv3 if IMPDEF traps are present Oliver Upton
2025-02-03 18:31 ` [PATCH v2 13/14] KVM: arm64: Provide 1 event counter on IMPDEF hardware Oliver Upton
2025-02-03 18:31 ` [PATCH v2 14/14] arm64: Enable IMP DEF PMUv3 traps on Apple M* Oliver Upton
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