From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
kvm@vger.kernel.org
Cc: Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Zenghui Yu <yuzenghui@huawei.com>,
Andre Przywara <andre.przywara@arm.com>,
Eric Auger <eric.auger@redhat.com>
Subject: [PATCH v3 14/16] KVM: arm64: nv: Fold GICv3 host trapping requirements into guest setup
Date: Thu, 6 Feb 2025 15:49:23 +0000 [thread overview]
Message-ID: <20250206154925.1109065-15-maz@kernel.org> (raw)
In-Reply-To: <20250206154925.1109065-1-maz@kernel.org>
Popular HW that is able to use NV also has a broken vgic implementation
that requires trapping.
On such HW, propagate the host trap bits into the guest's shadow
ICH_HCR_EL2 register, making sure we don't allow an L2 guest to bring
the system down.
This involves a bit of tweaking so that the emulation code correctly
poicks up the shadow state as needed, and to only partially sync
ICH_HCR_EL2 back with the guest state to capture EOIcount.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/kvm/vgic/vgic-v3-nested.c | 20 +++++++++++++++++---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/kvm/vgic/vgic-v3-nested.c b/arch/arm64/kvm/vgic/vgic-v3-nested.c
index 643bd8a8e0669..5350a4650b7a5 100644
--- a/arch/arm64/kvm/vgic/vgic-v3-nested.c
+++ b/arch/arm64/kvm/vgic/vgic-v3-nested.c
@@ -296,9 +296,19 @@ static void vgic_v3_create_shadow_state(struct kvm_vcpu *vcpu,
struct vgic_v3_cpu_if *s_cpu_if)
{
struct vgic_v3_cpu_if *host_if = &vcpu->arch.vgic_cpu.vgic_v3;
+ u64 val = 0;
int i;
- s_cpu_if->vgic_hcr = __vcpu_sys_reg(vcpu, ICH_HCR_EL2);
+ /*
+ * If we're on a system with a broken vgic that requires
+ * trapping, propagate the trapping requirements.
+ *
+ * Ah, the smell of rotten fruits...
+ */
+ if (static_branch_unlikely(&vgic_v3_cpuif_trap))
+ val = host_if->vgic_hcr & (ICH_HCR_EL2_TALL0 | ICH_HCR_EL2_TALL1 |
+ ICH_HCR_EL2_TC | ICH_HCR_EL2_TDIR);
+ s_cpu_if->vgic_hcr = __vcpu_sys_reg(vcpu, ICH_HCR_EL2) | val;
s_cpu_if->vgic_vmcr = __vcpu_sys_reg(vcpu, ICH_VMCR_EL2);
s_cpu_if->vgic_sre = host_if->vgic_sre;
@@ -335,6 +345,7 @@ void vgic_v3_put_nested(struct kvm_vcpu *vcpu)
{
struct shadow_if *shadow_if = get_shadow_if();
struct vgic_v3_cpu_if *s_cpu_if = &shadow_if->cpuif;
+ u64 val;
int i;
__vgic_v3_save_vmcr_aprs(s_cpu_if);
@@ -345,7 +356,10 @@ void vgic_v3_put_nested(struct kvm_vcpu *vcpu)
* Translate the shadow state HW fields back to the virtual ones
* before copying the shadow struct back to the nested one.
*/
- __vcpu_sys_reg(vcpu, ICH_HCR_EL2) = s_cpu_if->vgic_hcr;
+ val = __vcpu_sys_reg(vcpu, ICH_HCR_EL2);
+ val &= ~ICH_HCR_EL2_EOIcount_MASK;
+ val |= (s_cpu_if->vgic_hcr & ICH_HCR_EL2_EOIcount_MASK);
+ __vcpu_sys_reg(vcpu, ICH_HCR_EL2) = val;
__vcpu_sys_reg(vcpu, ICH_VMCR_EL2) = s_cpu_if->vgic_vmcr;
for (i = 0; i < 4; i++) {
@@ -354,7 +368,7 @@ void vgic_v3_put_nested(struct kvm_vcpu *vcpu)
}
for_each_set_bit(i, &shadow_if->lr_map, kvm_vgic_global_state.nr_lr) {
- u64 val = __vcpu_sys_reg(vcpu, ICH_LRN(i));
+ val = __vcpu_sys_reg(vcpu, ICH_LRN(i));
val &= ~ICH_LR_STATE;
val |= s_cpu_if->vgic_lr[i] & ICH_LR_STATE;
--
2.39.2
next prev parent reply other threads:[~2025-02-06 16:10 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-06 15:49 [PATCH v3 00/16] KVM: arm64: Add NV GICv3 support Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 01/16] arm64: sysreg: Add layout for ICH_HCR_EL2 Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 02/16] arm64: sysreg: Add layout for ICH_VTR_EL2 Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 03/16] arm64: sysreg: Add layout for ICH_MISR_EL2 Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 04/16] KVM: arm64: nv: Load timer before the GIC Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 05/16] KVM: arm64: nv: Add ICH_*_EL2 registers to vpcu_sysreg Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 06/16] KVM: arm64: nv: Plumb handling of GICv3 EL2 accesses Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 07/16] KVM: arm64: nv: Sanitise ICH_HCR_EL2 accesses Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 08/16] KVM: arm64: nv: Nested GICv3 emulation Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 09/16] KVM: arm64: nv: Handle L2->L1 transition on interrupt injection Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 10/16] KVM: arm64: nv: Add Maintenance Interrupt emulation Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 11/16] KVM: arm64: nv: Respect virtual HCR_EL2.TWx setting Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 12/16] KVM: arm64: nv: Request vPE doorbell upon nested ERET to L2 Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 13/16] KVM: arm64: nv: Propagate used_lrs between L1 and L0 contexts Marc Zyngier
2025-02-06 15:49 ` Marc Zyngier [this message]
2025-02-06 15:49 ` [PATCH v3 15/16] KVM: arm64: nv: Allow userland to set VGIC maintenance IRQ Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 16/16] KVM: arm64: nv: Fail KVM init if asking for NV without GICv3 Marc Zyngier
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250206154925.1109065-15-maz@kernel.org \
--to=maz@kernel.org \
--cc=andre.przywara@arm.com \
--cc=eric.auger@redhat.com \
--cc=joey.gouly@arm.com \
--cc=kvm@vger.kernel.org \
--cc=kvmarm@lists.linux.dev \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=oliver.upton@linux.dev \
--cc=suzuki.poulose@arm.com \
--cc=yuzenghui@huawei.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).