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From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
	kvm@vger.kernel.org
Cc: Joey Gouly <joey.gouly@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Oliver Upton <oliver.upton@linux.dev>,
	Zenghui Yu <yuzenghui@huawei.com>,
	Andre Przywara <andre.przywara@arm.com>,
	Eric Auger <eric.auger@redhat.com>
Subject: [PATCH v3 04/16] KVM: arm64: nv: Load timer before the GIC
Date: Thu,  6 Feb 2025 15:49:13 +0000	[thread overview]
Message-ID: <20250206154925.1109065-5-maz@kernel.org> (raw)
In-Reply-To: <20250206154925.1109065-1-maz@kernel.org>

In order for vgic_v3_load_nested to be able to observe which timer
interrupts have the HW bit set for the current context, the timers
must have been loaded in the new mode and the right timer mapped
to their corresponding HW IRQs.

At the moment, we load the GIC first, meaning that timer interrupts
injected to an L2 guest will never have the HW bit set (we see the
old configuration).

Swapping the two loads solves this particular problem.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/kvm/arm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index 646e806c6ca69..f3ffd8a6aebe2 100644
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -576,8 +576,8 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 nommu:
 	vcpu->cpu = cpu;
 
-	kvm_vgic_load(vcpu);
 	kvm_timer_vcpu_load(vcpu);
+	kvm_vgic_load(vcpu);
 	kvm_vcpu_load_debug(vcpu);
 	if (has_vhe())
 		kvm_vcpu_load_vhe(vcpu);
-- 
2.39.2



  parent reply	other threads:[~2025-02-06 15:54 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-06 15:49 [PATCH v3 00/16] KVM: arm64: Add NV GICv3 support Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 01/16] arm64: sysreg: Add layout for ICH_HCR_EL2 Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 02/16] arm64: sysreg: Add layout for ICH_VTR_EL2 Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 03/16] arm64: sysreg: Add layout for ICH_MISR_EL2 Marc Zyngier
2025-02-06 15:49 ` Marc Zyngier [this message]
2025-02-06 15:49 ` [PATCH v3 05/16] KVM: arm64: nv: Add ICH_*_EL2 registers to vpcu_sysreg Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 06/16] KVM: arm64: nv: Plumb handling of GICv3 EL2 accesses Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 07/16] KVM: arm64: nv: Sanitise ICH_HCR_EL2 accesses Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 08/16] KVM: arm64: nv: Nested GICv3 emulation Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 09/16] KVM: arm64: nv: Handle L2->L1 transition on interrupt injection Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 10/16] KVM: arm64: nv: Add Maintenance Interrupt emulation Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 11/16] KVM: arm64: nv: Respect virtual HCR_EL2.TWx setting Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 12/16] KVM: arm64: nv: Request vPE doorbell upon nested ERET to L2 Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 13/16] KVM: arm64: nv: Propagate used_lrs between L1 and L0 contexts Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 14/16] KVM: arm64: nv: Fold GICv3 host trapping requirements into guest setup Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 15/16] KVM: arm64: nv: Allow userland to set VGIC maintenance IRQ Marc Zyngier
2025-02-06 15:49 ` [PATCH v3 16/16] KVM: arm64: nv: Fail KVM init if asking for NV without GICv3 Marc Zyngier

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