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From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, kvm@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Cc: Joey Gouly <joey.gouly@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Oliver Upton <oliver.upton@linux.dev>,
	Zenghui Yu <yuzenghui@huawei.com>,
	Eric Auger <eric.auger@redhat.com>
Subject: [PATCH 04/14] KVM: arm64: nv: Snapshot S1 ASID tagging information during walk
Date: Sat, 15 Feb 2025 15:01:24 +0000	[thread overview]
Message-ID: <20250215150134.3765791-5-maz@kernel.org> (raw)
In-Reply-To: <20250215150134.3765791-1-maz@kernel.org>

We currently completely ignore any sort of ASID tagging during a S1
walk, as AT doesn't care about it.

However, such information is required if we are going to create
anything that looks like a TLB from this walk.

Let's capture it both the nG and ASID information while walking
the page tables.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/include/asm/kvm_nested.h |  2 ++
 arch/arm64/kvm/at.c                 | 27 +++++++++++++++++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/arch/arm64/include/asm/kvm_nested.h b/arch/arm64/include/asm/kvm_nested.h
index 43162f1dc4993..2bd315a59f283 100644
--- a/arch/arm64/include/asm/kvm_nested.h
+++ b/arch/arm64/include/asm/kvm_nested.h
@@ -273,6 +273,8 @@ struct s1_walk_result {
 			u64	pa;
 			s8	level;
 			u8	APTable;
+			bool	nG;
+			u16	asid;
 			bool	UXNTable;
 			bool	PXNTable;
 			bool	uwxn;
diff --git a/arch/arm64/kvm/at.c b/arch/arm64/kvm/at.c
index cded013587178..382847ce0c9b7 100644
--- a/arch/arm64/kvm/at.c
+++ b/arch/arm64/kvm/at.c
@@ -410,6 +410,33 @@ static int walk_s1(struct kvm_vcpu *vcpu, struct s1_walk_info *wi,
 	wr->pa = desc & GENMASK(47, va_bottom);
 	wr->pa |= va & GENMASK_ULL(va_bottom - 1, 0);
 
+	wr->nG = (wi->regime != TR_EL2) && (desc & PTE_NG);
+	if (wr->nG) {
+		u64 asid_ttbr, tcr;
+
+		switch (wi->regime) {
+		case TR_EL10:
+			tcr = vcpu_read_sys_reg(vcpu, TCR_EL1);
+			asid_ttbr = ((tcr & TCR_A1) ?
+				     vcpu_read_sys_reg(vcpu, TTBR1_EL1) :
+				     vcpu_read_sys_reg(vcpu, TTBR0_EL1));
+			break;
+		case TR_EL20:
+			tcr = vcpu_read_sys_reg(vcpu, TCR_EL2);
+			asid_ttbr = ((tcr & TCR_A1) ?
+				     vcpu_read_sys_reg(vcpu, TTBR1_EL2) :
+				     vcpu_read_sys_reg(vcpu, TTBR0_EL2));
+			break;
+		default:
+			BUG();
+		}
+
+		wr->asid = FIELD_GET(TTBR_ASID_MASK, asid_ttbr);
+		if (!kvm_has_feat_enum(vcpu->kvm, ID_AA64MMFR0_EL1, ASIDBITS, 16) ||
+		    !(tcr & TCR_ASID16))
+			wr->asid &= GENMASK(7, 0);
+	}
+
 	return 0;
 
 addrsz:
-- 
2.39.2



  parent reply	other threads:[~2025-02-15 15:09 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-15 15:01 [PATCH 00/14] KVM: arm64: Recursive NV support Marc Zyngier
2025-02-15 15:01 ` [PATCH 01/14] arm64: sysreg: Add layout for VNCR_EL2 Marc Zyngier
2025-02-15 15:01 ` [PATCH 02/14] KVM: arm64: nv: Allocate VNCR page when required Marc Zyngier
2025-02-15 15:01 ` [PATCH 03/14] KVM: arm64: nv: Extract translation helper from the AT code Marc Zyngier
2025-02-15 15:01 ` Marc Zyngier [this message]
2025-02-15 15:01 ` [PATCH 05/14] KVM: arm64: nv: Move TLBI range decoding to a helper Marc Zyngier
2025-02-15 15:01 ` [PATCH 06/14] KVM: arm64: nv: Don't adjust PSTATE.M when L2 is nesting Marc Zyngier
2025-02-15 15:01 ` [PATCH 07/14] KVM: arm64: nv: Add pseudo-TLB backing VNCR_EL2 Marc Zyngier
2025-02-15 15:01 ` [PATCH 08/14] KVM: arm64: nv: Add userspace and guest handling of VNCR_EL2 Marc Zyngier
2025-02-15 15:01 ` [PATCH 09/14] KVM: arm64: nv: Handle VNCR_EL2-triggered faults Marc Zyngier
2025-02-15 15:01 ` [PATCH 10/14] KVM: arm64: nv: Handle mapping of VNCR_EL2 at EL2 Marc Zyngier
2025-02-15 15:01 ` [PATCH 11/14] KVM: arm64: nv: Handle VNCR_EL2 invalidation from MMU notifiers Marc Zyngier
2025-02-15 15:01 ` [PATCH 12/14] KVM: arm64: nv: Program host's VNCR_EL2 to the fixmap address Marc Zyngier
2025-02-15 15:01 ` [PATCH 13/14] KVM: arm64: nv: Add S1 TLB invalidation primitive for VNCR_EL2 Marc Zyngier
2025-02-15 15:01 ` [PATCH 14/14] KVM: arm64: nv: Plumb TLBI S1E2 into system instruction dispatch Marc Zyngier

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