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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250202-en7581-pcie-pbus-csr-v2-2-65dcb201c9a9@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250219_102701_103707_91EA30EF X-CRM114-Status: GOOD ( 22.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sun, Feb 02, 2025 at 08:34:24PM +0100, Lorenzo Bianconi wrote: > Configure PBus base address and address mask to allow the hw > to detect if a given address is on PCIE0, PCIE1 or PCIE2. > > Signed-off-by: Lorenzo Bianconi Reviewed-by: Manivannan Sadhasivam - Mani > --- > drivers/pci/controller/pcie-mediatek-gen3.c | 30 ++++++++++++++++++++++++++++- > 1 file changed, 29 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c > index aa24ac9aaecc749b53cfc4faf6399913d20cdbf2..9c2a592cae959de8fbe9ca5c5c2253f8eadf2c76 100644 > --- a/drivers/pci/controller/pcie-mediatek-gen3.c > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c > @@ -15,6 +15,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -24,6 +25,7 @@ > #include > #include > #include > +#include > #include > > #include "../pci.h" > @@ -127,6 +129,13 @@ > > #define PCIE_MTK_RESET_TIME_US 10 > > +#define PCIE_EN7581_PBUS_ADDR(_n) (0x00 + ((_n) << 3)) > +#define PCIE_EN7581_PBUS_ADDR_MASK(_n) (0x04 + ((_n) << 3)) > +#define PCIE_EN7581_PBUS_BASE_ADDR(_n) \ > + ((_n) == 2 ? 0x28000000 : \ > + (_n) == 1 ? 0x24000000 : 0x20000000) > +#define PCIE_EN7581_PBUS_BASE_ADDR_MASK GENMASK(31, 26) > + > /* Time in ms needed to complete PCIe reset on EN7581 SoC */ > #define PCIE_EN7581_RESET_TIME_MS 100 > > @@ -931,7 +940,8 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) > static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) > { > struct device *dev = pcie->dev; > - int err; > + struct regmap *map; > + int err, slot; > u32 val; > > /* > @@ -945,6 +955,24 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) > /* Wait for the time needed to complete the reset lines assert. */ > msleep(PCIE_EN7581_RESET_TIME_MS); > > + map = syscon_regmap_lookup_by_phandle(dev->of_node, > + "mediatek,pbus-csr"); > + if (IS_ERR(map)) > + return PTR_ERR(map); > + > + /* > + * Configure PBus base address and address mask to allow the > + * hw to detect if a given address is on PCIE0, PCIE1 or PCIE2. > + */ > + slot = of_get_pci_domain_nr(dev->of_node); > + if (slot < 0) > + return slot; > + > + regmap_write(map, PCIE_EN7581_PBUS_ADDR(slot), > + PCIE_EN7581_PBUS_BASE_ADDR(slot)); > + regmap_write(map, PCIE_EN7581_PBUS_ADDR_MASK(slot), > + PCIE_EN7581_PBUS_BASE_ADDR_MASK); > + > /* > * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581 > * requires PHY initialization and power-on before PHY reset deassert. > > -- > 2.48.1 > -- மணிவண்ணன் சதாசிவம்