Re: [PATCH] arm: clk: Add ETH switch clock description for vf610 SoC

[Lukasz Majewski <lukma@denx.de>]

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Hi Andrew,

> On Wed, Feb 19, 2025 at 12:49:36PM +0100, Lukasz Majewski wrote:
> > The NXP's vf610 soc is equipped with L2 switch IP block from More
> > Than IP (MTIP) vendor.
> > 
> > It requires special clock (VF610_CLK_ESW) to be operational.  
> 
> So you have a driver for this switch? It has been talked about in the
> past, but nobody made any progress with it. Ah, it was you in 2020.

Yes, I'm going to try another time to upstream it.... :-)

> It
> will be interesting to see what you came up with in the end, pure
> switchdev or a DSA driver.

I think it would be:

1. Standalone driver, which would configure the L2 switch from the very
beginning to work (this is different from FEC on imx28/vf610 where
switch is bypassed)

2. It will use the in-switch registers to have two network interfaces
separated. As a result - it may be slower than the fec_main.c in this
use case.

3. When somebody call "bridge ..." on it - then the in-switch
separation would be disabled. This is the "normal" state of operation
for L2 switch, which would be a HW accelerator for bridging.

4. The switchdev would be used to manage it

5. This would be just a very simple driver - just bridging and startup
of the L2 switch.

After we would have a consensus (i.e. it would be pulled to mainline) -
I would proceed further.

I will try to not touch fec_main.c driver - just write standalone, new
for MoreThanIP L2 switch driver.

If somebody would like to use FEC, then he will insert the proper
module. If switch, another one can be inserted, depending o the target
use case.

> 
> 	Andrew


Best regards,

Lukasz Majewski

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