* [PATCH 1/9] arm64: dts: apple: s5l8960x: Add CPU caches
2025-02-20 12:21 [PATCH 0/9] arm64: dts: apple: Add CPU cache information for Apple A7-A11, T2 SoCs Nick Chan
@ 2025-02-20 12:21 ` Nick Chan
2025-02-20 12:21 ` [PATCH 2/9] arm64: dts: apple: t7000: " Nick Chan
` (8 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Nick Chan @ 2025-02-20 12:21 UTC (permalink / raw)
To: Sven Peter, Janne Grunau, Alyssa Rosenzweig, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: asahi, linux-arm-kernel, devicetree, linux-kernel, Nick Chan
Add information about CPU caches in Apple A7 SoC.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
arch/arm64/boot/dts/apple/s5l8960x.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/apple/s5l8960x.dtsi b/arch/arm64/boot/dts/apple/s5l8960x.dtsi
index 64dbae5c73515bb6a1651b9b26d349d0cfd0408a..e58a3a280abf72c0a390cbefb4fdf89942d77512 100644
--- a/arch/arm64/boot/dts/apple/s5l8960x.dtsi
+++ b/arch/arm64/boot/dts/apple/s5l8960x.dtsi
@@ -37,6 +37,9 @@ cpu0: cpu@0 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache>;
+ i-cache-size = <0x10000>;
+ d-cache-size = <0x10000>;
};
cpu1: cpu@1 {
@@ -47,6 +50,16 @@ cpu1: cpu@1 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache>;
+ i-cache-size = <0x10000>;
+ d-cache-size = <0x10000>;
+ };
+
+ l2_cache: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x100000>;
};
};
--
2.48.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 2/9] arm64: dts: apple: t7000: Add CPU caches
2025-02-20 12:21 [PATCH 0/9] arm64: dts: apple: Add CPU cache information for Apple A7-A11, T2 SoCs Nick Chan
2025-02-20 12:21 ` [PATCH 1/9] arm64: dts: apple: s5l8960x: Add CPU caches Nick Chan
@ 2025-02-20 12:21 ` Nick Chan
2025-02-20 12:21 ` [PATCH 3/9] arm64: dts: apple: t7001: " Nick Chan
` (7 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Nick Chan @ 2025-02-20 12:21 UTC (permalink / raw)
To: Sven Peter, Janne Grunau, Alyssa Rosenzweig, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: asahi, linux-arm-kernel, devicetree, linux-kernel, Nick Chan
Add information about CPU caches in Apple A8 SoC.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
arch/arm64/boot/dts/apple/t7000.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/apple/t7000.dtsi b/arch/arm64/boot/dts/apple/t7000.dtsi
index 32cac8c30e62d657079dbf32aece8af0fd9cef38..229ebd78c9d14609c30cdd011d1ec59847c846f8 100644
--- a/arch/arm64/boot/dts/apple/t7000.dtsi
+++ b/arch/arm64/boot/dts/apple/t7000.dtsi
@@ -37,6 +37,9 @@ cpu0: cpu@0 {
operating-points-v2 = <&typhoon_opp>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache>;
+ i-cache-size = <0x10000>;
+ d-cache-size = <0x10000>;
};
cpu1: cpu@1 {
@@ -47,6 +50,16 @@ cpu1: cpu@1 {
operating-points-v2 = <&typhoon_opp>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache>;
+ i-cache-size = <0x10000>;
+ d-cache-size = <0x10000>;
+ };
+
+ l2_cache: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x100000>;
};
};
--
2.48.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 3/9] arm64: dts: apple: t7001: Add CPU caches
2025-02-20 12:21 [PATCH 0/9] arm64: dts: apple: Add CPU cache information for Apple A7-A11, T2 SoCs Nick Chan
2025-02-20 12:21 ` [PATCH 1/9] arm64: dts: apple: s5l8960x: Add CPU caches Nick Chan
2025-02-20 12:21 ` [PATCH 2/9] arm64: dts: apple: t7000: " Nick Chan
@ 2025-02-20 12:21 ` Nick Chan
2025-02-20 12:21 ` [PATCH 4/9] arm64: dts: apple: s800-0-3: " Nick Chan
` (6 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Nick Chan @ 2025-02-20 12:21 UTC (permalink / raw)
To: Sven Peter, Janne Grunau, Alyssa Rosenzweig, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: asahi, linux-arm-kernel, devicetree, linux-kernel, Nick Chan
Add information about CPU caches in Apple A8X SoC.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
arch/arm64/boot/dts/apple/t7001.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/apple/t7001.dtsi b/arch/arm64/boot/dts/apple/t7001.dtsi
index 8e2c67e19c4167fc6639458ce79588e153336603..a2efa81305df47bdfea6bc2a4d6749719a6ee619 100644
--- a/arch/arm64/boot/dts/apple/t7001.dtsi
+++ b/arch/arm64/boot/dts/apple/t7001.dtsi
@@ -39,6 +39,9 @@ cpu0: cpu@0 {
operating-points-v2 = <&typhoon_opp>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache>;
+ i-cache-size = <0x10000>;
+ d-cache-size = <0x10000>;
};
cpu1: cpu@1 {
@@ -49,6 +52,9 @@ cpu1: cpu@1 {
operating-points-v2 = <&typhoon_opp>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache>;
+ i-cache-size = <0x10000>;
+ d-cache-size = <0x10000>;
};
cpu2: cpu@2 {
@@ -59,6 +65,16 @@ cpu2: cpu@2 {
operating-points-v2 = <&typhoon_opp>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache>;
+ i-cache-size = <0x10000>;
+ d-cache-size = <0x10000>;
+ };
+
+ l2_cache: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x200000>;
};
};
--
2.48.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 4/9] arm64: dts: apple: s800-0-3: Add CPU caches
2025-02-20 12:21 [PATCH 0/9] arm64: dts: apple: Add CPU cache information for Apple A7-A11, T2 SoCs Nick Chan
` (2 preceding siblings ...)
2025-02-20 12:21 ` [PATCH 3/9] arm64: dts: apple: t7001: " Nick Chan
@ 2025-02-20 12:21 ` Nick Chan
2025-02-20 12:21 ` [PATCH 5/9] arm64: dts: apple: s8001: " Nick Chan
` (5 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Nick Chan @ 2025-02-20 12:21 UTC (permalink / raw)
To: Sven Peter, Janne Grunau, Alyssa Rosenzweig, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: asahi, linux-arm-kernel, devicetree, linux-kernel, Nick Chan
Add information about CPU caches in both variants of Apple A9 SoC.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
arch/arm64/boot/dts/apple/s800-0-3.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/apple/s800-0-3.dtsi b/arch/arm64/boot/dts/apple/s800-0-3.dtsi
index 2aec49f0da6467519aeb2561d00b14f46fe216fb..e56697689d953fdb0da9d23b57fd92b6f8eb5756 100644
--- a/arch/arm64/boot/dts/apple/s800-0-3.dtsi
+++ b/arch/arm64/boot/dts/apple/s800-0-3.dtsi
@@ -36,6 +36,9 @@ cpu0: cpu@0 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache>;
+ i-cache-size = <0x10000>;
+ d-cache-size = <0x10000>;
};
cpu1: cpu@1 {
@@ -46,6 +49,16 @@ cpu1: cpu@1 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache>;
+ i-cache-size = <0x10000>;
+ d-cache-size = <0x10000>;
+ };
+
+ l2_cache: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x300000>;
};
};
--
2.48.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 5/9] arm64: dts: apple: s8001: Add CPU caches
2025-02-20 12:21 [PATCH 0/9] arm64: dts: apple: Add CPU cache information for Apple A7-A11, T2 SoCs Nick Chan
` (3 preceding siblings ...)
2025-02-20 12:21 ` [PATCH 4/9] arm64: dts: apple: s800-0-3: " Nick Chan
@ 2025-02-20 12:21 ` Nick Chan
2025-02-20 12:21 ` [PATCH 6/9] arm64: dts: apple: t8010: " Nick Chan
` (4 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Nick Chan @ 2025-02-20 12:21 UTC (permalink / raw)
To: Sven Peter, Janne Grunau, Alyssa Rosenzweig, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: asahi, linux-arm-kernel, devicetree, linux-kernel, Nick Chan
Add information about CPU caches in Apple A9X SoC.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
arch/arm64/boot/dts/apple/s8001.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/apple/s8001.dtsi b/arch/arm64/boot/dts/apple/s8001.dtsi
index d56d49c048bbf55e5f2edf40f6fd1fcff6342a9f..fee3507658948a9b4db6a185665fdff9f5acc446 100644
--- a/arch/arm64/boot/dts/apple/s8001.dtsi
+++ b/arch/arm64/boot/dts/apple/s8001.dtsi
@@ -36,6 +36,9 @@ cpu0: cpu@0 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache>;
+ i-cache-size = <0x10000>;
+ d-cache-size = <0x10000>;
};
cpu1: cpu@1 {
@@ -46,6 +49,16 @@ cpu1: cpu@1 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache>;
+ i-cache-size = <0x10000>;
+ d-cache-size = <0x10000>;
+ };
+
+ l2_cache: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x300000>;
};
};
--
2.48.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 6/9] arm64: dts: apple: t8010: Add CPU caches
2025-02-20 12:21 [PATCH 0/9] arm64: dts: apple: Add CPU cache information for Apple A7-A11, T2 SoCs Nick Chan
` (4 preceding siblings ...)
2025-02-20 12:21 ` [PATCH 5/9] arm64: dts: apple: s8001: " Nick Chan
@ 2025-02-20 12:21 ` Nick Chan
2025-02-20 12:21 ` [PATCH 7/9] arm64: dts: apple: t8011: " Nick Chan
` (3 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Nick Chan @ 2025-02-20 12:21 UTC (permalink / raw)
To: Sven Peter, Janne Grunau, Alyssa Rosenzweig, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: asahi, linux-arm-kernel, devicetree, linux-kernel, Nick Chan
Add information about CPU caches in the P-cluster of Apple A10 SoC. Due to
"Apple Fusion Architecture" big.LITTLE switcher, only caches from one of
the clusters can be used at any given moment.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
arch/arm64/boot/dts/apple/t8010.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/apple/t8010.dtsi b/arch/arm64/boot/dts/apple/t8010.dtsi
index b355d443ee476e7c98b352470e3b1b5d0fae7652..5d24da52cf255b6ad211d2ac40aad75a6194d595 100644
--- a/arch/arm64/boot/dts/apple/t8010.dtsi
+++ b/arch/arm64/boot/dts/apple/t8010.dtsi
@@ -36,6 +36,9 @@ cpu0: cpu@0 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache>;
+ i-cache-size = <0x10000>; /* P-core */
+ d-cache-size = <0x10000>; /* P-core */
};
cpu1: cpu@1 {
@@ -46,6 +49,16 @@ cpu1: cpu@1 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache>;
+ i-cache-size = <0x10000>; /* P-core */
+ d-cache-size = <0x10000>; /* P-core */
+ };
+
+ l2_cache: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x300000>; /* P-cluster */
};
};
--
2.48.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 7/9] arm64: dts: apple: t8011: Add CPU caches
2025-02-20 12:21 [PATCH 0/9] arm64: dts: apple: Add CPU cache information for Apple A7-A11, T2 SoCs Nick Chan
` (5 preceding siblings ...)
2025-02-20 12:21 ` [PATCH 6/9] arm64: dts: apple: t8010: " Nick Chan
@ 2025-02-20 12:21 ` Nick Chan
2025-02-20 12:21 ` [PATCH 8/9] arm64: dts: apple: t8012: " Nick Chan
` (2 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Nick Chan @ 2025-02-20 12:21 UTC (permalink / raw)
To: Sven Peter, Janne Grunau, Alyssa Rosenzweig, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: asahi, linux-arm-kernel, devicetree, linux-kernel, Nick Chan
Add information about CPU caches in the P-cluster of Apple A10X SoC. Due to
"Apple Fusion Architecture" big.LITTLE switcher, only caches from one of
the clusters can be used at any given moment.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
arch/arm64/boot/dts/apple/t8011.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/apple/t8011.dtsi b/arch/arm64/boot/dts/apple/t8011.dtsi
index 5b280c896b760dc8b759bf38dae79060e34dfc19..974f78cc77cfe28d3c26a52a292b643172d8f5bd 100644
--- a/arch/arm64/boot/dts/apple/t8011.dtsi
+++ b/arch/arm64/boot/dts/apple/t8011.dtsi
@@ -36,6 +36,9 @@ cpu0: cpu@0 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache>;
+ i-cache-size = <0x10000>; /* P-core */
+ d-cache-size = <0x10000>; /* P-core */
};
cpu1: cpu@1 {
@@ -46,6 +49,9 @@ cpu1: cpu@1 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache>;
+ i-cache-size = <0x10000>; /* P-core */
+ d-cache-size = <0x10000>; /* P-core */
};
cpu2: cpu@2 {
@@ -56,6 +62,16 @@ cpu2: cpu@2 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache>;
+ i-cache-size = <0x10000>; /* P-core */
+ d-cache-size = <0x10000>; /* P-core */
+ };
+
+ l2_cache: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x800000>; /* P-cluster */
};
};
--
2.48.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 8/9] arm64: dts: apple: t8012: Add CPU caches
2025-02-20 12:21 [PATCH 0/9] arm64: dts: apple: Add CPU cache information for Apple A7-A11, T2 SoCs Nick Chan
` (6 preceding siblings ...)
2025-02-20 12:21 ` [PATCH 7/9] arm64: dts: apple: t8011: " Nick Chan
@ 2025-02-20 12:21 ` Nick Chan
2025-02-20 12:21 ` [PATCH 9/9] arm64: dts: apple: t8015: " Nick Chan
2025-03-01 11:11 ` [PATCH 0/9] arm64: dts: apple: Add CPU cache information for Apple A7-A11, T2 SoCs Sven Peter
9 siblings, 0 replies; 12+ messages in thread
From: Nick Chan @ 2025-02-20 12:21 UTC (permalink / raw)
To: Sven Peter, Janne Grunau, Alyssa Rosenzweig, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: asahi, linux-arm-kernel, devicetree, linux-kernel, Nick Chan
Add information about CPU caches in the P-cluster of Apple T2 SoC. Due to
"Apple Fusion Architecture" big.LITTLE switcher, only caches from one of
the clusters can be used at any given moment.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
arch/arm64/boot/dts/apple/t8012.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/apple/t8012.dtsi b/arch/arm64/boot/dts/apple/t8012.dtsi
index 42df2f51ad7be4c4533e76d18e49a9a747b6b7a8..a259e5735d938cfa5b29cee6c754c7a3c0aaae08 100644
--- a/arch/arm64/boot/dts/apple/t8012.dtsi
+++ b/arch/arm64/boot/dts/apple/t8012.dtsi
@@ -36,6 +36,9 @@ cpu0: cpu@10000 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache>;
+ i-cache-size = <0x10000>; /* P-core */
+ d-cache-size = <0x10000>; /* P-core */
};
cpu1: cpu@10001 {
@@ -46,6 +49,16 @@ cpu1: cpu@10001 {
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache>;
+ i-cache-size = <0x10000>; /* P-core */
+ d-cache-size = <0x10000>; /* P-core */
+ };
+
+ l2_cache: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x300000>; /* P-cluster */
};
};
--
2.48.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 9/9] arm64: dts: apple: t8015: Add CPU caches
2025-02-20 12:21 [PATCH 0/9] arm64: dts: apple: Add CPU cache information for Apple A7-A11, T2 SoCs Nick Chan
` (7 preceding siblings ...)
2025-02-20 12:21 ` [PATCH 8/9] arm64: dts: apple: t8012: " Nick Chan
@ 2025-02-20 12:21 ` Nick Chan
2025-03-01 11:11 ` [PATCH 0/9] arm64: dts: apple: Add CPU cache information for Apple A7-A11, T2 SoCs Sven Peter
9 siblings, 0 replies; 12+ messages in thread
From: Nick Chan @ 2025-02-20 12:21 UTC (permalink / raw)
To: Sven Peter, Janne Grunau, Alyssa Rosenzweig, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: asahi, linux-arm-kernel, devicetree, linux-kernel, Nick Chan
Add information about CPU caches in Apple A11 SoC.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
arch/arm64/boot/dts/apple/t8015.dtsi | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/apple/t8015.dtsi b/arch/arm64/boot/dts/apple/t8015.dtsi
index b68647bebd20782ba7a125e670b3264c184b62cd..138073dbac3c5a3ec495b078b3714cf800b471dd 100644
--- a/arch/arm64/boot/dts/apple/t8015.dtsi
+++ b/arch/arm64/boot/dts/apple/t8015.dtsi
@@ -63,6 +63,9 @@ cpu_e0: cpu@0 {
capacity-dmips-mhz = <633>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache_0>;
+ i-cache-size = <0x8000>;
+ d-cache-size = <0x8000>;
};
cpu_e1: cpu@1 {
@@ -74,6 +77,9 @@ cpu_e1: cpu@1 {
capacity-dmips-mhz = <633>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache_0>;
+ i-cache-size = <0x8000>;
+ d-cache-size = <0x8000>;
};
cpu_e2: cpu@2 {
@@ -85,6 +91,9 @@ cpu_e2: cpu@2 {
capacity-dmips-mhz = <633>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache_0>;
+ i-cache-size = <0x8000>;
+ d-cache-size = <0x8000>;
};
cpu_e3: cpu@3 {
@@ -96,6 +105,9 @@ cpu_e3: cpu@3 {
capacity-dmips-mhz = <633>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache_0>;
+ i-cache-size = <0x8000>;
+ d-cache-size = <0x8000>;
};
cpu_p0: cpu@10004 {
@@ -107,6 +119,9 @@ cpu_p0: cpu@10004 {
capacity-dmips-mhz = <1024>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache_1>;
+ i-cache-size = <0x10000>;
+ d-cache-size = <0x10000>;
};
cpu_p1: cpu@10005 {
@@ -118,6 +133,23 @@ cpu_p1: cpu@10005 {
capacity-dmips-mhz = <1024>;
enable-method = "spin-table";
device_type = "cpu";
+ next-level-cache = <&l2_cache_1>;
+ i-cache-size = <0x10000>;
+ d-cache-size = <0x10000>;
+ };
+
+ l2_cache_0: l2-cache-0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x100000>;
+ };
+
+ l2_cache_1: l2-cache-1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x800000>;
};
};
--
2.48.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 0/9] arm64: dts: apple: Add CPU cache information for Apple A7-A11, T2 SoCs
2025-02-20 12:21 [PATCH 0/9] arm64: dts: apple: Add CPU cache information for Apple A7-A11, T2 SoCs Nick Chan
` (8 preceding siblings ...)
2025-02-20 12:21 ` [PATCH 9/9] arm64: dts: apple: t8015: " Nick Chan
@ 2025-03-01 11:11 ` Sven Peter
2025-03-01 12:32 ` Nick Chan
9 siblings, 1 reply; 12+ messages in thread
From: Sven Peter @ 2025-03-01 11:11 UTC (permalink / raw)
To: Nick Chan, Janne Grunau, Alyssa Rosenzweig, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: asahi, linux-arm-kernel, devicetree, linux-kernel
Hi,
On Thu, Feb 20, 2025, at 13:21, Nick Chan wrote:
> Add CPU cache information for Apple A7-A11, T2 SoCs. On Apple
> A10 (T8010), A10X (T8011), T2 (T8012), only the caches in one of the
> CPU clusters can be used due to the "Apple Fusion Architecture"
> big.LITTLE switcher. The values for the P-cluster is used in this
> case.
So this means that the cache information will be "wrong" when the CPU
is in the lower power states and only correct for the higher ones?
I'm not familiar with how these values are used; are you and do you
know if this will have any weird or unexpected effects?
Would it be better to use the cache size for the lower rather than
the higher states or does this not matter much?
Best,
Sven
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 0/9] arm64: dts: apple: Add CPU cache information for Apple A7-A11, T2 SoCs
2025-03-01 11:11 ` [PATCH 0/9] arm64: dts: apple: Add CPU cache information for Apple A7-A11, T2 SoCs Sven Peter
@ 2025-03-01 12:32 ` Nick Chan
0 siblings, 0 replies; 12+ messages in thread
From: Nick Chan @ 2025-03-01 12:32 UTC (permalink / raw)
To: Sven Peter, Janne Grunau, Alyssa Rosenzweig, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: asahi, linux-arm-kernel, devicetree, linux-kernel
Sven Peter 於 2025/3/1 夜晚7:11 寫道:
> Hi,
>
> On Thu, Feb 20, 2025, at 13:21, Nick Chan wrote:
>> Add CPU cache information for Apple A7-A11, T2 SoCs. On Apple
>> A10 (T8010), A10X (T8011), T2 (T8012), only the caches in one of the
>> CPU clusters can be used due to the "Apple Fusion Architecture"
>> big.LITTLE switcher. The values for the P-cluster is used in this
>> case.
> So this means that the cache information will be "wrong" when the CPU
> is in the lower power states and only correct for the higher ones?
> I'm not familiar with how these values are used; are you and do you
> know if this will have any weird or unexpected effects?
> Would it be better to use the cache size for the lower rather than
> the higher states or does this not matter much?
The information in the device tree is only used for reporting cache sizes in /sys/devices/system/cpu.
It represents the physical cache size which may not be the same as the architecturally visible cache
size. Cache operations in the kernel consult ccsidr_el1 and csselr_el1, so it should be fine.
>
>
>
> Best,
>
>
> Sven
Nick Chan
^ permalink raw reply [flat|nested] 12+ messages in thread