From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6723CC021B1 for ; Thu, 20 Feb 2025 18:30:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:References: List-Owner; bh=gzNH8x4NOGW0cud1f8ME8sdfxa05diGDGx+/4XOkv5w=; b=DlKCIU0UN+/ycG b3/tpsSigM2wVmA1Na9Kmj8PF63vRdg24CnkAoQ/VdjwBaEBdCvJvWZwAfgXiZBQcAxtxLnCBR564 RPkUTi8eHybpVFmbtiNDTQNEnyA3DXPrNT4HknYfHUXV81B+OBiFjueJLkFPO9/VpNXLgUpHDoodP xG3V1wPhHi+d0qq6Zh1YYpKQEwg15SMtd0F9+7QEMnshYH8Syvq/nlmcTdcsMgfqmEus5aSl5ncA6 aEjxgSZ3LTt6OKCDXGJdfI0jJxGqna1+llQn0pOIiJMbZv56ZssWf2OKakJetHaFklUxPGCQA4PW8 xsOaVvGxSfVSspTvM2CQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tlBJ6-00000002NMq-1YDj; Thu, 20 Feb 2025 18:29:56 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tlBAH-00000002Kuc-13PP; Thu, 20 Feb 2025 18:20:50 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 658B85C5F26; Thu, 20 Feb 2025 18:20:09 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0BFBDC4CED1; Thu, 20 Feb 2025 18:20:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1740075648; bh=goF2sXGlwePNxi5jXjCq7qXTeQ/IBQiDq6ijNZ4pmnQ=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=PAB7y20XkqjVJWJyMszBT2gK8dHTBRm1WnFEnoSGcwRQboueF7LTqLi97yrR7aW8a ec9hWNjpBclx1fMFB+5NQ+a0eELhDRFNsVoOF0zaK1R3OyQsEgxNZGg/5SbSs8rTd0 RmYWSE7Ba49iPbYfnws3o7DoaqyDNnlq1Br4qjR3PN2UbS/NXgLbSgV3sPrx+nXZnY cm415/43Uw8gX5j6UqRyDvfgpTsprHWy/NZh6Wy7WR92oT+cqNi5vmfvZlDEyBDwZj YCamWFjRj0Cg8MaechwLKmK9Vn9zTe6T7zvW6qEpZo80fwEFD1CWh3xEdZXQWkFwgU 4SXT3GNl6aqJg== Date: Thu, 20 Feb 2025 12:20:46 -0600 From: Bjorn Helgaas To: Lorenzo Bianconi Cc: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 2/2] PCI: mediatek-gen3: Configure PBUS_CSR registers for EN7581 SoC Message-ID: <20250220182046.GA304343@bhelgaas> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250202-en7581-pcie-pbus-csr-v2-2-65dcb201c9a9@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250220_102049_343469_4590ACC7 X-CRM114-Status: GOOD ( 14.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sun, Feb 02, 2025 at 08:34:24PM +0100, Lorenzo Bianconi wrote: > Configure PBus base address and address mask to allow the hw > to detect if a given address is on PCIE0, PCIE1 or PCIE2. > > Signed-off-by: Lorenzo Bianconi > --- > drivers/pci/controller/pcie-mediatek-gen3.c | 30 ++++++++++++++++++++++++++++- > 1 file changed, 29 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c > index aa24ac9aaecc749b53cfc4faf6399913d20cdbf2..9c2a592cae959de8fbe9ca5c5c2253f8eadf2c76 100644 > --- a/drivers/pci/controller/pcie-mediatek-gen3.c > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c > @@ -15,6 +15,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -24,6 +25,7 @@ > #include > #include > #include > +#include > #include > > #include "../pci.h" > @@ -127,6 +129,13 @@ > > #define PCIE_MTK_RESET_TIME_US 10 > > +#define PCIE_EN7581_PBUS_ADDR(_n) (0x00 + ((_n) << 3)) > +#define PCIE_EN7581_PBUS_ADDR_MASK(_n) (0x04 + ((_n) << 3)) > +#define PCIE_EN7581_PBUS_BASE_ADDR(_n) \ > + ((_n) == 2 ? 0x28000000 : \ > + (_n) == 1 ? 0x24000000 : 0x20000000) Are these addresses something that should be expressed in devicetree? It seems unusual to encode addresses directly in a driver. Bjorn