Re: [PATCH 2/2] PCI: dw-rockchip: hide broken ATS capability

[Bjorn Helgaas <helgaas@kernel.org>]

On Fri, Feb 21, 2025 at 09:26:48PM +0100, Niklas Cassel wrote:
> When running the rk3588 in endpoint mode, with an Intel host with IOMMU
> enabled, the host side prints:
> DMAR: VT-d detected Invalidation Time-out Error: SID 0
> 
> When running the rk3588 in endpoint mode, with an AMD host with IOMMU
> enabled, the host side prints:
> iommu ivhd0: AMD-Vi: Event logged [IOTLB_INV_TIMEOUT device=63:00.0 address=0x42b5b01a0]

Maybe add a blank line and indent the message since it's quoted
material?  E.g.,

  When running the rk3588 in endpoint mode, with an Intel IOMMU, the
  host side prints:

    DMAR: VT-d detected Invalidation Time-out Error: SID 0

  When running the rk3588 in endpoint mode, with an AMD ...

    iommu ivhd0: AMD-Vi: Event logged [IOTLB_INV_TIMEOUT device=63:00.0 address=0x42b5b01a0]

Too bad DMAR isn't smart enough to include a device ID in its message ;)

Can you include something here about what the issue is?  Based on the
subject line and the patch, I assume something is wrong with the ATS
Capability?  I guess this is some kind of rk3588 defect, right?

> Usually, to handle these issues, we add a quirk for the PCI vendor and
> device ID in drivers/pci/quirks.c with quirk_no_ats(). That is because
> we cannot usually modify the capabilities on the EP side.
> 
> In this case, we can modify the capabilties on the EP side. Thus, hide the
> broken ATS capability on rk3588 when running in EP mode. That way,
> we don't need any quirk on the host side, and we see no errors on the host
> side, and we can run pci_endpoint_test successfully, with the IOMMU
> enabled on the host side.

s/capabilties/capabilities/

Bjorn