From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Lorenzo Bianconi <lorenzo@kernel.org>
Cc: "Ryder Lee" <ryder.lee@mediatek.com>,
"Jianjun Wang" <jianjun.wang@mediatek.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Matthias Brugger" <matthias.bgg@gmail.com>,
"AngeloGioacchino Del Regno"
<angelogioacchino.delregno@collabora.com>,
linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>
Subject: Re: [PATCH v3 2/2] PCI: mediatek-gen3: Configure PBUS_CSR registers for EN7581 SoC
Date: Mon, 24 Feb 2025 18:48:31 +0530 [thread overview]
Message-ID: <20250224131831.jqut4hpvv7tf7vzy@thinkpad> (raw)
In-Reply-To: <Z7xEZPpWLQjTMnIz@lore-desk>
On Mon, Feb 24, 2025 at 11:05:24AM +0100, Lorenzo Bianconi wrote:
> > On Sat, Feb 22, 2025 at 11:43:45AM +0100, Lorenzo Bianconi wrote:
>
> [...]
>
> > > +
> > > + entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
> > > + if (!entry)
> > > + return -EINVAL;
> >
> > -ENODEV or -ENOMEM
>
> ack, I will fix it in v4
>
> >
> > > +
> > > + addr = entry->res->start - entry->offset;
> > > + err = regmap_write(pbus_regmap, args[0], lower_32_bits(addr));
> > > + if (err)
> >
> > MMIO write is not supposed to fail.
>
> ack, I will fix it in v4
>
> >
> > > + return err;
> > > +
> > > + size = lower_32_bits(resource_size(entry->res));
> > > + mask = size ? GENMASK(31, __fls(size)) : 0;
> >
> > Size of MEM region could be 0?
>
> I added this check since we consider just lower_32_bits().
> Do you think we should remove it?
>
Yes please.
> >
> > > + err = regmap_write(pbus_regmap, args[1], mask);
> > > + if (err)
> >
> > MMIO write is not supposed to fail.
>
> ack, I will fix it in v4
>
> BTW I will remove your Reviwed-by tag since the patch has changed
> with respect to the one you added it. Please let me know if you
> prepfer to keep it.
>
Sure, fine with me.
- Mani
--
மணிவண்ணன் சதாசிவம்
prev parent reply other threads:[~2025-02-24 13:20 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-22 10:43 [PATCH v3 0/2] PCI: mediatek-gen3: Set PBUS_CSR regs for Airoha EN7581 SoC Lorenzo Bianconi
2025-02-22 10:43 ` [PATCH v3 1/2] dt-bindings: PCI: mediatek-gen3: Add mediatek,pbus-csr phandle array property Lorenzo Bianconi
2025-02-23 9:43 ` Krzysztof Kozlowski
2025-02-23 13:39 ` Lorenzo Bianconi
2025-02-24 8:26 ` Krzysztof Kozlowski
2025-02-24 5:43 ` Manivannan Sadhasivam
2025-02-22 10:43 ` [PATCH v3 2/2] PCI: mediatek-gen3: Configure PBUS_CSR registers for EN7581 SoC Lorenzo Bianconi
2025-02-24 5:52 ` Manivannan Sadhasivam
2025-02-24 10:05 ` Lorenzo Bianconi
2025-02-24 13:18 ` Manivannan Sadhasivam [this message]
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