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[209.17.68.221]) by smtp.gmail.com with UTF8SMTPSA id d9443c01a7336-220d5586075sm178543045ad.228.2025.02.24.06.18.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2025 06:18:59 -0800 (PST) Date: Mon, 24 Feb 2025 23:18:58 +0900 From: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= To: Bjorn Helgaas Cc: Niklas Cassel , Lorenzo Pieralisi , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Damien Le Moal , Shawn Lin , Simon Xue , Wenrui Li , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: Re: [PATCH 2/2] PCI: dw-rockchip: hide broken ATS capability Message-ID: <20250224141858.GB76745@rocinante> References: <20250221202646.395252-4-cassel@kernel.org> <20250222000029.GA373377@bhelgaas> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250222000029.GA373377@bhelgaas> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250224_061901_793432_1B31C89C X-CRM114-Status: GOOD ( 17.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello, [...] > Can you include something here about what the issue is? Based on the > subject line and the patch, I assume something is wrong with the ATS > Capability? I guess this is some kind of rk3588 defect, right? > > > Usually, to handle these issues, we add a quirk for the PCI vendor and > > device ID in drivers/pci/quirks.c with quirk_no_ats(). That is because > > we cannot usually modify the capabilities on the EP side. > > > > In this case, we can modify the capabilties on the EP side. Thus, hide the > > broken ATS capability on rk3588 when running in EP mode. That way, > > we don't need any quirk on the host side, and we see no errors on the host > > side, and we can run pci_endpoint_test successfully, with the IOMMU > > enabled on the host side. Rockchip folks, anything to add about this issue? Perhaps there is an erratum about this? Any code reviews? Anything? Western Digital folks are doing you a lot of favour with all the upstream work they do maintaining drivers for your platforms. But it would be nice if Rockchip took some ownership. I have seen none recently. No reviews, not even an Acked-by, nothing. A bit of a letdown, if you ask me. Thank you! Krzysztof