[PATCH v4 0/6] arm64: Introduce CIX P1 (SKY1) SoC

[PATCH v4 0/6] arm64: Introduce CIX P1 (SKY1) SoC

[Peter Chen]

Cixtech P1 (internal name sky1) is high performance generic Armv9 SoC.
Orion O6 is the world's first open source Arm V9 Motherboard built by
Radxa. You could find brief introduction for SoC and related boards at:
https://radxa.com/products/orion/o6#overview

In this series, we add initial SoC and board support for Kernel building.
Patch 1-2: Add dt-binding doc for CIX and its sky1 SoC
Patch 3: add related maintainers entry
Patch 4-5: add Arm64 build support
Patch 6: add initial dts support for SoC and Orion O6 board

To run upstream kernel at Orion O6 board, you need to use BIOS
released by Radxa:
https://docs.radxa.com/en/orion/o6/bios/install-bios

Changes for v4:
- Move add MAINTAINERS entry patch to the last, and add two dts files entry in it. 
- Add three Krzysztof Kozlowski's Reviewed-by Tags
- For sky1.dtsi, makes below changes:
	- Add ppi-partition entry for gic-v3 node, and let pmu-a520 and pmu-a720's interrupt entry
	get its handle
	- Remove gic-v3's #redistributor-regions and redistributor-stride properties
	- Change gic-v3's #interrupt-cells as 4, and change all interrupt specifiers accordingly
	- Remove "arm,no-tick-in-suspend" for timer due to global counter is at always-on power domain
	- Remove timer's clock frequency due to firmware has already set it

Changes for v3:
- Patch 1: Add Krzysztof Kozlowski's Acked-by Tag
- Patch 2: Add Krzysztof Kozlowski's Reviewed-by Tag
- Patch 6: Fix two dts coding sytle issues

Changes for v2:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=vendor-prefixes.yaml
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=arm/cix.yaml
make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb
- Re-order the patch set, and move vendor-perfixes to the 1st patch.
- Patch 4: Ordered Kconfig config entry by alpha-numerically
- Patch 5: Corrects the Ack tag's name
- Patch 6: see below.
1) Corrects the SoF tag's name
2) Fix several coding sytle issues
3) move linux,cma node to dts file
4) delete memory node, memory size is passed by firmware
5) delete uart2 node which will be added in future patches
6) Improve for pmu and cpu node to stands for more specific cpu model
7) Improve the timer node and add hypervisor virtual timer irq

Fugang Duan (1):
  arm64: Kconfig: add ARCH_CIX for cix silicons

Peter Chen (5):
  dt-bindings: vendor-prefixes: Add CIX Technology Group Co., Ltd.
  dt-bindings: arm: add CIX P1 (SKY1) SoC
  arm64: defconfig: Enable CIX SoC
  arm64: dts: cix: add initial CIX P1(SKY1) dts support
  MAINTAINERS: Add CIX SoC maintainer entry

 .../devicetree/bindings/arm/cix.yaml          |  26 ++
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 MAINTAINERS                                   |  10 +
 arch/arm64/Kconfig.platforms                  |   6 +
 arch/arm64/boot/dts/Makefile                  |   1 +
 arch/arm64/boot/dts/cix/Makefile              |   2 +
 arch/arm64/boot/dts/cix/sky1-orion-o6.dts     |  26 ++
 arch/arm64/boot/dts/cix/sky1.dtsi             | 222 ++++++++++++++++++
 arch/arm64/configs/defconfig                  |   1 +
 9 files changed, 296 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/cix.yaml
 create mode 100644 arch/arm64/boot/dts/cix/Makefile
 create mode 100644 arch/arm64/boot/dts/cix/sky1-orion-o6.dts
 create mode 100644 arch/arm64/boot/dts/cix/sky1.dtsi

-- 
2.25.1

[PATCH v4 1/6] dt-bindings: vendor-prefixes: Add CIX Technology Group Co., Ltd.

[Peter Chen]

CIX Technology Group Co., Ltd. is a high performance Arm SoC design
company. Link: https://www.cixtech.com/.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Fugang Duan <fugang.duan@cixtech.com>
Signed-off-by: Peter Chen <peter.chen@cixtech.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 5079ca6ce1d1..5e76223e4570 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -302,6 +302,8 @@ patternProperties:
     description: Cirrus Logic, Inc.
   "^cisco,.*":
     description: Cisco Systems, Inc.
+  "^cix,.*":
+    description: CIX Technology Group Co., Ltd.
   "^clockwork,.*":
     description: Clockwork Tech LLC
   "^cloos,.*":
-- 
2.25.1

[PATCH v4 2/6] dt-bindings: arm: add CIX P1 (SKY1) SoC

[Peter Chen]

Add device tree bindings for CIX P1 (Internal name sky1) Arm SoC,
it consists several SoC models like CP8180, CD8180, etc.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Fugang Duan <fugang.duan@cixtech.com>
Signed-off-by: Peter Chen <peter.chen@cixtech.com>
---
 .../devicetree/bindings/arm/cix.yaml          | 26 +++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/cix.yaml

diff --git a/Documentation/devicetree/bindings/arm/cix.yaml b/Documentation/devicetree/bindings/arm/cix.yaml
new file mode 100644
index 000000000000..114dab4bc4d2
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cix.yaml
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/cix.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: CIX platforms
+
+maintainers:
+  - Peter Chen <peter.chen@cixtech.com>
+  - Fugang Duan <fugang.duan@cixtech.com>
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+
+      - description: Radxa Orion O6
+        items:
+          - const: radxa,orion-o6
+          - const: cix,sky1
+
+additionalProperties: true
+
+...
-- 
2.25.1

[PATCH v4 3/6] arm64: Kconfig: add ARCH_CIX for cix silicons

[Peter Chen]

From: Fugang Duan <fugang.duan@cixtech.com>

Add ARCH_CIX for CIX SoC series support.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Fugang Duan <fugang.duan@cixtech.com>
Signed-off-by: Peter Chen <peter.chen@cixtech.com>
---
Changes for v4:
- Add Krzysztof Kozlowski's Reviewed-by Tag

 arch/arm64/Kconfig.platforms | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 02f9248f7c84..abe41db9b9b3 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -106,6 +106,12 @@ config ARCH_BLAIZE
 	help
 	  This enables support for the Blaize SoC family
 
+config ARCH_CIX
+	bool "Cixtech SoC family"
+	help
+	  This enables support for the Cixtech SoC family,
+	  like P1(sky1).
+
 config ARCH_EXYNOS
 	bool "Samsung Exynos SoC family"
 	select COMMON_CLK_SAMSUNG
-- 
2.25.1

[PATCH v4 4/6] arm64: defconfig: Enable CIX SoC

[Peter Chen]

Enable CIX SoC support at ARM64 defconfig

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Fugang Duan <fugang.duan@cixtech.com>
Signed-off-by: Peter Chen <peter.chen@cixtech.com>
---
Changes for v4:
- Add Krzysztof Kozlowski's Reviewed-by Tag

 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index cb7da4415599..1dd46d200401 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -45,6 +45,7 @@ CONFIG_ARCH_BCMBCA=y
 CONFIG_ARCH_BRCMSTB=y
 CONFIG_ARCH_BERLIN=y
 CONFIG_ARCH_BLAIZE=y
+CONFIG_ARCH_CIX=y
 CONFIG_ARCH_EXYNOS=y
 CONFIG_ARCH_SPARX5=y
 CONFIG_ARCH_K3=y
-- 
2.25.1

[PATCH v4 5/6] arm64: dts: cix: add initial CIX P1(SKY1) dts support

[Peter Chen]

CIX SKY1 SoC is high performance Armv9 SoC designed by Cixtech,
and Orion O6 is open source motherboard launched by Radxa.
See below for detail:
https://docs.radxa.com/en/orion/o6/getting-started/introduction

In this commit, it only adds limited components for running initramfs
at Orion O6.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Fugang Duan <fugang.duan@cixtech.com>
Signed-off-by: Peter Chen <peter.chen@cixtech.com>
---
Changes for v4:
- Add ppi-partition entry for gic-v3 node, and let pmu-a520 and pmu-a720's interrupt entry
get its handle
- Remove gic-v3's #redistributor-regions and redistributor-stride properties
- Change gic-v3's #interrupt-cells as 4, and change all interrupt specifiers accordingly
- Remove "arm,no-tick-in-suspend" for timer due to global counter is at always-on power domain
- Remove timer's clock frequency due to firmware has already set it
- Add Krzysztof Kozlowski's reviewed-by
Changes for v3:
- Fix two dts coding sytle issues 
Changes for v2:
- Corrects the SoF tag's name
- Fix several coding sytle issues
- move linux,cma node to dts file
- delete memory node, memory size is passed by firmware
- delete uart2 node which will be added in future patches
- Improve for pmu and cpu node to stands for more specific cpu model
- Improve the timer node and add hypervisor virtual timer irq
- Pass "make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb"

 arch/arm64/boot/dts/Makefile              |   1 +
 arch/arm64/boot/dts/cix/Makefile          |   2 +
 arch/arm64/boot/dts/cix/sky1-orion-o6.dts |  26 +++
 arch/arm64/boot/dts/cix/sky1.dtsi         | 222 ++++++++++++++++++++++
 4 files changed, 251 insertions(+)
 create mode 100644 arch/arm64/boot/dts/cix/Makefile
 create mode 100644 arch/arm64/boot/dts/cix/sky1-orion-o6.dts
 create mode 100644 arch/arm64/boot/dts/cix/sky1.dtsi

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 79b73a21ddc2..8e7ccd0027bd 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -13,6 +13,7 @@ subdir-y += bitmain
 subdir-y += blaize
 subdir-y += broadcom
 subdir-y += cavium
+subdir-y += cix
 subdir-y += exynos
 subdir-y += freescale
 subdir-y += hisilicon
diff --git a/arch/arm64/boot/dts/cix/Makefile b/arch/arm64/boot/dts/cix/Makefile
new file mode 100644
index 000000000000..ed3713982012
--- /dev/null
+++ b/arch/arm64/boot/dts/cix/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_CIX) += sky1-orion-o6.dtb
diff --git a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
new file mode 100644
index 000000000000..78f4fcd87216
--- /dev/null
+++ b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2025 Cix Technology Group Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "sky1.dtsi"
+/ {
+	model = "Radxa Orion O6";
+	compatible = "radxa,orion-o6", "cix,sky1";
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x28000000>;
+			linux,cma-default;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
new file mode 100644
index 000000000000..5c5a2d1144c1
--- /dev/null
+++ b/arch/arm64/boot/dts/cix/sky1.dtsi
@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2025 Cix Technology Group Co., Ltd.
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a520";
+			enable-method = "psci";
+			reg = <0x0 0x0>;
+			device_type = "cpu";
+			capacity-dmips-mhz = <403>;
+		};
+
+		cpu1: cpu@100 {
+			compatible = "arm,cortex-a520";
+			enable-method = "psci";
+			reg = <0x0 0x100>;
+			device_type = "cpu";
+			capacity-dmips-mhz = <403>;
+		};
+
+		cpu2: cpu@200 {
+			compatible = "arm,cortex-a520";
+			enable-method = "psci";
+			reg = <0x0 0x200>;
+			device_type = "cpu";
+			capacity-dmips-mhz = <403>;
+		};
+
+		cpu3: cpu@300 {
+			compatible = "arm,cortex-a520";
+			enable-method = "psci";
+			reg = <0x0 0x300>;
+			device_type = "cpu";
+			capacity-dmips-mhz = <403>;
+		};
+
+		cpu4: cpu@400 {
+			compatible = "arm,cortex-a720";
+			enable-method = "psci";
+			reg = <0x0 0x400>;
+			device_type = "cpu";
+			capacity-dmips-mhz = <1024>;
+		};
+
+		cpu5: cpu@500 {
+			compatible = "arm,cortex-a720";
+			enable-method = "psci";
+			reg = <0x0 0x500>;
+			device_type = "cpu";
+			capacity-dmips-mhz = <1024>;
+		};
+
+		cpu6: cpu@600 {
+			compatible = "arm,cortex-a720";
+			enable-method = "psci";
+			reg = <0x0 0x600>;
+			device_type = "cpu";
+			capacity-dmips-mhz = <1024>;
+		};
+
+		cpu7: cpu@700 {
+			compatible = "arm,cortex-a720";
+			enable-method = "psci";
+			reg = <0x0 0x700>;
+			device_type = "cpu";
+			capacity-dmips-mhz = <1024>;
+		};
+
+		cpu8: cpu@800 {
+			compatible = "arm,cortex-a720";
+			enable-method = "psci";
+			reg = <0x0 0x800>;
+			device_type = "cpu";
+			capacity-dmips-mhz = <1024>;
+		};
+
+		cpu9: cpu@900 {
+			compatible = "arm,cortex-a720";
+			enable-method = "psci";
+			reg = <0x0 0x900>;
+			device_type = "cpu";
+			capacity-dmips-mhz = <1024>;
+		};
+
+		cpu10: cpu@a00 {
+			compatible = "arm,cortex-a720";
+			enable-method = "psci";
+			reg = <0x0 0xa00>;
+			device_type = "cpu";
+			capacity-dmips-mhz = <1024>;
+		};
+
+		cpu11: cpu@b00 {
+			compatible = "arm,cortex-a720";
+			enable-method = "psci";
+			reg = <0x0 0xb00>;
+			device_type = "cpu";
+			capacity-dmips-mhz = <1024>;
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+				core2 {
+					cpu = <&cpu2>;
+				};
+				core3 {
+					cpu = <&cpu3>;
+				};
+				core4 {
+					cpu = <&cpu4>;
+				};
+				core5 {
+					cpu = <&cpu5>;
+				};
+				core6 {
+					cpu = <&cpu6>;
+				};
+				core7 {
+					cpu = <&cpu7>;
+				};
+				core8 {
+					cpu = <&cpu8>;
+				};
+				core9 {
+					cpu = <&cpu9>;
+				};
+				core10 {
+					cpu = <&cpu10>;
+				};
+				core11 {
+					cpu = <&cpu11>;
+				};
+			};
+		};
+	};
+
+	pmu-a520 {
+		compatible = "arm,cortex-a520-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition0>;
+	};
+
+	pmu-a720 {
+		compatible = "arm,cortex-a720-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition1>;
+	};
+
+	pmu-spe {
+		compatible = "arm,statistical-profiling-extension-v1";
+		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW 0>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	soc@0 {
+		compatible = "simple-bus";
+		ranges = <0 0 0 0 0x20 0>;
+		dma-ranges;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		gic: interrupt-controller@e010000 {
+			compatible = "arm,gic-v3";
+			reg = <0x0 0x0e010000 0 0x10000>,	/* GICD */
+			      <0x0 0x0e090000 0 0x300000>;       /* GICR * 12 */
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW 0>;
+			#interrupt-cells = <4>;
+			interrupt-controller;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			gic_its: msi-controller@e050000 {
+				compatible = "arm,gic-v3-its";
+				reg = <0x0 0x0e050000 0x0 0x30000>;
+				msi-controller;
+				#msi-cells = <1>;
+			};
+
+			ppi-partitions {
+				ppi_partition0: interrupt-partition-0 {
+					affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
+				};
+
+				ppi_partition1: interrupt-partition-1 {
+					affinity = <&cpu4 &cpu5 &cpu6 &cpu7 &cpu8 &cpu9 &cpu10 &cpu11>;
+				};
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>,
+			     <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>;
+	};
+};
-- 
2.25.1

[PATCH v4 6/6] MAINTAINERS: Add CIX SoC maintainer entry

[Peter Chen]

Using this entry as the maintainers information for CIX SKY series SoCs.

Acked-by: Fugang Duan <fugang.duan@cixtech.com>
Signed-off-by: Peter Chen <peter.chen@cixtech.com>
---
Changes for v4
- Add two dts files as maintained files

 MAINTAINERS | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index efee40ea589f..edf26cf11ee2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2354,6 +2354,16 @@ F:	arch/arm/boot/compressed/misc-ep93xx.h
 F:	arch/arm/mach-ep93xx/
 F:	drivers/iio/adc/ep93xx_adc.c
 
+ARM/CIX SKY ARM ARCHITECTURE
+M:	Peter Chen <peter.chen@cixtech.com>
+M:	Fugang Duan <fugang.duan@cixtech.com>
+R:	CIX Linux Kernel Upstream Group <cix-kernel-upstream@cixtech.com>
+L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S:	Maintained
+F:	Documentation/devicetree/bindings/arm/cix.yaml
+F:	arch/arm64/boot/dts/cix/sky1-orion-o6.dts
+F:	arch/arm64/boot/dts/cix/sky1.dtsi
+
 ARM/CLKDEV SUPPORT
 M:	Russell King <linux@armlinux.org.uk>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-- 
2.25.1

Re: [PATCH v4 0/6] arm64: Introduce CIX P1 (SKY1) SoC

[Peter Chen]

On 25-03-05 13:38:17, Peter Chen wrote:
> Cixtech P1 (internal name sky1) is high performance generic Armv9 SoC.
> Orion O6 is the world's first open source Arm V9 Motherboard built by
> Radxa. You could find brief introduction for SoC and related boards at:
> https://radxa.com/products/orion/o6#overview
> 
> In this series, we add initial SoC and board support for Kernel building.
> Patch 1-2: Add dt-binding doc for CIX and its sky1 SoC
> Patch 3: add related maintainers entry
> Patch 4-5: add Arm64 build support
> Patch 6: add initial dts support for SoC and Orion O6 board
> 
> To run upstream kernel at Orion O6 board, you need to use BIOS
> released by Radxa:
> https://docs.radxa.com/en/orion/o6/bios/install-bios
> 
> Changes for v4:
> - Move add MAINTAINERS entry patch to the last, and add two dts files entry in it. 
> - Add three Krzysztof Kozlowski's Reviewed-by Tags
> - For sky1.dtsi, makes below changes:
> 	- Add ppi-partition entry for gic-v3 node, and let pmu-a520 and pmu-a720's interrupt entry
> 	get its handle
> 	- Remove gic-v3's #redistributor-regions and redistributor-stride properties
> 	- Change gic-v3's #interrupt-cells as 4, and change all interrupt specifiers accordingly
> 	- Remove "arm,no-tick-in-suspend" for timer due to global counter is at always-on power domain
> 	- Remove timer's clock frequency due to firmware has already set it

Hi Arnd,

I assume this series (all patches) will go your tree, right?

Peter

> 
> Changes for v3:
> - Patch 1: Add Krzysztof Kozlowski's Acked-by Tag
> - Patch 2: Add Krzysztof Kozlowski's Reviewed-by Tag
> - Patch 6: Fix two dts coding sytle issues
> 
> Changes for v2:
> - Pass dts build check with below commands:
> make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=vendor-prefixes.yaml
> make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=arm/cix.yaml
> make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb
> - Re-order the patch set, and move vendor-perfixes to the 1st patch.
> - Patch 4: Ordered Kconfig config entry by alpha-numerically
> - Patch 5: Corrects the Ack tag's name
> - Patch 6: see below.
> 1) Corrects the SoF tag's name
> 2) Fix several coding sytle issues
> 3) move linux,cma node to dts file
> 4) delete memory node, memory size is passed by firmware
> 5) delete uart2 node which will be added in future patches
> 6) Improve for pmu and cpu node to stands for more specific cpu model
> 7) Improve the timer node and add hypervisor virtual timer irq
> 
> Fugang Duan (1):
>   arm64: Kconfig: add ARCH_CIX for cix silicons
> 
> Peter Chen (5):
>   dt-bindings: vendor-prefixes: Add CIX Technology Group Co., Ltd.
>   dt-bindings: arm: add CIX P1 (SKY1) SoC
>   arm64: defconfig: Enable CIX SoC
>   arm64: dts: cix: add initial CIX P1(SKY1) dts support
>   MAINTAINERS: Add CIX SoC maintainer entry
> 
>  .../devicetree/bindings/arm/cix.yaml          |  26 ++
>  .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
>  MAINTAINERS                                   |  10 +
>  arch/arm64/Kconfig.platforms                  |   6 +
>  arch/arm64/boot/dts/Makefile                  |   1 +
>  arch/arm64/boot/dts/cix/Makefile              |   2 +
>  arch/arm64/boot/dts/cix/sky1-orion-o6.dts     |  26 ++
>  arch/arm64/boot/dts/cix/sky1.dtsi             | 222 ++++++++++++++++++
>  arch/arm64/configs/defconfig                  |   1 +
>  9 files changed, 296 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/cix.yaml
>  create mode 100644 arch/arm64/boot/dts/cix/Makefile
>  create mode 100644 arch/arm64/boot/dts/cix/sky1-orion-o6.dts
>  create mode 100644 arch/arm64/boot/dts/cix/sky1.dtsi
> 
> -- 
> 2.25.1
> 

-- 

Best regards,
Peter

Re: [PATCH v4 0/6] arm64: Introduce CIX P1 (SKY1) SoC

[Peter Chen]

On 25-03-11 09:02:29, Peter Chen wrote:
> On 25-03-05 13:38:17, Peter Chen wrote:
> > Cixtech P1 (internal name sky1) is high performance generic Armv9 SoC.
> > Orion O6 is the world's first open source Arm V9 Motherboard built by
> > Radxa. You could find brief introduction for SoC and related boards at:
> > https://radxa.com/products/orion/o6#overview
> > 
> > In this series, we add initial SoC and board support for Kernel building.
> > Patch 1-2: Add dt-binding doc for CIX and its sky1 SoC
> > Patch 3: add related maintainers entry
> > Patch 4-5: add Arm64 build support
> > Patch 6: add initial dts support for SoC and Orion O6 board
> > 
> > To run upstream kernel at Orion O6 board, you need to use BIOS
> > released by Radxa:
> > https://docs.radxa.com/en/orion/o6/bios/install-bios
> > 
> > Changes for v4:
> > - Move add MAINTAINERS entry patch to the last, and add two dts files entry in it. 
> > - Add three Krzysztof Kozlowski's Reviewed-by Tags
> > - For sky1.dtsi, makes below changes:
> > 	- Add ppi-partition entry for gic-v3 node, and let pmu-a520 and pmu-a720's interrupt entry
> > 	get its handle
> > 	- Remove gic-v3's #redistributor-regions and redistributor-stride properties
> > 	- Change gic-v3's #interrupt-cells as 4, and change all interrupt specifiers accordingly
> > 	- Remove "arm,no-tick-in-suspend" for timer due to global counter is at always-on power domain
> > 	- Remove timer's clock frequency due to firmware has already set it
> 
> Hi Arnd,
> 
> I assume this series (all patches) will go your tree, right?
> 

A gentle ping, thanks.

Peter

> Peter
> 
> > 
> > Changes for v3:
> > - Patch 1: Add Krzysztof Kozlowski's Acked-by Tag
> > - Patch 2: Add Krzysztof Kozlowski's Reviewed-by Tag
> > - Patch 6: Fix two dts coding sytle issues
> > 
> > Changes for v2:
> > - Pass dts build check with below commands:
> > make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=vendor-prefixes.yaml
> > make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=arm/cix.yaml
> > make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb
> > - Re-order the patch set, and move vendor-perfixes to the 1st patch.
> > - Patch 4: Ordered Kconfig config entry by alpha-numerically
> > - Patch 5: Corrects the Ack tag's name
> > - Patch 6: see below.
> > 1) Corrects the SoF tag's name
> > 2) Fix several coding sytle issues
> > 3) move linux,cma node to dts file
> > 4) delete memory node, memory size is passed by firmware
> > 5) delete uart2 node which will be added in future patches
> > 6) Improve for pmu and cpu node to stands for more specific cpu model
> > 7) Improve the timer node and add hypervisor virtual timer irq
> > 
> > Fugang Duan (1):
> >   arm64: Kconfig: add ARCH_CIX for cix silicons
> > 
> > Peter Chen (5):
> >   dt-bindings: vendor-prefixes: Add CIX Technology Group Co., Ltd.
> >   dt-bindings: arm: add CIX P1 (SKY1) SoC
> >   arm64: defconfig: Enable CIX SoC
> >   arm64: dts: cix: add initial CIX P1(SKY1) dts support
> >   MAINTAINERS: Add CIX SoC maintainer entry
> > 
> >  .../devicetree/bindings/arm/cix.yaml          |  26 ++
> >  .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
> >  MAINTAINERS                                   |  10 +
> >  arch/arm64/Kconfig.platforms                  |   6 +
> >  arch/arm64/boot/dts/Makefile                  |   1 +
> >  arch/arm64/boot/dts/cix/Makefile              |   2 +
> >  arch/arm64/boot/dts/cix/sky1-orion-o6.dts     |  26 ++
> >  arch/arm64/boot/dts/cix/sky1.dtsi             | 222 ++++++++++++++++++
> >  arch/arm64/configs/defconfig                  |   1 +
> >  9 files changed, 296 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/arm/cix.yaml
> >  create mode 100644 arch/arm64/boot/dts/cix/Makefile
> >  create mode 100644 arch/arm64/boot/dts/cix/sky1-orion-o6.dts
> >  create mode 100644 arch/arm64/boot/dts/cix/sky1.dtsi
> > 
> > -- 
> > 2.25.1
> > 
> 
> -- 
> 
> Best regards,
> Peter

-- 

Best regards,
Peter

Re: [PATCH v4 6/6] MAINTAINERS: Add CIX SoC maintainer entry

[Krzysztof Kozlowski]

On 05/03/2025 06:38, Peter Chen wrote:
> Using this entry as the maintainers information for CIX SKY series SoCs.
> 
> Acked-by: Fugang Duan <fugang.duan@cixtech.com>
> Signed-off-by: Peter Chen <peter.chen@cixtech.com>
> ---
> Changes for v4
> - Add two dts files as maintained files
> 
>  MAINTAINERS | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index efee40ea589f..edf26cf11ee2 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2354,6 +2354,16 @@ F:	arch/arm/boot/compressed/misc-ep93xx.h
>  F:	arch/arm/mach-ep93xx/
>  F:	drivers/iio/adc/ep93xx_adc.c
>  
> +ARM/CIX SKY ARM ARCHITECTURE
> +M:	Peter Chen <peter.chen@cixtech.com>
> +M:	Fugang Duan <fugang.duan@cixtech.com>
> +R:	CIX Linux Kernel Upstream Group <cix-kernel-upstream@cixtech.com>
> +L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> +S:	Maintained
> +F:	Documentation/devicetree/bindings/arm/cix.yaml
> +F:	arch/arm64/boot/dts/cix/sky1-orion-o6.dts
> +F:	arch/arm64/boot/dts/cix/sky1.dtsi

Instead:
arch/arm64/boot/dts/cix/

or if you think there will be more different architectures coming from
cix, which you will not maintain, then useful would be a "sky" subdirectory.

Best regards,
Krzysztof

Re: [PATCH v4 5/6] arm64: dts: cix: add initial CIX P1(SKY1) dts support

[Marc Zyngier]

On Wed, 05 Mar 2025 05:38:22 +0000,
Peter Chen <peter.chen@cixtech.com> wrote:
> 
> +	pmu-a520 {
> +		compatible = "arm,cortex-a520-pmu";
> +		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition0>;
> +	};
> +
> +	pmu-a720 {
> +		compatible = "arm,cortex-a720-pmu";
> +		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition1>;
> +	};
> +
> +	pmu-spe {
> +		compatible = "arm,statistical-profiling-extension-v1";
> +		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW 0>;
> +	};

SPE should follow the same model as the PMU, as each CPU has its own
SPE implementation, exposing different micro-architectural details.

The rest looks OK.

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH v4 5/6] arm64: dts: cix: add initial CIX P1(SKY1) dts support

[Peter Chen]

On 25-03-20 09:36:37, Marc Zyngier wrote:
> Peter Chen <peter.chen@cixtech.com> wrote:
> >
> > +     pmu-a520 {
> > +             compatible = "arm,cortex-a520-pmu";
> > +             interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition0>;
> > +     };
> > +
> > +     pmu-a720 {
> > +             compatible = "arm,cortex-a720-pmu";
> > +             interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition1>;
> > +     };
> > +
> > +     pmu-spe {
> > +             compatible = "arm,statistical-profiling-extension-v1";
> > +             interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW 0>;
> > +     };
> 
> SPE should follow the same model as the PMU, as each CPU has its own
> SPE implementation, exposing different micro-architectural details.
> 

Hi Marc,

Thanks for your reply. But there is only one compatible string
"statistical-profiling-extension-v1" at drivers/perf/arm_spe_pmu.c,
how could differentiate pmu-spe-a720 and pmu-spe-a520, do I need
to change arm_spe_pmu.c as well?

-- 

Best regards,
Peter

Re: [PATCH v4 6/6] MAINTAINERS: Add CIX SoC maintainer entry

[Peter Chen]

On 25-03-20 10:25:53, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL
> 
> On 05/03/2025 06:38, Peter Chen wrote:
> > Using this entry as the maintainers information for CIX SKY series SoCs.
> >
> > Acked-by: Fugang Duan <fugang.duan@cixtech.com>
> > Signed-off-by: Peter Chen <peter.chen@cixtech.com>
> > ---
> > Changes for v4
> > - Add two dts files as maintained files
> >
> >  MAINTAINERS | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index efee40ea589f..edf26cf11ee2 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -2354,6 +2354,16 @@ F:     arch/arm/boot/compressed/misc-ep93xx.h
> >  F:   arch/arm/mach-ep93xx/
> >  F:   drivers/iio/adc/ep93xx_adc.c
> >
> > +ARM/CIX SKY ARM ARCHITECTURE
> > +M:   Peter Chen <peter.chen@cixtech.com>
> > +M:   Fugang Duan <fugang.duan@cixtech.com>
> > +R:   CIX Linux Kernel Upstream Group <cix-kernel-upstream@cixtech.com>
> > +L:   linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> > +S:   Maintained
> > +F:   Documentation/devicetree/bindings/arm/cix.yaml
> > +F:   arch/arm64/boot/dts/cix/sky1-orion-o6.dts
> > +F:   arch/arm64/boot/dts/cix/sky1.dtsi
> 
> Instead:
> arch/arm64/boot/dts/cix/
> 
> or if you think there will be more different architectures coming from
> cix, which you will not maintain, then useful would be a "sky" subdirectory.
> 
Hi Krzysztof,

Thanks for your comment, CIX is Arm SoC based silicon design
company, we may have different SoC style for middle end in future.
So, for that SoC series, it may not name sky.

-- 

Best regards,
Peter

Re: [PATCH v4 6/6] MAINTAINERS: Add CIX SoC maintainer entry

[Kajetan Puchalski]

On Thu, Mar 20, 2025 at 06:49:47PM +0800, Peter Chen wrote:

(...)

> > > +ARM/CIX SKY ARM ARCHITECTURE
> > > +M:   Peter Chen <peter.chen@cixtech.com>
> > > +M:   Fugang Duan <fugang.duan@cixtech.com>
> > > +R:   CIX Linux Kernel Upstream Group <cix-kernel-upstream@cixtech.com>
> > > +L:   linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> > > +S:   Maintained
> > > +F:   Documentation/devicetree/bindings/arm/cix.yaml
> > > +F:   arch/arm64/boot/dts/cix/sky1-orion-o6.dts
> > > +F:   arch/arm64/boot/dts/cix/sky1.dtsi
> >
> > Instead:
> > arch/arm64/boot/dts/cix/
> >
> > or if you think there will be more different architectures coming from
> > cix, which you will not maintain, then useful would be a "sky" subdirectory.
> >
> Hi Krzysztof,
>
> Thanks for your comment, CIX is Arm SoC based silicon design
> company, we may have different SoC style for middle end in future.
> So, for that SoC series, it may not name sky.

I believe the idea is that the file should either say

+F:   arch/arm64/boot/dts/cix/

if the two of you intend to be maintainers for everything under cix/.
You don't need to list every specific file.

Otherwise it should say

+F:   arch/arm64/boot/dts/cix/sky/

with its own subdirectory if you only intend to be maintaining the sky family.

> --
>
> Best regards,
> Peter

Re: [PATCH v4 6/6] MAINTAINERS: Add CIX SoC maintainer entry

[Krzysztof Kozlowski]

On 20/03/2025 11:49, Peter Chen wrote:
> On 25-03-20 10:25:53, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL
>>
>> On 05/03/2025 06:38, Peter Chen wrote:
>>> Using this entry as the maintainers information for CIX SKY series SoCs.
>>>
>>> Acked-by: Fugang Duan <fugang.duan@cixtech.com>
>>> Signed-off-by: Peter Chen <peter.chen@cixtech.com>
>>> ---
>>> Changes for v4
>>> - Add two dts files as maintained files
>>>
>>>  MAINTAINERS | 10 ++++++++++
>>>  1 file changed, 10 insertions(+)
>>>
>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>> index efee40ea589f..edf26cf11ee2 100644
>>> --- a/MAINTAINERS
>>> +++ b/MAINTAINERS
>>> @@ -2354,6 +2354,16 @@ F:     arch/arm/boot/compressed/misc-ep93xx.h
>>>  F:   arch/arm/mach-ep93xx/
>>>  F:   drivers/iio/adc/ep93xx_adc.c
>>>
>>> +ARM/CIX SKY ARM ARCHITECTURE
>>> +M:   Peter Chen <peter.chen@cixtech.com>
>>> +M:   Fugang Duan <fugang.duan@cixtech.com>
>>> +R:   CIX Linux Kernel Upstream Group <cix-kernel-upstream@cixtech.com>
>>> +L:   linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
>>> +S:   Maintained
>>> +F:   Documentation/devicetree/bindings/arm/cix.yaml
>>> +F:   arch/arm64/boot/dts/cix/sky1-orion-o6.dts
>>> +F:   arch/arm64/boot/dts/cix/sky1.dtsi
>>
>> Instead:
>> arch/arm64/boot/dts/cix/
>>
>> or if you think there will be more different architectures coming from
>> cix, which you will not maintain, then useful would be a "sky" subdirectory.
>>
> Hi Krzysztof,
> 
> Thanks for your comment, CIX is Arm SoC based silicon design
> company, we may have different SoC style for middle end in future.
> So, for that SoC series, it may not name sky.

Your Kconfig says ARCH_CIX :/

Anyway, listing individual files is pointless, so if you are not going
to maintain entire arch, then create subdir. Otherwise why creating so
many entries? The biggest upstreamed SoC vendor (by number of SoCs and
boards has one entry.


Best regards,
Krzysztof

Re: [PATCH v4 6/6] MAINTAINERS: Add CIX SoC maintainer entry

[Peter Chen]

On 25-03-20 15:28:49, Kajetan Puchalski wrote:
> 
> > > > +ARM/CIX SKY ARM ARCHITECTURE
> > > > +M:   Peter Chen <peter.chen@cixtech.com>
> > > > +M:   Fugang Duan <fugang.duan@cixtech.com>
> > > > +R:   CIX Linux Kernel Upstream Group <cix-kernel-upstream@cixtech.com>
> > > > +L:   linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> > > > +S:   Maintained
> > > > +F:   Documentation/devicetree/bindings/arm/cix.yaml
> > > > +F:   arch/arm64/boot/dts/cix/sky1-orion-o6.dts
> > > > +F:   arch/arm64/boot/dts/cix/sky1.dtsi
> > >
> > > Instead:
> > > arch/arm64/boot/dts/cix/
> > >
> > > or if you think there will be more different architectures coming from
> > > cix, which you will not maintain, then useful would be a "sky" subdirectory.
> > >
> > Hi Krzysztof,
> >
> > Thanks for your comment, CIX is Arm SoC based silicon design
> > company, we may have different SoC style for middle end in future.
> > So, for that SoC series, it may not name sky.
> 
> I believe the idea is that the file should either say
> 
> +F:   arch/arm64/boot/dts/cix/
> 
> if the two of you intend to be maintainers for everything under cix/.
> You don't need to list every specific file.
> 
> Otherwise it should say
> 
> +F:   arch/arm64/boot/dts/cix/sky/
> 
> with its own subdirectory if you only intend to be maintaining the sky family.

Hi Kajetan & Krzysztof,

Thanks for your valuable comments. We prefer maintain the entire
CIX architecture under one entry, I will change maintain information
like below:

ARM/CIX SOC SUPPORT
M:	Peter Chen <peter.chen@cixtech.com>
M:	Fugang Duan <fugang.duan@cixtech.com>
R:	CIX Linux Kernel Upstream Group <cix-kernel-upstream@cixtech.com>
L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S:	Maintained
F:	Documentation/devicetree/bindings/arm/cix.yaml
F:	arch/arm64/boot/dts/cix/

-- 

Best regards,
Peter

Re: [PATCH v4 6/6] MAINTAINERS: Add CIX SoC maintainer entry

[Arnd Bergmann]

On Wed, Mar 5, 2025, at 06:38, Peter Chen wrote:
> +ARM/CIX SKY ARM ARCHITECTURE
> +M:     Peter Chen <peter.chen@cixtech.com>
> +M:     Fugang Duan <fugang.duan@cixtech.com>
> +R:     CIX Linux Kernel Upstream Group <cix-kernel-upstream@cixtech.com>
> +L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> +S:     Maintained
> +F:     Documentation/devicetree/bindings/arm/cix.yaml
> +F:     arch/arm64/boot/dts/cix/sky1-orion-o6.dts
> +F:     arch/arm64/boot/dts/cix/sky1.dtsi
> +

Looks good to me. You can also add a regex keyword entry such as

K:       \bcix\b

to match any filenames that have 'cix' as a whole word.

    Arnd

Re: [PATCH v4 5/6] arm64: dts: cix: add initial CIX P1(SKY1) dts support

[Marc Zyngier]

On Thu, 20 Mar 2025 09:57:13 +0000,
Peter Chen <peter.chen@cixtech.com> wrote:
> 
> On 25-03-20 09:36:37, Marc Zyngier wrote:
> > Peter Chen <peter.chen@cixtech.com> wrote:
> > >
> > > +     pmu-a520 {
> > > +             compatible = "arm,cortex-a520-pmu";
> > > +             interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition0>;
> > > +     };
> > > +
> > > +     pmu-a720 {
> > > +             compatible = "arm,cortex-a720-pmu";
> > > +             interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition1>;
> > > +     };
> > > +
> > > +     pmu-spe {
> > > +             compatible = "arm,statistical-profiling-extension-v1";
> > > +             interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW 0>;
> > > +     };
> > 
> > SPE should follow the same model as the PMU, as each CPU has its own
> > SPE implementation, exposing different micro-architectural details.
> > 
> 
> Hi Marc,
> 
> Thanks for your reply. But there is only one compatible string
> "statistical-profiling-extension-v1" at drivers/perf/arm_spe_pmu.c,
> how could differentiate pmu-spe-a720 and pmu-spe-a520, do I need
> to change arm_spe_pmu.c as well?

I don't think there is a need to have different compatible. The driver
can probe which CPU this is on, and work out the implemented
subfeatures from the PMSIDR_EL1 register. New compatible strings are
better avoided when there is a way to probe/discover the HW (and in
most cases, there is).

Note that this equally applies to TRBE, which also explicitly deals
with interrupt partitioning and yet only has a single compatible.
Please consider adding TRBE support when you repost this series.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH v4 5/6] arm64: dts: cix: add initial CIX P1(SKY1) dts support

[Peter Chen]

On 25-03-21 09:04:00, Marc Zyngier wrote:
> > On 25-03-20 09:36:37, Marc Zyngier wrote:
> > > Peter Chen <peter.chen@cixtech.com> wrote:
> > > >
> > > > +     pmu-a520 {
> > > > +             compatible = "arm,cortex-a520-pmu";
> > > > +             interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition0>;
> > > > +     };
> > > > +
> > > > +     pmu-a720 {
> > > > +             compatible = "arm,cortex-a720-pmu";
> > > > +             interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition1>;
> > > > +     };
> > > > +
> > > > +     pmu-spe {
> > > > +             compatible = "arm,statistical-profiling-extension-v1";
> > > > +             interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW 0>;
> > > > +     };
> > >
> > > SPE should follow the same model as the PMU, as each CPU has its own
> > > SPE implementation, exposing different micro-architectural details.
> > >
> >
> > Hi Marc,
> >
> > Thanks for your reply. But there is only one compatible string
> > "statistical-profiling-extension-v1" at drivers/perf/arm_spe_pmu.c,
> > how could differentiate pmu-spe-a720 and pmu-spe-a520, do I need
> > to change arm_spe_pmu.c as well?
> 
> I don't think there is a need to have different compatible. The driver
> can probe which CPU this is on, and work out the implemented
> subfeatures from the PMSIDR_EL1 register. New compatible strings are
> better avoided when there is a way to probe/discover the HW (and in
> most cases, there is).
> 
> Note that this equally applies to TRBE, which also explicitly deals
> with interrupt partitioning and yet only has a single compatible.
> Please consider adding TRBE support when you repost this series.
> 

Hi Marc,

Thanks for your comment, we need to discuss it internally. Since it
is very initial dts support for CIX sky1 SoC, I will delete pmu-spe
support at this time, and add better support for it when adding
more components next time.

-- 

Best regards,
Peter

Re: [PATCH v4 5/6] arm64: dts: cix: add initial CIX P1(SKY1) dts support

[Marc Zyngier]

On Fri, 21 Mar 2025 10:31:55 +0000,
Peter Chen <peter.chen@cixtech.com> wrote:
> 
> On 25-03-21 09:04:00, Marc Zyngier wrote:
> > > On 25-03-20 09:36:37, Marc Zyngier wrote:
> > > > Peter Chen <peter.chen@cixtech.com> wrote:
> > > > >
> > > > > +     pmu-a520 {
> > > > > +             compatible = "arm,cortex-a520-pmu";
> > > > > +             interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition0>;
> > > > > +     };
> > > > > +
> > > > > +     pmu-a720 {
> > > > > +             compatible = "arm,cortex-a720-pmu";
> > > > > +             interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition1>;
> > > > > +     };
> > > > > +
> > > > > +     pmu-spe {
> > > > > +             compatible = "arm,statistical-profiling-extension-v1";
> > > > > +             interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW 0>;
> > > > > +     };
> > > >
> > > > SPE should follow the same model as the PMU, as each CPU has its own
> > > > SPE implementation, exposing different micro-architectural details.
> > > >
> > >
> > > Hi Marc,
> > >
> > > Thanks for your reply. But there is only one compatible string
> > > "statistical-profiling-extension-v1" at drivers/perf/arm_spe_pmu.c,
> > > how could differentiate pmu-spe-a720 and pmu-spe-a520, do I need
> > > to change arm_spe_pmu.c as well?
> > 
> > I don't think there is a need to have different compatible. The driver
> > can probe which CPU this is on, and work out the implemented
> > subfeatures from the PMSIDR_EL1 register. New compatible strings are
> > better avoided when there is a way to probe/discover the HW (and in
> > most cases, there is).
> > 
> > Note that this equally applies to TRBE, which also explicitly deals
> > with interrupt partitioning and yet only has a single compatible.
> > Please consider adding TRBE support when you repost this series.
> > 
> 
> Hi Marc,
> 
> Thanks for your comment, we need to discuss it internally. Since it
> is very initial dts support for CIX sky1 SoC, I will delete pmu-spe
> support at this time, and add better support for it when adding
> more components next time.

And therefore making this machine even less useful than it already is?

<s> I think this is a great plan. </s>

	M.

-- 
Without deviation from the norm, progress is not possible.