[PATCH v2 6/7] arm64: dts: renesas: r9a09g047: Add TSU node

John Madieu
2025-02-27T13:14:35Z

Add TSU node along with thermal zones and keep it enabled in the SoC DTSI.

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
v1 -> v2: Fix IRQ names

arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 49 ++++++++++++++++++++++
1 file changed, 49 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index a6b83e057a40..93b57d7ad7b9 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -64,6 +64,7 @@ cpu0: cpu@0 {
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>;
+ #cooling-cells = <2>;
operating-points-v2 = <&cluster0_opp>;
};

@@ -74,6 +75,7 @@ cpu1: cpu@100 {
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>;
+ #cooling-cells = <2>;
operating-points-v2 = <&cluster0_opp>;
};

@@ -84,6 +86,7 @@ cpu2: cpu@200 {
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>;
+ #cooling-cells = <2>;
operating-points-v2 = <&cluster0_opp>;
};

@@ -94,6 +97,7 @@ cpu3: cpu@300 {
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>;
+ #cooling-cells = <2>;
operating-points-v2 = <&cluster0_opp>;
};

@@ -302,6 +306,20 @@ wdt3: watchdog@13000400 {
status = "disabled";
};

+ tsu: thermal@14002000 {
+ compatible = "renesas,r9a09g047-tsu";
+ reg = <0 0x14002000 0 0x1000>;
+ interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "adi", "adcmpi";
+ clocks = <&cpg CPG_MOD 0x10a>;
+ resets = <&cpg 0xf8>;
+ power-domains = <&cpg>;
+ #thermal-sensor-cells = <0>;
+ renesas,tsu-operating-mode = <0>;
+ renesas,tsu-calibration-sys = <&sys>;
+ };
+
i2c0: i2c@14400400 {
compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
reg = <0 0x14400400 0 0x400>;
@@ -502,6 +520,37 @@ gic: interrupt-controller@14900000 {
};
};

+ thermal-zones {
+ cpu-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&tsu>;
+
+ cooling-maps {
+ map0 {
+ trip = <&target>;
+ cooling-device = <&cpu0 0 3>, <&cpu1 0 3>,
+ <&cpu2 0 3>, <&cpu3 0 3>;
+ contribution = <1024>;
+ };
+ };
+
+ trips {
+ target: trip-point {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ sensor_crit: sensor-crit {
+ temperature = <120000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
--
2.25.1