From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, kvm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Cc: Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Zenghui Yu <yuzenghui@huawei.com>,
Mark Rutland <mark.rutland@arm.com>,
Fuad Tabba <tabba@google.com>
Subject: [PATCH v2 14/23] KVM: arm64: Use computed FGT masks to setup FGT registers
Date: Mon, 10 Mar 2025 12:24:56 +0000 [thread overview]
Message-ID: <20250310122505.2857610-15-maz@kernel.org> (raw)
In-Reply-To: <20250310122505.2857610-1-maz@kernel.org>
Flip the hyervisor FGT configuration over to the computed FGT
masks.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/kvm/hyp/include/hyp/switch.h | 45 +++++++++++++++++++++----
1 file changed, 38 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h
index c4e12516f6466..b3f02fa5ab79e 100644
--- a/arch/arm64/kvm/hyp/include/hyp/switch.h
+++ b/arch/arm64/kvm/hyp/include/hyp/switch.h
@@ -65,12 +65,41 @@ static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
}
}
+#define reg_to_fgt_masks(reg) \
+ ({ \
+ struct fgt_masks *m; \
+ switch(reg) { \
+ case HFGRTR_EL2: \
+ m = &hfgrtr_masks; \
+ break; \
+ case HFGWTR_EL2: \
+ m = &hfgwtr_masks; \
+ break; \
+ case HFGITR_EL2: \
+ m = &hfgitr_masks; \
+ break; \
+ case HDFGRTR_EL2: \
+ m = &hdfgrtr_masks; \
+ break; \
+ case HDFGWTR_EL2: \
+ m = &hdfgwtr_masks; \
+ break; \
+ case HAFGRTR_EL2: \
+ m = &hafgrtr_masks; \
+ break; \
+ default: \
+ BUILD_BUG_ON(1); \
+ } \
+ \
+ m; \
+ })
+
#define compute_clr_set(vcpu, reg, clr, set) \
do { \
- u64 hfg; \
- hfg = __vcpu_sys_reg(vcpu, reg) & ~__ ## reg ## _RES0; \
- set |= hfg & __ ## reg ## _MASK; \
- clr |= ~hfg & __ ## reg ## _nMASK; \
+ u64 hfg = __vcpu_sys_reg(vcpu, reg); \
+ struct fgt_masks *m = reg_to_fgt_masks(reg); \
+ set |= hfg & m->mask; \
+ clr |= ~hfg & m->nmask; \
} while(0)
#define reg_to_fgt_group_id(reg) \
@@ -101,12 +130,14 @@ static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
#define compute_undef_clr_set(vcpu, kvm, reg, clr, set) \
do { \
u64 hfg = kvm->arch.fgu[reg_to_fgt_group_id(reg)]; \
- set |= hfg & __ ## reg ## _MASK; \
- clr |= hfg & __ ## reg ## _nMASK; \
+ struct fgt_masks *m = reg_to_fgt_masks(reg); \
+ set |= hfg & m->mask; \
+ clr |= hfg & m->nmask; \
} while(0)
#define update_fgt_traps_cs(hctxt, vcpu, kvm, reg, clr, set) \
do { \
+ struct fgt_masks *m = reg_to_fgt_masks(reg); \
u64 c = clr, s = set; \
u64 val; \
\
@@ -116,7 +147,7 @@ static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
\
compute_undef_clr_set(vcpu, kvm, reg, c, s); \
\
- val = __ ## reg ## _nMASK; \
+ val = m->nmask; \
val |= s; \
val &= ~c; \
write_sysreg_s(val, SYS_ ## reg); \
--
2.39.2
next prev parent reply other threads:[~2025-03-10 13:15 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-10 12:24 [PATCH v2 00/23] KVM: arm64: Revamp Fine Grained Trap handling Marc Zyngier
2025-03-10 12:24 ` [PATCH v2 01/23] arm64: sysreg: Add ID_AA64ISAR1_EL1.LS64 encoding for FEAT_LS64WB Marc Zyngier
2025-03-10 12:24 ` [PATCH v2 02/23] arm64: sysreg: Update ID_AA64MMFR4_EL1 description Marc Zyngier
2025-03-10 12:24 ` [PATCH v2 03/23] arm64: sysreg: Add layout for HCR_EL2 Marc Zyngier
2025-03-10 12:24 ` [PATCH v2 04/23] arm64: Add syndrome information for trapped LD64B/ST64B{,V,V0} Marc Zyngier
2025-03-10 12:24 ` [PATCH v2 05/23] KVM: arm64: Handle trapping of FEAT_LS64* instructions Marc Zyngier
2025-03-10 12:24 ` [PATCH v2 06/23] KVM: arm64: Restrict ACCDATA_EL1 undef to FEAT_ST64_ACCDATA being disabled Marc Zyngier
2025-03-10 12:24 ` [PATCH v2 07/23] KVM: arm64: Don't treat HCRX_EL2 as a FGT register Marc Zyngier
2025-03-10 12:24 ` [PATCH v2 08/23] KVM: arm64: Plug FEAT_GCS handling Marc Zyngier
2025-03-10 12:24 ` [PATCH v2 09/23] KVM: arm64: Compute FGT masks from KVM's own FGT tables Marc Zyngier
2025-03-10 12:24 ` [PATCH v2 10/23] KVM: arm64: Add description of FGT bits leading to EC!=0x18 Marc Zyngier
2025-03-10 12:24 ` [PATCH v2 11/23] KVM: arm64: Use computed masks as sanitisers for FGT registers Marc Zyngier
2025-03-10 12:24 ` [PATCH v2 12/23] KVM: arm64: Unconditionally configure fine-grain traps Marc Zyngier
2025-03-10 12:24 ` [PATCH v2 13/23] KVM: arm64: Propagate FGT masks to the nVHE hypervisor Marc Zyngier
2025-03-10 12:24 ` Marc Zyngier [this message]
2025-03-10 12:24 ` [PATCH v2 15/23] KVM: arm64: Remove most hand-crafted masks for FGT registers Marc Zyngier
2025-03-10 12:24 ` [PATCH v2 16/23] KVM: arm64: Use KVM-specific HCRX_EL2 RES0 mask Marc Zyngier
2025-03-10 12:24 ` [PATCH v2 17/23] KVM: arm64: Handle PSB CSYNC traps Marc Zyngier
2025-03-10 12:25 ` [PATCH v2 18/23] KVM: arm64: Switch to table-driven FGU configuration Marc Zyngier
2025-03-10 12:25 ` [PATCH v2 19/23] KVM: arm64: Validate FGT register descriptions against RES0 masks Marc Zyngier
2025-03-10 12:25 ` [PATCH v2 20/23] KVM: arm64: Use FGT feature maps to drive RES0 bits Marc Zyngier
2025-03-10 12:25 ` [PATCH v2 21/23] KVM: arm64: Allow kvm_has_feat() to take variable arguments Marc Zyngier
2025-03-10 12:25 ` [PATCH v2 22/23] KVM: arm64: Use HCRX_EL2 feature map to drive fixed-value bits Marc Zyngier
2025-03-10 12:25 ` [PATCH v2 23/23] KVM: arm64: Use HCR_EL2 " Marc Zyngier
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