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[209.17.68.221]) by smtp.gmail.com with UTF8SMTPSA id 98e67ed59e1d1-300fe40c28dsm706225a91.33.2025.03.10.14.07.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Mar 2025 14:07:48 -0700 (PDT) Date: Tue, 11 Mar 2025 06:07:46 +0900 From: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= To: Siddharth Vadapalli Cc: lpieralisi@kernel.org, vigneshr@ti.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, bhelgaas@google.com, rogerq@kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, stable@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, srk@ti.com Subject: Re: [PATCH] PCI: j721e: Fix the value of linkdown_irq_regfield for J784S4 Message-ID: <20250310210746.GA2377483@rocinante> References: <20250305132018.2260771-1-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250305132018.2260771-1-s-vadapalli@ti.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250310_140750_937011_8AFB57C1 X-CRM114-Status: UNSURE ( 9.78 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello, > Hence, set 'linkdown_irq_regfield' to the macro 'J7200_LINK_DOWN' which > expands to BIT(10) and was first defined for the J7200 SoC. Other SoCs > already reuse this macro since it accurately represents the link-state > field in their respective "PCIE_INTD_ENABLE_REG_SYS_2" register. Can you confirm for me that the following use the correct macro? 333-static const struct j721e_pcie_data j721e_pcie_rc_data = { 337: .linkdown_irq_regfield = LINK_DOWN, 341-static const struct j721e_pcie_data j721e_pcie_ep_data = { 343: .linkdown_irq_regfield = LINK_DOWN, 347-static const struct j721e_pcie_data j7200_pcie_rc_data = { 350: .linkdown_irq_regfield = J7200_LINK_DOWN, 362-static const struct j721e_pcie_data am64_pcie_rc_data = { 364: .linkdown_irq_regfield = J7200_LINK_DOWN, 369-static const struct j721e_pcie_data am64_pcie_ep_data = { 371: .linkdown_irq_regfield = J7200_LINK_DOWN, 375-static const struct j721e_pcie_data j784s4_pcie_rc_data = { 379: .linkdown_irq_regfield = LINK_DOWN, 383-static const struct j721e_pcie_data j784s4_pcie_ep_data = { 385: .linkdown_irq_regfield = LINK_DOWN, 389-static const struct j721e_pcie_data j722s_pcie_rc_data = { 391: .linkdown_irq_regfield = J7200_LINK_DOWN, I am asking as some use LINK_DOWN, so I wanted to make sure. Tht said, the following has no .linkdown_irq_regfield property set: 355-static const struct j721e_pcie_data j7200_pcie_ep_data = { 356- .mode = PCI_MODE_EP, 357- .quirk_detect_quiet_flag = true, 358- .quirk_disable_flr = true, 359- .max_lanes = 2, 360-}; Would this be a problem? Or is this as expected? Thank you! Krzysztof