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Wed, 19 Mar 2025 10:08:44 -0700 (PDT) Received: from localhost ([2a02:8308:a00c:e200::59a5]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-395c83b748bsm21797789f8f.39.2025.03.19.10.08.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Mar 2025 10:08:44 -0700 (PDT) Date: Wed, 19 Mar 2025 18:08:43 +0100 From: Andrew Jones To: =?utf-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= Cc: Paul Walmsley , Palmer Dabbelt , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Himanshu Chauhan , Anup Patel , Xu Lu , Atish Patra Subject: Re: [PATCH v3 2/4] riscv: add support for SBI Supervisor Software Events extension Message-ID: <20250319-46b625cf8b771616d4c7c053@orel> References: <20241206163102.843505-1-cleger@rivosinc.com> <20241206163102.843505-3-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20241206163102.843505-3-cleger@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250319_100846_354593_9FFCC142 X-CRM114-Status: GOOD ( 17.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Dec 06, 2024 at 05:30:58PM +0100, Clément Léger wrote: ... > +int arch_sse_init_event(struct sse_event_arch_data *arch_evt, u32 evt_id, int cpu) > +{ > + void *stack; > + > + arch_evt->evt_id = evt_id; > + stack = sse_stack_alloc(cpu, SSE_STACK_SIZE); > + if (!stack) > + return -ENOMEM; > + > + arch_evt->stack = stack + SSE_STACK_SIZE; > + > + if (sse_init_scs(cpu, arch_evt)) > + goto free_stack; > + > + if (is_kernel_percpu_address((unsigned long)&arch_evt->interrupted)) { > + arch_evt->interrupted_state_phys = > + per_cpu_ptr_to_phys(&arch_evt->interrupted); > + } else { > + arch_evt->interrupted_state_phys = > + virt_to_phys(&arch_evt->interrupted); > + } > + > + return 0; Hi Clément, Testing SSE support with tools/testing/selftests/kvm/riscv/sbi_pmu_test led to an opensbi sbi_trap_error because the output_phys_lo address passed to sbi_sse_read_attrs() wasn't a physical address. The reason is that is_kernel_percpu_address() can only be used on static percpu addresses, but local sse events get their percpu addresses with alloc_percpu(), so is_kernel_percpu_address() was returning false even for local events. I made the following changes to get things working. Thanks, drew diff --git a/arch/riscv/kernel/sse.c b/arch/riscv/kernel/sse.c index b48ae69dad8d..f46893946086 100644 --- a/arch/riscv/kernel/sse.c +++ b/arch/riscv/kernel/sse.c @@ -100,12 +100,12 @@ int arch_sse_init_event(struct sse_event_arch_data *arch_evt, u32 evt_id, int cp if (sse_init_scs(cpu, arch_evt)) goto free_stack; - if (is_kernel_percpu_address((unsigned long)&arch_evt->interrupted)) { + if (sse_event_is_global(evt_id)) { arch_evt->interrupted_state_phys = - per_cpu_ptr_to_phys(&arch_evt->interrupted); + virt_to_phys(&arch_evt->interrupted); } else { arch_evt->interrupted_state_phys = - virt_to_phys(&arch_evt->interrupted); + per_cpu_ptr_to_phys(&arch_evt->interrupted); } return 0; diff --git a/drivers/firmware/riscv/riscv_sse.c b/drivers/firmware/riscv/riscv_sse.c index 511db9ad7a9e..fef375046f75 100644 --- a/drivers/firmware/riscv/riscv_sse.c +++ b/drivers/firmware/riscv/riscv_sse.c @@ -62,11 +62,6 @@ void sse_handle_event(struct sse_event_arch_data *arch_event, ret); } -static bool sse_event_is_global(u32 evt) -{ - return !!(evt & SBI_SSE_EVENT_GLOBAL); -} - static struct sse_event *sse_event_get(u32 evt) { diff --git a/include/linux/riscv_sse.h b/include/linux/riscv_sse.h index 16700677f1e8..06b757b036b0 100644 --- a/include/linux/riscv_sse.h +++ b/include/linux/riscv_sse.h @@ -8,6 +8,7 @@ #include #include +#include struct sse_event; struct pt_regs; @@ -16,6 +17,11 @@ struct ghes; typedef int (sse_event_handler)(u32 event_num, void *arg, struct pt_regs *regs); +static inline bool sse_event_is_global(u32 evt) +{ + return !!(evt & SBI_SSE_EVENT_GLOBAL); +} + #ifdef CONFIG_RISCV_SSE struct sse_event *sse_event_register(u32 event_num, u32 priority,