From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 286BAC36001 for ; Fri, 21 Mar 2025 22:34:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=xK9Qm6/xTRU/x1rTDkdKbqtKlovHDKLBQ5YH7f1Z2IU=; b=apeNzH8dR+ww0I9tjBADh1twwH G6JKOldZzmYHghDnxDGk/A/RCGutsRDdEFHZo9dPtC0DNP3R771h6uFGNo1NKD4Rst10TDUdAeJRe zdUqvipuPjw37mZvfrm/9E1CWD+tK3RTLlRsb2bI1gqXD90RLr97DVjydTBuc96nhZra28eggnVfG MdLkt2kazuXGFoop6yqE12mvWiA/m6R3rnoVo4xMT3fYOe4A0RoBW6cRrYtajtixCgtgNUahCdvZG /0YqkU/JYBWgIFv+qrEaImXmHU3Osg0e6BD3UFeaT9C+fGMVxyZUeonmCOZBIArkkyf3XzWwo27Jd KPACL1nw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tvkwH-0000000GUrQ-3nDN; Fri, 21 Mar 2025 22:34:05 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tvkub-0000000GUkO-2n4n for linux-arm-kernel@lists.infradead.org; Fri, 21 Mar 2025 22:32:22 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 0634B5C6CD2; Fri, 21 Mar 2025 22:30:04 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AF287C4CEE3; Fri, 21 Mar 2025 22:32:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1742596340; bh=UzLNiQ5Wvn9rKAUANHTjv00uwdzSTTzEUgki6vN47rE=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=oDTGb5abR2KDLvK+8ds6skrd6W1UtIQ/hokDvvG5OHnrB5GRHzihjplyW9Dr6mGpr tEFr6YgI0z7nOq6Kx1wY3wBBfL5doWPuT5YcTSDhhAUucE8NvOQMIA0N9ya7UAm4fU Pb3O3ag7abVK/wR4RA8RqfmEbPRIEgpRBdh7dyJtt9VAYOPHFmnSzMGyM2u6cZusYc mWDW9sq91fVXSWYLo2rhrIdcTxgPAzhU0SAyO+t38GtP/8FppDTrHGkR3eLlvoEzoD 3mwDR9Fy85FsneXge0VU8VtdxCaPsGl6+nMjgHrPGVaYbRTWumxuYDjRLg6I5kWrhN Aom54EoL5NaEQ== Date: Fri, 21 Mar 2025 22:32:15 +0000 From: Conor Dooley To: Jonathan Cameron Cc: linux-cxl@vger.kernel.org, linux-arm-kernel@lists.infradead.org, james.morse@arm.com, Yicong Yang , linux-acpi@vger.kernel.org, linux-arch@vger.kernel.org, linuxarm@huawei.com, Yushan Wang , linux-mm@kvack.org, gregkh@linuxfoundation.org, Lorenzo Pieralisi , Mark Rutland , Catalin Marinas , Will Deacon , Dan Williams Subject: Re: [RFC PATCH 0/6] Cache coherency management subsystem Message-ID: <20250321-failing-squatted-37a88909bde2@spud> References: <20250320174118.39173-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="eWBfxz5cC1rG3K4K" Content-Disposition: inline In-Reply-To: <20250320174118.39173-1-Jonathan.Cameron@huawei.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250321_153221_795062_C07BBB90 X-CRM114-Status: GOOD ( 30.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --eWBfxz5cC1rG3K4K Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Mar 20, 2025 at 05:41:12PM +0000, Jonathan Cameron wrote: > Note that I've only a vague idea of who will care about this > so please do +CC others as needed. >=20 > On x86 there is the much loved WBINVD instruction that causes a write back > and invalidate of all caches in the system. It is expensive but it is > necessary in a few corner cases. These are cases where the contents of > Physical Memory may change without any writes from the host. Whilst there > are a few reasons this might happen, the one I care about here is when > we are adding or removing mappings on CXL. So typically going from > there being actual memory at a host Physical Address to nothing there > (reads as zero, writes dropped) or visa-versa. That involves the > reprogramming of address decoders (HDM Decoders); in the near future > it may also include the device offering dynamic capacity extents. The > thing that makes it very hard to handle with CPU flushes is that the > instructions are normally VA based and not guaranteed to reach beyond > the Point of Coherence or similar. You might be able to (ab)use > various flush operations intended to ensure persistence memory but > in general they don't work either. >=20 > So on other architectures such as ARM64 we have no instruction similar to > WBINVD but we may have device interfaces in the system that provide a way > to ensure a PA range undergoes the write back and invalidate action. This > RFC is to find a way to support those cache maintenance device interfaces. > The ones I know about are much more flexible than WBINVD, allowing > invalidation of particular PA ranges, or a much richer set of flush types > (not supported yet as not needed for upstream use cases). >=20 > To illustrate how a solution might work, I've taken both a HiSilicon > design (slight quirk as registers overlap with existing PMU driver) > and more controversially a firmware interface proposal from ARM > (wrapped up in made up ACPI) that was dropped from the released spec > but for which the alpha spec is still available. >=20 > Why drivers/cache? > - Mainly because it exists and smells like a reasonable place. > - Conor, you are maintainer for this currently do you mind us putting this > stuff in there? drivers/cache was just something to put the cache controller drivers we have on RISC-V that implement the various arch_dma*() callbacks in non-standard ways that made more sense than drivers/soc/ since the controllers are IP provided by CPU vendors. There's only two drivers here now, but I am aware of another two non-standard CMO mechanisms if the silicon with them so there'll likely be more in the future :) I'm only really maintainer of it to avoid it being another thing for Palmer to look after :) I've only skimmed this for now, but I think it is reasonable to put them here. Maybe my skim is showing, but it would not surprise me to see a driver providing both non-standard arch_dma*() callbacks as well as dealing with CXL mappings via this new class on RISC-V in the future.. Either way, I think it'd probably be a good idea to add ?you? as a co-maintainer if the directory is going to be used for your proposed interface/drivers, for what I hope is an obvious reason! --eWBfxz5cC1rG3K4K Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZ93o7wAKCRB4tDGHoIJi 0qSeAQCDYiitjFXwNZKbbEFUkUXhfIYYuu03HmpuYwBJ0POhpgEAmO04672uw1BL hytebcnudQFH53/qJg2okVO4XHPPLAw= =cvbz -----END PGP SIGNATURE----- --eWBfxz5cC1rG3K4K--