From: Bjorn Helgaas <helgaas@kernel.org>
To: Mike Looijmans <mike.looijmans@topic.nl>
Cc: "Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
linux-pci@vger.kernel.org, "Bjorn Helgaas" <bhelgaas@google.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Michal Simek" <michal.simek@amd.com>,
"Rob Herring" <robh@kernel.org>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] pcie-xilinx: Support reset GPIO and wait for link-up status
Date: Mon, 24 Mar 2025 11:08:38 -0500 [thread overview]
Message-ID: <20250324160838.GA1251294@bhelgaas> (raw)
In-Reply-To: <0e7637a0-8b8f-4aa7-be46-1e7b8ac07a45@topic.nl>
On Mon, Mar 24, 2025 at 04:46:55PM +0100, Mike Looijmans wrote:
> On 24-03-2025 08:49, Manivannan Sadhasivam wrote:
> > On Fri, Mar 14, 2025 at 03:59:02PM +0100, Mike Looijmans wrote:
> > > Support providing the PERST reset signal through a devicetree binding.
Use "PERST#" to include the polarity and match the spec usage.
> > > As the PCIe spec mentions about 120 ms time to establish a link, we'll
> > > allow up to 200ms before giving up.
> > >
> > This should be a separate change/patch.
>
> Indeed, this is a separate issue, I'll split it in two parts.
And please include a specific spec reference, e.g., "PCIe r6.0, sec
x.y.z".
prev parent reply other threads:[~2025-03-24 16:10 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1b153bce-a66a-45ee-a5c6-963ea6fb1c82.949ef384-8293-46b8-903f-40a477c056ae.c4ab15e9-561e-402d-bf39-9e852485e4fa@emailsignatures365.codetwo.com>
2025-03-14 14:59 ` [PATCH] pcie-xilinx: Support reset GPIO and wait for link-up status Mike Looijmans
2025-03-24 7:49 ` Manivannan Sadhasivam
2025-03-24 15:46 ` Mike Looijmans
2025-03-24 16:08 ` Bjorn Helgaas [this message]
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