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x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: multipart/signed; boundary="Sig_/=NAIwEwO9lbdwvsUnTeQSey"; protocol="application/pgp-signature"; micalg=pgp-sha512 X-Last-TLS-Session-Version: TLSv1.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250329_141616_666585_B03BC37D X-CRM114-Status: GOOD ( 34.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --Sig_/=NAIwEwO9lbdwvsUnTeQSey Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Hi Rob, > On Fri, Mar 28, 2025 at 02:35:41PM +0100, Lukasz Majewski wrote: > > This patch provides description of the MTIP L2 switch available in > > some NXP's SOCs - e.g. imx287. > >=20 > > Signed-off-by: Lukasz Majewski > > --- > > Changes for v2: > > - Rename the file to match exactly the compatible > > (nxp,imx287-mtip-switch) > > --- > > .../bindings/net/nxp,imx287-mtip-switch.yaml | 165 > > ++++++++++++++++++ 1 file changed, 165 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/net/nxp,imx287-mtip-switch.yaml > >=20 > > diff --git > > a/Documentation/devicetree/bindings/net/nxp,imx287-mtip-switch.yaml > > b/Documentation/devicetree/bindings/net/nxp,imx287-mtip-switch.yaml > > new file mode 100644 index 000000000000..a3e0fe7783ec --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/net/nxp,imx287-mtip-switch.yaml > > @@ -0,0 +1,165 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR > > BSD-2-Clause) +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/net/nxp,imx287-mtip-switch.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: NXP SoC Ethernet Switch Controller (L2 MoreThanIP switch) > > + > > +maintainers: > > + - Lukasz Majewski > > + > > +description: > > + The 2-port switch ethernet subsystem provides ethernet packet > > (L2) > > + communication and can be configured as an ethernet switch. It > > provides the > > + reduced media independent interface (RMII), the management data > > input > > + output (MDIO) for physical layer device (PHY) management. > > + > > +properties: > > + compatible: > > + const: nxp,imx287-mtip--switch > > + > > + reg: > > + maxItems: 1 > > + description: > > + The physical base address and size of the MTIP L2 SW module > > IO range + > > + phy-supply: > > + description: > > + Regulator that powers Ethernet PHYs. > > + > > + clocks: > > + items: > > + - description: Register accessing clock > > + - description: Bus access clock > > + - description: Output clock for external device - e.g. PHY > > source clock > > + - description: IEEE1588 timer clock > > + > > + clock-names: > > + items: > > + - const: ipg > > + - const: ahb > > + - const: enet_out > > + - const: ptp > > + > > + interrupts: > > + items: > > + - description: Switch interrupt > > + - description: ENET0 interrupt > > + - description: ENET1 interrupt > > + > > + pinctrl-names: true > > + > > + ethernet-ports: > > + type: object > > + additionalProperties: false > > + > > + properties: > > + '#address-cells': > > + const: 1 > > + '#size-cells': > > + const: 0 > > + > > + patternProperties: > > + "^port@[0-9]+$": > > + type: object > > + description: MTIP L2 switch external ports > > + > > + $ref: ethernet-controller.yaml# > > + unevaluatedProperties: false > > + > > + properties: > > + reg: > > + items: > > + - enum: [1, 2] > > + description: MTIP L2 switch port number > > + > > + label: > > + description: Label associated with this port > > + > > + required: > > + - reg > > + - label > > + - phy-mode > > + - phy-handle > > + > > + mdio: > > + type: object > > + $ref: mdio.yaml# > > + unevaluatedProperties: false > > + description: > > + Specifies the mdio bus in the switch, used as a container > > for phy nodes. + > > +required: > > + - compatible > > + - reg > > + - clocks > > + - clock-names > > + - interrupts > > + - mdio > > + - ethernet-ports > > + - '#address-cells' > > + - '#size-cells' > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include > > + switch@800f0000 { > > + compatible =3D "nxp,imx287-mtip-switch"; > > + reg =3D <0x800f0000 0x20000>; > > + pinctrl-names =3D "default"; > > + pinctrl-0 =3D <&mac0_pins_a>, <&mac1_pins_a>; > > + phy-supply =3D <®_fec_3v3>; > > + interrupts =3D <100>, <101>, <102>; > > + clocks =3D <&clks 57>, <&clks 57>, <&clks 64>, <&clks 35>; > > + clock-names =3D "ipg", "ahb", "enet_out", "ptp"; > > + status =3D "okay"; > > + > > + ethernet-ports { > > + #address-cells =3D <1>; > > + #size-cells =3D <0>; > > + > > + mtip_port1: port@1 { > > + reg =3D <1>; > > + label =3D "lan0"; > > + local-mac-address =3D [ 00 00 00 00 00 00 ]; > > + phy-mode =3D "rmii"; > > + phy-handle =3D <ðphy0>; > > + }; > > + > > + mtip_port2: port@2 { > > + reg =3D <2>; > > + label =3D "lan1"; > > + local-mac-address =3D [ 00 00 00 00 00 00 ]; > > + phy-mode =3D "rmii"; > > + phy-handle =3D <ðphy1>; > > + }; > > + }; > > + > > + mdio_sw: mdio { > > + #address-cells =3D <1>; > > + #size-cells =3D <0>; > > + > > + reset-gpios =3D <&gpio2 13 0>; > > + reset-delay-us =3D <25000>; > > + reset-post-delay-us =3D <10000>; > > + > > + ethphy0: ethernet-phy@0 { > > + reg =3D <0>; > > + smsc,disable-energy-detect; =20 >=20 > With a custom property, you should have a specific compatible. I could add: compatible =3D "ethernet-phy-id0007.c0f0","ethernet-phy-ieee802.3-c22"; but it would not make things either clearer nor simpler. I will just remove this property. >=20 > > + /* Both PHYs (i.e. 0,1) have the same, > > single GPIO, */ > > + /* line to handle both, their interrupts > > (AND'ed) */ > > + interrupt-parent =3D <&gpio4>; > > + interrupts =3D <13 IRQ_TYPE_EDGE_FALLING>; =20 >=20 > The error report is because the examples have to guess the number of=20 > provider interrupt cells and only 1 guess is supported. It guessed 1=20 > from above. >=20 > In any case, unless the phys are built-in and fixed, they are out of=20 > scope of this binding. So perhaps drop the interrupts and smsc > property. Ok, I will remove them. >=20 > Rob Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Erika Unter HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de --Sig_/=NAIwEwO9lbdwvsUnTeQSey Content-Type: application/pgp-signature Content-Description: OpenPGP digital signature -----BEGIN PGP SIGNATURE----- iQEzBAEBCgAdFiEEgAyFJ+N6uu6+XupJAR8vZIA0zr0FAmfoYxQACgkQAR8vZIA0 zr0/EwgAx/s1HQ3OV9LuT1M2dDnFpa7Ck55tkTu6Id5VMV6ygsaFR4D7/UpS++xQ g+YhbzhnrVE1ri5GYyfwYhCCT8XFesFyhbpqJydqNbAGHNnY7if9if3lxni0/Pz2 wNeZOcdAGmem3uhT1yK7pWxHgIIYcCJ0Roq5iu9Urdjr0VpuAhhlXOexcKqfyzXk MMnBPBo3XGqk6DUh3ncY02wE6hDh8y5DZZRk5PgzvyCdUVvnX8ekpnklIk3VKKVh te7QIf3ECkgKqzQYFUq4mGnOzcH7ODz0kf0rt/DCdKDyIJXqqMzM+1cT7TZLcTE5 TU5jL4DS18I0ufbg1ZbAb2xrlbk1WQ== =u478 -----END PGP SIGNATURE----- --Sig_/=NAIwEwO9lbdwvsUnTeQSey--