From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 22013C3600C for ; Thu, 3 Apr 2025 19:57:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=lU2eOhb2hTb28P4aQDlLcOfsaRn+842r9CtkXTf6JGs=; b=ztzYwoInk1UVvd4RL6VPZnJUst vWhbDdbkLxM7eEQSLkpPvRaaAHs+JvSYDT7EJdzJkXYWLt6C8QOEvhFfNtA9QqjNxRh/rmSwaI3N9 lzT1MMFlxqC9AKBP4asgICLTxh/LLahqmAJ+xVX47u1Z9FEwISANGuA6jRFqle9Qr8pOUF2UeHJBg dKBcdZQTZHT1AEy7rakMI5K+FsWTafz85lshCobLOA/tiZZ2bkYujSgRW4Fm/jKd1H64XpQIQcuPi kwxeqhiMeQJhnIfCmqVjo3cWl/RhndMywvl52QiWf9dY5dea/kT6ndCNorAuKDHuJl9IkIT9WKc65 oGzL+m6A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.1 #2 (Red Hat Linux)) id 1u0Qgb-00000009r1I-0vVU; Thu, 03 Apr 2025 19:57:13 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.98.1 #2 (Red Hat Linux)) id 1u0Q6y-00000009ifV-3lHq; Thu, 03 Apr 2025 19:20:26 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 641935C6C59; Thu, 3 Apr 2025 19:18:07 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id BB3E3C4CEE3; Thu, 3 Apr 2025 19:20:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743708024; bh=P5c0h/WnpNP5G0dQIP0NgDWmaNf/0VFioha6pC1xPm8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kwP8PIjWELPxtpYG4jItc1Xp7nFDwx9h9FhGkYTjHkxrZByb2CFBudFg9e4QLMyFY NSaMkAVVZLXNQ9qd0RRLY3ccPl4vx2BV0NnmHQ5ITWdnD5vTOriJ7MUtZ5XTGtdMIM DXH9mKigEDVr+yUHQss6nzEG+7lpW3yKe0vc4oHs0yAnkJFrD2d43b49+/OnX4sjhi wqReEHuuaHVpSh5xJQ6N8AHfhwnpSf9sIxFHOUDR6nFcy5plT3FDxR6FT8NeN3SpPk Lt6B2Kp8eVSaSH8YmuXA68+FrQJ7PpYDeXh64rp13Sim34DUoH9zgsrFJX8j/cos6O shx0h0eIoeiVA== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: AngeloGioacchino Del Regno , CK Hu , Chun-Kuang Hu , Sasha Levin , p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, matthias.bgg@gmail.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH AUTOSEL 5.15 09/12] drm/mediatek: mtk_dpi: Explicitly manage TVD clock in power on/off Date: Thu, 3 Apr 2025 15:19:58 -0400 Message-Id: <20250403192001.2682149-9-sashal@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250403192001.2682149-1-sashal@kernel.org> References: <20250403192001.2682149-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 5.15.179 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250403_122025_040013_B8193692 X-CRM114-Status: GOOD ( 11.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: AngeloGioacchino Del Regno [ Upstream commit 473c33f5ce651365468503c76f33158aaa1c7dd2 ] In preparation for adding support for MT8195's HDMI reserved DPI, add calls to clk_prepare_enable() / clk_disable_unprepare() for the TVD clock: in this particular case, the aforementioned clock is not (and cannot be) parented to neither pixel or engine clocks hence it won't get enabled automatically by the clock framework. Please note that on all of the currently supported MediaTek platforms, the TVD clock is always a parent of either pixel or engine clocks, and this means that the common clock framework is already enabling this clock before the children. On such platforms, this commit will only increase the refcount of the TVD clock without any functional change. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno Link: https://patchwork.kernel.org/project/dri-devel/patch/20250217154836.108895-10-angelogioacchino.delregno@collabora.com/ Signed-off-by: Chun-Kuang Hu Signed-off-by: Sasha Levin --- drivers/gpu/drm/mediatek/mtk_dpi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 94c6bd3b00823..9518672dc21b3 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -389,6 +389,7 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi) mtk_dpi_disable(dpi); clk_disable_unprepare(dpi->pixel_clk); + clk_disable_unprepare(dpi->tvd_clk); clk_disable_unprepare(dpi->engine_clk); } @@ -405,6 +406,12 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) goto err_refcount; } + ret = clk_prepare_enable(dpi->tvd_clk); + if (ret) { + dev_err(dpi->dev, "Failed to enable tvd pll: %d\n", ret); + goto err_engine; + } + ret = clk_prepare_enable(dpi->pixel_clk); if (ret) { dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret); @@ -414,6 +421,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) return 0; err_pixel: + clk_disable_unprepare(dpi->tvd_clk); +err_engine: clk_disable_unprepare(dpi->engine_clk); err_refcount: dpi->refcount--; -- 2.39.5