From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A4706C3601E for ; Fri, 4 Apr 2025 09:51:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:CC:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=qDJ3Mb7YyqUASiYdnt4nl93Qyi0Oahcb6qeEI0SSTA0=; b=nFYXwfUyaQ8RmzuXAI2yOudkmz WkfWS7j80OyXGAOJ0fnSOX+VcSradWjX9FDY/bidJnPR4GXh4Nq4qvkH6xKMHjIUOyz7FuQOIC9MI n7zNbu0+0xRZyT4w6JsgpuIPI5kdZRJ+X0g7qK+tqlUwPcqrNADEFM+7Pj/JwyH5HWQIjmsDLX4BI Dmt+Kx3HGIy3X1czGLWFSEreDkD2BC1QkVXODRTdjCemZRzzOLXkXJzO7iGPgt6Kzqvu76mwNuGyI ALwdb0WwY4ZQ2sjyFsZ1ARwchzphf9Fmv4SqSB/1j7K+HfsbkvNmRCp12Xj9t/VlXcLqny29ALVvt LqAOJs0Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.1 #2 (Red Hat Linux)) id 1u0dhf-0000000BKUZ-37QH; Fri, 04 Apr 2025 09:51:11 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.98.1 #2 (Red Hat Linux)) id 1u0dam-0000000BJDS-09mV; Fri, 04 Apr 2025 09:44:06 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1743759843; x=1775295843; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=/1xoPsKQlQBWMpLcgEjKZ/hJOcJIL0rM7P/QyChG6kU=; b=MlzXWpqJ7mWNZk8vxaj24vZmpxXGpN5gd91Wynlbn/v32f283FGuXyXp NcnD1jU3ABkTE44yq+ZPaab3j4tDylCb37ZrvcCq4d1GQ40pnIvQg3byd MjYqUXxk0FGsMbUKg5v4N63yLO7Gk7vbZiutaOGY5+pUZJjzOD+S59ejB uC+8rWbotewgXRGiLxNDvs/ZV+MJ/ZEux7MT09I9vBTfmdcNAFbCcdzIx ji5F8cMY0tztrlVRoVsnVJ+li6e9+ss51SELSYQtcMFpzRLxlfAQ4yErS lmNk11IIv8atNt+aa6G0e89iKj8d7vMC+PxKJRYO5MfjHTQ0QfIdQblA7 Q==; X-CSE-ConnectionGUID: CCbOwbOjQ2SseDv2d8Zv6w== X-CSE-MsgGUID: TTSMcQbYQG2UnIfQGa0ggw== X-IronPort-AV: E=Sophos;i="6.15,187,1739862000"; d="scan'208";a="39641646" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 04 Apr 2025 02:44:01 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Fri, 4 Apr 2025 02:43:37 -0700 Received: from DEN-DL-M70577 (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Fri, 4 Apr 2025 02:43:28 -0700 Date: Fri, 4 Apr 2025 09:43:28 +0000 From: Daniel Machon To: "Rob Herring (Arm)" CC: Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , "Rafael J. Wysocki" , Viresh Kumar , Matthias Brugger , AngeloGioacchino Del Regno , Vincenzo Frascino , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , "Bjorn Andersson" , Konrad Dybcio , Thomas Bogendoerfer , Viresh Kumar , Nishanth Menon , Stephen Boyd , , Conor Dooley , Nicolas Ferre , "Claudiu Beznea" , Steen Hegelund , , Shawn Guo , Sascha Hauer , "Pengutronix Kernel Team" , Fabio Estevam , Heiko Stuebner , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Geert Uytterhoeven , Magnus Damm , , , , , , , , , , , , Subject: Re: [PATCH 04/19] arm64: dts: microchip: sparx5: Fix CPU node "enable-method" property dependencies Message-ID: <20250404094328.cojaf5cxrotnetln@DEN-DL-M70577> References: <20250403-dt-cpu-schema-v1-0-076be7171a85@kernel.org> <20250403-dt-cpu-schema-v1-4-076be7171a85@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20250403-dt-cpu-schema-v1-4-076be7171a85@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250404_024404_316779_9D26B064 X-CRM114-Status: GOOD ( 12.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org > The "spin-table" enable-method requires "cpu-release-addr" property, > so add a dummy entry. It is assumed the bootloader will fill in the > correct values. > > Signed-off-by: Rob Herring (Arm) > --- > arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi > index 32bb76b3202a..83bf5c81b5f7 100644 > --- a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi > +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi > @@ -12,10 +12,12 @@ &psci { > > &cpu0 { > enable-method = "spin-table"; > + cpu-release-addr = /bits/ 64 <0>; > }; > > &cpu1 { > enable-method = "spin-table"; > + cpu-release-addr = /bits/ 64 <0>; > }; > > &uart0 { > > -- > 2.47.2 > Reviewed-by: Daniel Machon Tested-by: Daniel Machon