From: Will Deacon <will@kernel.org>
To: Atish Patra <atishp@rivosinc.com>
Cc: "Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Anup Patel" <anup@brainfault.org>,
"Atish Patra" <atishp@atishpatra.org>,
"Mark Rutland" <mark.rutland@arm.com>,
"Peter Zijlstra" <peterz@infradead.org>,
"Ingo Molnar" <mingo@redhat.com>,
"Arnaldo Carvalho de Melo" <acme@kernel.org>,
"Namhyung Kim" <namhyung@kernel.org>,
"Alexander Shishkin" <alexander.shishkin@linux.intel.com>,
"Jiri Olsa" <jolsa@kernel.org>, "Ian Rogers" <irogers@google.com>,
"Adrian Hunter" <adrian.hunter@intel.com>,
weilin.wang@intel.com, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, "Conor Dooley" <conor@kernel.org>,
devicetree@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-perf-users@vger.kernel.org,
"Clément Léger" <cleger@rivosinc.com>
Subject: Re: [PATCH v5 11/21] RISC-V: perf: Restructure the SBI PMU code
Date: Fri, 4 Apr 2025 14:49:38 +0100 [thread overview]
Message-ID: <20250404134937.GA29394@willie-the-truck> (raw)
In-Reply-To: <20250327-counter_delegation-v5-11-1ee538468d1b@rivosinc.com>
On Thu, Mar 27, 2025 at 12:35:52PM -0700, Atish Patra wrote:
> With Ssccfg/Smcdeleg, we no longer need SBI PMU extension to program/
> access hpmcounter/events. However, we do need it for firmware counters.
> Rename the driver and its related code to represent generic name
> that will handle both sbi and ISA mechanism for hpmcounter related
> operations. Take this opportunity to update the Kconfig names to
> match the new driver name closely.
>
> No functional change intended.
>
> Reviewed-by: Clément Léger <cleger@rivosinc.com>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
> MAINTAINERS | 4 +-
> arch/riscv/include/asm/kvm_vcpu_pmu.h | 4 +-
> arch/riscv/include/asm/kvm_vcpu_sbi.h | 2 +-
> arch/riscv/kvm/Makefile | 4 +-
> arch/riscv/kvm/vcpu_sbi.c | 2 +-
> drivers/perf/Kconfig | 16 +-
> drivers/perf/Makefile | 4 +-
> drivers/perf/{riscv_pmu.c => riscv_pmu_common.c} | 0
> drivers/perf/{riscv_pmu_sbi.c => riscv_pmu_dev.c} | 214 +++++++++++++---------
I'm still against this renaming churn. It sucks for backporting and
you're also changing the name of the driver, which could be used by
scripts in userspace (e.g. module listings, udev rules, cmdline options)
Will
next prev parent reply other threads:[~2025-04-04 13:59 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-27 19:35 [PATCH v5 00/21] Add Counter delegation ISA extension support Atish Patra
2025-03-27 19:35 ` [PATCH v5 01/21] perf pmu-events: Add functions in jevent.py to parse counter and event info for hardware aware grouping Atish Patra
2025-04-23 0:13 ` Atish Patra
2025-03-27 19:35 ` [PATCH v5 02/21] RISC-V: Add Sxcsrind ISA extension CSR definitions Atish Patra
2025-03-27 19:35 ` [PATCH v5 03/21] RISC-V: Add Sxcsrind ISA extension definition and parsing Atish Patra
2025-03-27 19:35 ` [PATCH v5 04/21] dt-bindings: riscv: add Sxcsrind ISA extension description Atish Patra
2025-03-27 19:35 ` [PATCH v5 05/21] RISC-V: Define indirect CSR access helpers Atish Patra
2025-03-27 19:35 ` [PATCH v5 06/21] RISC-V: Add Smcntrpmf extension parsing Atish Patra
2025-03-27 19:35 ` [PATCH v5 07/21] dt-bindings: riscv: add Smcntrpmf ISA extension description Atish Patra
2025-03-27 19:35 ` [PATCH v5 08/21] RISC-V: Add Sscfg extension CSR definition Atish Patra
2025-03-27 19:35 ` [PATCH v5 09/21] RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing Atish Patra
2025-03-27 19:35 ` [PATCH v5 10/21] dt-bindings: riscv: add Counter delegation ISA extensions description Atish Patra
2025-03-31 15:38 ` Conor Dooley
2025-03-27 19:35 ` [PATCH v5 11/21] RISC-V: perf: Restructure the SBI PMU code Atish Patra
2025-04-04 13:49 ` Will Deacon [this message]
2025-04-23 0:02 ` Atish Patra
2025-03-27 19:35 ` [PATCH v5 12/21] RISC-V: perf: Modify the counter discovery mechanism Atish Patra
2025-09-23 6:12 ` [External] " yunhui cui
2025-03-27 19:35 ` [PATCH v5 13/21] RISC-V: perf: Add a mechanism to defined legacy event encoding Atish Patra
2025-03-27 19:35 ` [PATCH v5 14/21] RISC-V: perf: Implement supervisor counter delegation support Atish Patra
2025-08-28 9:56 ` [External] " yunhui cui
2025-03-27 19:35 ` [PATCH v5 15/21] RISC-V: perf: Skip PMU SBI extension when not implemented Atish Patra
2025-03-27 19:35 ` [PATCH v5 16/21] RISC-V: perf: Use config2/vendor table for event to counter mapping Atish Patra
2025-03-27 19:35 ` [PATCH v5 17/21] RISC-V: perf: Add legacy event encodings via sysfs Atish Patra
2025-03-27 19:35 ` [PATCH v5 18/21] RISC-V: perf: Add Qemu virt machine events Atish Patra
2025-09-11 13:24 ` [External] " yunhui cui
2025-03-27 19:36 ` [PATCH v5 19/21] tools/perf: Support event code for arch standard events Atish Patra
2025-03-27 19:36 ` [PATCH v5 20/21] tools/perf: Pass the Counter constraint values in the pmu events Atish Patra
2025-04-23 0:17 ` Atish Patra
2025-03-27 19:36 ` [PATCH v5 21/21] Sync empty-pmu-events.c with autogenerated one Atish Patra
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