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From: Xiquan Zhang <zhangxiquan@hisilicon.com>
To: <catalin.marinas@arm.com>, <will@kernel.org>, <corbet@lwn.net>
Cc: <linux-arm-kernel@lists.infradead.org>,
	<linux-doc@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH] Documentation (arm64):Advanced SIMD and floating point support condition
Date: Tue, 8 Apr 2025 11:13:09 +0800	[thread overview]
Message-ID: <20250408031309.2095-1-zhangxiquan@hisilicon.com> (raw)

From: zhangyu <zhangyu550@huawei.com>

Because the kernel code cannot be started from el1
according to the booting.rst.
It is found that CPTR_EL2.FPEN is not configured.
After the configuration, the problem is solved.

Signed-off-by: zhangyu <zhangyu550@huawei.com>
Signed-off-by: zhangxiquan <zhangxiquan@hisilicon.com>
---
 Documentation/arch/arm64/booting.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm64/booting.rst
index dee7b6de864f..ccefc42b51bc 100644
--- a/Documentation/arch/arm64/booting.rst
+++ b/Documentation/arch/arm64/booting.rst
@@ -309,6 +309,7 @@ Before jumping into the kernel, the following conditions must be met:
   - If EL2 is present and the kernel is entered at EL1:

     - CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
+    - CPTR_EL2.FPEN (bit 21:20) must be initialised to 0b11.

   For CPUs with the Scalable Vector Extension (FEAT_SVE) present:

--
2.45.1.windows.1



             reply	other threads:[~2025-04-08  3:27 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-08  3:13 Xiquan Zhang [this message]
2025-04-29 13:11 ` [PATCH] Documentation (arm64):Advanced SIMD and floating point support condition Will Deacon
     [not found]   ` <0acdf18f6c2748919dcbeb943e4ced3e@hisilicon.com>
     [not found]     ` <a90e072198c344e3a4ae0ed0cb8bbe62@huawei.com>
2025-05-13  3:11       ` 答复: " Zhangxiquan

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