Re: [PATCH 2/2] arm64: dts: ti: Add basic support for phyBOARD-Izar-AM68x

[Nishanth Menon <nm@ti.com>]

Quick look comments below.

On 12:10-20250411, Dominik Haller wrote:
> The phyCORE-AM68x/TDA4x [1] is a SoM (System on Module) featuring TI's
> AM68x/TDA4x SoC. It can be used in combination with different carrier
> boards. This module can come with different sizes and models for DDR,
> eMMC, SPI NOR Flash and various SoCs from the AM68x/TDA4x (J721S2) family.
> 
> A reference carrier board design, called phyBOARD-Izar is used for the
> phyCORE-AM68x/TDA4x development kit [2].
> 
>     Supported features:
>       * Debug UART
>       * 2x SPI NOR Flash
>       * eMMC
>       * 2x Ethernet
>       * Micro SD card
>       * I2C EEPROM
>       * I2C RTC
>       * 2x I2C GPIO Expander
>       * LEDs
>       * USB 5 Gbit/s
>       * PCIe

Can we drop the whitespace prefix?

> 
> For more details see the product pages for the SoM and the
> development kit:
> 
> [1] https://www.phytec.eu/en/produkte/system-on-modules/phycore-am68x-tda4x/
> [2] https://www.phytec.eu/en/produkte/development-kits/phyboard-izar/
> 
> Signed-off-by: Dominik Haller <d.haller@phytec.de>
> ---

Could you share the bootlog in the diffstat along with output of
deferred_devices Using the default defconfig -> I want to make sure
there are no defconfig updates needed.

>  arch/arm64/boot/dts/ti/Makefile               |   1 +
>  .../boot/dts/ti/k3-am68-phyboard-izar.dts     | 576 +++++++++++++++++
>  .../boot/dts/ti/k3-am68-phycore-som.dtsi      | 594 ++++++++++++++++++
>  3 files changed, 1171 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts
>  create mode 100644 arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi
> 

[...]

> +
> +#include "k3-serdes.h"
> +
> +/ {
> +	compatible = "phytec,am68-phyboard-izar", "ti,j721s2";
> +	model = "PHYTEC phyBOARD-Izar-AM68x";
> +
> +	aliases {
> +		ethernet0 = &cpsw_port1;
> +		mmc1 = &main_sdhci1;
> +		serial0 = &wkup_uart0;
> +		serial1 = &mcu_uart0;
> +		serial2 = &main_uart8;
> +		serial3 = &main_uart1;
> +		serial4 = &main_uart2;


Could you order this slightly differently:
serial
mmc
ethernet

> +	};
> +
> +	chosen {
> +		stdout-path = "serial2:115200n8";

= &main_uart8

> +	};
> +
> +	transceiver1: can-phy1 {
> +		compatible = "ti,tcan1043";
> +		#phy-cells = <0>;
> +		max-bitrate = <8000000>;
> +	};
> +

[...]

> +
> +&serdes_refclk {
> +	clock-frequency = <100000000>;
> +};
> +
> +&serdes0 {
> +	status = "okay";

Documentation/devicetree/bindings/dts-coding-style.rst
	Add an EoL

> +	serdes0_pcie_link: phy@0 {
> +		reg = <0>;
> +		cdns,num-lanes = <1>;
> +		#phy-cells = <0>;
> +		cdns,phy-type = <PHY_TYPE_PCIE>;
vendor specific properties come last



> +		resets = <&serdes_wiz0 1>;
> +	};
Add an EoL

> +	serdes0_usb_link: phy@1 {
> +		reg = <1>;
> +		cdns,num-lanes = <1>;
> +		#phy-cells = <0>;
> +		cdns,phy-type = <PHY_TYPE_USB3>;

Same.

> +		resets = <&serdes_wiz0 2>;
> +	};
> +};
> +

[...]

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D