[PATCH v1 0/3] MediaTek Dimensity 1200 - Add Clocks support

[PATCH v1 0/3] MediaTek Dimensity 1200 - Add Clocks support

[AngeloGioacchino Del Regno]

In preparation for adding basic support for the OnePlus Nord 2 5G
DN2103 smartphone, this series adds support for main, multimedia,
and MFG clocks of the MediaTek Dimensity 1200 (MT6893) SoC.

Main blocks are required for console boot, while multimedia clocks
are required for display support, and MediaTek Flexible Graphics
(MFG) clocks are required for bringing up the Mali-G77 MC9 GPU.

AngeloGioacchino Del Regno (3):
  dt-bindings: clock: mediatek: Describe MT6893 Clock Controllers
  clk: mediatek: Add main clocks drivers for Dimensity 1200 MT6893
  clk: mediatek: mt6893: Add peripheral and multimedia clock drivers

 .../bindings/clock/mediatek,mt6893-clock.yaml |  56 ++
 .../clock/mediatek,mt6893-sys-clock.yaml      |  68 ++
 drivers/clk/mediatek/Kconfig                  |  58 ++
 drivers/clk/mediatek/Makefile                 |  10 +
 drivers/clk/mediatek/clk-mt6893-apmixedsys.c  | 137 +++
 .../clk/mediatek/clk-mt6893-imp_iic_wrap.c    |  94 ++
 drivers/clk/mediatek/clk-mt6893-infra_ao.c    | 185 ++++
 drivers/clk/mediatek/clk-mt6893-mdp.c         | 116 +++
 drivers/clk/mediatek/clk-mt6893-mfg.c         |  51 +
 drivers/clk/mediatek/clk-mt6893-mm.c          | 129 +++
 drivers/clk/mediatek/clk-mt6893-scp_adsp.c    |  52 ++
 drivers/clk/mediatek/clk-mt6893-topckgen.c    | 880 ++++++++++++++++++
 drivers/clk/mediatek/clk-mt6893-vdec.c        |  98 ++
 drivers/clk/mediatek/clk-mt6893-venc.c        |  72 ++
 .../dt-bindings/clock/mediatek,mt6893-clk.h   | 449 +++++++++
 15 files changed, 2455 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt6893-clock.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt6893-sys-clock.yaml
 create mode 100644 drivers/clk/mediatek/clk-mt6893-apmixedsys.c
 create mode 100644 drivers/clk/mediatek/clk-mt6893-imp_iic_wrap.c
 create mode 100644 drivers/clk/mediatek/clk-mt6893-infra_ao.c
 create mode 100644 drivers/clk/mediatek/clk-mt6893-mdp.c
 create mode 100644 drivers/clk/mediatek/clk-mt6893-mfg.c
 create mode 100644 drivers/clk/mediatek/clk-mt6893-mm.c
 create mode 100644 drivers/clk/mediatek/clk-mt6893-scp_adsp.c
 create mode 100644 drivers/clk/mediatek/clk-mt6893-topckgen.c
 create mode 100644 drivers/clk/mediatek/clk-mt6893-vdec.c
 create mode 100644 drivers/clk/mediatek/clk-mt6893-venc.c
 create mode 100644 include/dt-bindings/clock/mediatek,mt6893-clk.h

-- 
2.49.0

[PATCH v1 1/3] dt-bindings: clock: mediatek: Describe MT6893 Clock Controllers

[AngeloGioacchino Del Regno]

Add bindings to describe both the System Clock Controllers,
providing PLLs and main clocks, and the functional clock
controllers, providing peripheral clocks (i2c, multimedia, etc),
as found in the MediaTek Dimensity 1200 (MT6893) SoC.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 .../bindings/clock/mediatek,mt6893-clock.yaml |  56 +++
 .../clock/mediatek,mt6893-sys-clock.yaml      |  68 +++
 .../dt-bindings/clock/mediatek,mt6893-clk.h   | 449 ++++++++++++++++++
 3 files changed, 573 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt6893-clock.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt6893-sys-clock.yaml
 create mode 100644 include/dt-bindings/clock/mediatek,mt6893-clk.h

diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt6893-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt6893-clock.yaml
new file mode 100644
index 000000000000..72fbde7263a1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt6893-clock.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt6893-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Functional Clock Controller for MT6893
+
+maintainers:
+  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+
+description: |
+  The clock architecture in MediaTek SoCs is structured like below:
+  PLLs -->
+          dividers -->
+                      muxes
+                           -->
+                              clock gate
+
+  The devices provide clock gate control in different IP blocks.
+
+properties:
+  compatible:
+    enum:
+      - mediatek,mt6893-scp-adsp
+      - mediatek,mt6893-imp-iic-wrap-c
+      - mediatek,mt6893-imp-iic-wrap-e
+      - mediatek,mt6893-imp-iic-wrap-n
+      - mediatek,mt6893-imp-iic-wrap-s
+      - mediatek,mt6893-mdpsys
+      - mediatek,mt6893-mfgcfg
+      - mediatek,mt6893-vdecsys
+      - mediatek,mt6893-vdecsys-soc
+      - mediatek,mt6893-vencsys-c0
+      - mediatek,mt6893-vencsys-c1
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@11008000 {
+        compatible = "mediatek,mt6893-imp-iic-wrap-c";
+        reg = <0x11008000 0x1000>;
+        #clock-cells = <1>;
+    };
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt6893-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt6893-sys-clock.yaml
new file mode 100644
index 000000000000..a7d258f5b6e2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt6893-sys-clock.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt6893-sys-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek System Clock Controller for MT6893
+
+maintainers:
+  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+
+description: |
+  The clock architecture in MediaTek SoCs is structured like below:
+  PLLs -->
+          dividers -->
+                      muxes
+                           -->
+                              clock gate
+
+  The apmixedsys provides most of PLLs which are generated from SoC 26m.
+  The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
+  The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
+  The device nodes also provide the system control capacity for configuration.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt6893-apmixedsys
+          - mediatek,mt6893-infracfg-ao
+          - mediatek,mt6893-topckgen
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@10000000 {
+        compatible = "mediatek,mt6893-topckgen", "syscon";
+        reg = <0x10000000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+    clock-controller@10001000 {
+        compatible = "mediatek,mt6893-infracfg-ao", "syscon";
+        reg = <0x10001000 0x1000>;
+        #clock-cells = <1>;
+    };
+
+    clock-controller@1000c000 {
+        compatible = "mediatek,mt6893-apmixedsys", "syscon";
+        reg = <0x1000c000 0x1000>;
+        #clock-cells = <1>;
+    };
diff --git a/include/dt-bindings/clock/mediatek,mt6893-clk.h b/include/dt-bindings/clock/mediatek,mt6893-clk.h
new file mode 100644
index 000000000000..e56da571615d
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt6893-clk.h
@@ -0,0 +1,449 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Copyright (c) 2025 Collabora Ltd
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT6893_H
+#define _DT_BINDINGS_CLK_MT6893_H
+
+/* TOPCKGEN */
+#define CLK_TOP_ULPOSC			0
+#define CLK_TOP_MAINPLL_D3		1
+#define CLK_TOP_MAINPLL_D4		2
+#define CLK_TOP_MAINPLL_D4_D2		3
+#define CLK_TOP_MAINPLL_D4_D4		4
+#define CLK_TOP_MAINPLL_D4_D8		5
+#define CLK_TOP_MAINPLL_D4_D16		6
+#define CLK_TOP_MAINPLL_D5		7
+#define CLK_TOP_MAINPLL_D5_D2		8
+#define CLK_TOP_MAINPLL_D5_D4		9
+#define CLK_TOP_MAINPLL_D5_D8		10
+#define CLK_TOP_MAINPLL_D6		11
+#define CLK_TOP_MAINPLL_D6_D2		12
+#define CLK_TOP_MAINPLL_D6_D4		13
+#define CLK_TOP_MAINPLL_D6_D8		14
+#define CLK_TOP_MAINPLL_D7		15
+#define CLK_TOP_MAINPLL_D7_D2		16
+#define CLK_TOP_MAINPLL_D7_D4		17
+#define CLK_TOP_MAINPLL_D7_D8		18
+#define CLK_TOP_MAINPLL_D9		19
+#define CLK_TOP_UNIVPLL_D2		20
+#define CLK_TOP_UNIVPLL_D3		21
+#define CLK_TOP_UNIVPLL_D4		22
+#define CLK_TOP_UNIVPLL_D4_D2		23
+#define CLK_TOP_UNIVPLL_D4_D4		24
+#define CLK_TOP_UNIVPLL_D4_D8		25
+#define CLK_TOP_UNIVPLL_D5		26
+#define CLK_TOP_UNIVPLL_D5_D2		27
+#define CLK_TOP_UNIVPLL_D5_D4		28
+#define CLK_TOP_UNIVPLL_D5_D8		29
+#define CLK_TOP_UNIVPLL_D5_D16		30
+#define CLK_TOP_UNIVPLL_D6		31
+#define CLK_TOP_UNIVPLL_D6_D2		32
+#define CLK_TOP_UNIVPLL_D6_D4		33
+#define CLK_TOP_UNIVPLL_D6_D8		34
+#define CLK_TOP_UNIVPLL_D6_D16		35
+#define CLK_TOP_UNIVPLL_D7		36
+#define CLK_TOP_UNIVPLL_D7_D2		37
+#define CLK_TOP_UNIVPLL_192M_D2		38
+#define CLK_TOP_UNIVPLL_192M_D4		39
+#define CLK_TOP_UNIVPLL_192M_D8		40
+#define CLK_TOP_UNIVPLL_192M_D16	41
+#define CLK_TOP_UNIVPLL_192M_D32	42
+#define CLK_TOP_USB20_192M		43
+#define CLK_TOP_USB20_PLL_D2		44
+#define CLK_TOP_USB20_PLL_D4		45
+#define CLK_TOP_MPLL_D2			46
+#define CLK_TOP_MPLL_D4			47
+#define CLK_TOP_APLL1_D2		48
+#define CLK_TOP_APLL1_D4		49
+#define CLK_TOP_APLL1_D8		50
+#define CLK_TOP_APLL2_D2		51
+#define CLK_TOP_APLL2_D4		52
+#define CLK_TOP_APLL2_D8		53
+#define CLK_TOP_ADSPPLL_D4		54
+#define CLK_TOP_ADSPPLL_D5		55
+#define CLK_TOP_ADSPPLL_D6		56
+#define CLK_TOP_MMPLL_D3		57
+#define CLK_TOP_MMPLL_D4		58
+#define CLK_TOP_MMPLL_D4_D2		59
+#define CLK_TOP_MMPLL_D4_D4		60
+#define CLK_TOP_MMPLL_D5		61
+#define CLK_TOP_MMPLL_D5_D2		62
+#define CLK_TOP_MMPLL_D5_D4		63
+#define CLK_TOP_MMPLL_D6		64
+#define CLK_TOP_MMPLL_D6_D2		65
+#define CLK_TOP_MMPLL_D7		66
+#define CLK_TOP_MMPLL_D9		67
+#define CLK_TOP_APUPLL_D2		68
+#define CLK_TOP_TVDPLL_D2		69
+#define CLK_TOP_TVDPLL_D4		70
+#define CLK_TOP_TVDPLL_D8		71
+#define CLK_TOP_TVDPLL_D16		72
+#define CLK_TOP_MSDCPLL_D2		73
+#define CLK_TOP_MSDCPLL_D4		74
+#define CLK_TOP_MSDCPLL_D8		75
+#define CLK_TOP_MSDCPLL_D16		76
+#define CLK_TOP_OSC_D2			77
+#define CLK_TOP_OSC_D4			78
+#define CLK_TOP_OSC_D8			79
+#define CLK_TOP_OSC_D16			80
+#define CLK_TOP_OSC_D10			81
+#define CLK_TOP_OSC_D20			82
+#define CLK_TOP_TVDPLL_MAINPLL_D2	83
+#define CLK_TOP_AXI_SEL			84
+#define CLK_TOP_SPM_SEL			85
+#define CLK_TOP_SCP_SEL			86
+#define CLK_TOP_BUS_AXIMEM_SEL		87
+#define CLK_TOP_DISP_SEL		88
+#define CLK_TOP_MDP_SEL			89
+#define CLK_TOP_IMG1_SEL		90
+#define CLK_TOP_IMG2_SEL		91
+#define CLK_TOP_IPE_SEL			92
+#define CLK_TOP_DPE_SEL			93
+#define CLK_TOP_CAM_SEL			94
+#define CLK_TOP_CCU_SEL			95
+#define CLK_TOP_DSP_SEL			96
+#define CLK_TOP_DSP1_SEL		97
+#define CLK_TOP_DSP2_SEL		98
+#define CLK_TOP_DSP3_SEL		99
+#define CLK_TOP_DSP4_SEL		100
+#define CLK_TOP_DSP5_SEL		101
+#define CLK_TOP_DSP6_SEL		102
+#define CLK_TOP_DSP7_SEL		103
+#define CLK_TOP_IPU_IF_SEL		104
+#define CLK_TOP_MFG_SEL			105
+#define CLK_TOP_CAMTG_SEL		106
+#define CLK_TOP_CAMTG2_SEL		107
+#define CLK_TOP_CAMTG3_SEL		108
+#define CLK_TOP_CAMTG4_SEL		109
+#define CLK_TOP_UART_SEL		110
+#define CLK_TOP_SPI_SEL			111
+#define CLK_TOP_MSDC50_0_HCLK_SEL	112
+#define CLK_TOP_MSDC50_0_SEL		113
+#define CLK_TOP_MSDC30_1_SEL		114
+#define CLK_TOP_AUDIO_SEL		115
+#define CLK_TOP_AUD_INTBUS_SEL		116
+#define CLK_TOP_PWRAP_ULPOSC_SEL	117
+#define CLK_TOP_ATB_SEL			118
+#define CLK_TOP_SSPM_SEL		119
+#define CLK_TOP_DP_SEL			120
+#define CLK_TOP_SCAM_SEL		121
+#define CLK_TOP_DISP_PWM_SEL		122
+#define CLK_TOP_USB_TOP_SEL		123
+#define CLK_TOP_SSUSB_XHCI_SEL		124
+#define CLK_TOP_I2C_SEL			125
+#define CLK_TOP_SENINF_SEL		126
+#define CLK_TOP_SENINF1_SEL		127
+#define CLK_TOP_SENINF2_SEL		128
+#define CLK_TOP_SENINF3_SEL		129
+#define CLK_TOP_DXCC_SEL		130
+#define CLK_TOP_AUD_ENGEN1_SEL		131
+#define CLK_TOP_AUD_ENGEN2_SEL		132
+#define CLK_TOP_AES_UFSFDE_SEL		133
+#define CLK_TOP_UFS_SEL			134
+#define CLK_TOP_AUD_1_SEL		135
+#define CLK_TOP_AUD_2_SEL		136
+#define CLK_TOP_ADSP_SEL		137
+#define CLK_TOP_DPMAIF_MAIN_SEL		138
+#define CLK_TOP_VENC_SEL		139
+#define CLK_TOP_VDEC_SEL		140
+#define CLK_TOP_VDEC_LAT_SEL		141
+#define CLK_TOP_CAMTM_SEL		142
+#define CLK_TOP_PWM_SEL			143
+#define CLK_TOP_AUDIO_H_SEL		144
+#define CLK_TOP_CAMTG5_SEL		145
+#define CLK_TOP_CAMTG6_SEL		146
+#define CLK_TOP_MCUPM_SEL		147
+#define CLK_TOP_SPMI_MST_SEL		148
+#define CLK_TOP_DVFSRC_SEL		149
+#define CLK_TOP_APLL_I2S0_MCK_SEL	150
+#define CLK_TOP_APLL_I2S1_MCK_SEL	151
+#define CLK_TOP_APLL_I2S2_MCK_SEL	152
+#define CLK_TOP_APLL_I2S3_MCK_SEL	153
+#define CLK_TOP_APLL_I2S4_MCK_SEL	154
+#define CLK_TOP_APLL_I2S5_MCK_SEL	155
+#define CLK_TOP_APLL_I2S6_MCK_SEL	156
+#define CLK_TOP_APLL_I2S7_MCK_SEL	157
+#define CLK_TOP_APLL_I2S8_MCK_SEL	158
+#define CLK_TOP_APLL_I2S9_MCK_SEL	159
+#define CLK_TOP_APLL1_CK_DIV0		160
+#define CLK_TOP_APLL2_CK_DIV0		161
+#define CLK_TOP_APLL12_CK_DIV0		162
+#define CLK_TOP_APLL12_CK_DIV1		163
+#define CLK_TOP_APLL12_CK_DIV2		164
+#define CLK_TOP_APLL12_CK_DIV3		165
+#define CLK_TOP_APLL12_CK_DIV4		166
+#define CLK_TOP_APLL12_CK_DIVB		167
+#define CLK_TOP_APLL12_CK_DIV5_LSB	168
+#define CLK_TOP_APLL12_CK_DIV5_MSB	169
+#define CLK_TOP_APLL12_CK_DIV6		170
+#define CLK_TOP_APLL12_CK_DIV7		171
+#define CLK_TOP_APLL12_CK_DIV8		172
+#define CLK_TOP_APLL12_CK_DIV9		173
+
+/* INFRACFG_AO */
+#define CLK_INFRA_AO_PMIC_TMR		0
+#define CLK_INFRA_AO_PMIC_AP		1
+#define CLK_INFRA_AO_GCE		2
+#define CLK_INFRA_AO_GCE2		3
+#define CLK_INFRA_AO_THERM		4
+#define CLK_INFRA_AO_I2C0		5
+#define CLK_INFRA_AO_I2C1		6
+#define CLK_INFRA_AO_I2C2		7
+#define CLK_INFRA_AO_I2C3		8
+#define CLK_INFRA_AO_PWM_HCLK		9
+#define CLK_INFRA_AO_PWM1		10
+#define CLK_INFRA_AO_PWM2		11
+#define CLK_INFRA_AO_PWM3		12
+#define CLK_INFRA_AO_PWM4		13
+#define CLK_INFRA_AO_PWM		14
+#define CLK_INFRA_AO_UART0		15
+#define CLK_INFRA_AO_UART1		16
+#define CLK_INFRA_AO_UART2		17
+#define CLK_INFRA_AO_UART3		18
+#define CLK_INFRA_AO_GCE_26M		19
+#define CLK_INFRA_AO_CQ_DMA_FPC		20
+#define CLK_INFRA_AO_BTIF		21
+#define CLK_INFRA_AO_SPI0		22
+#define CLK_INFRA_AO_MSDC0		23
+#define CLK_INFRA_AO_MSDC1		24
+#define CLK_INFRA_AO_MSDC0_SRC		25
+#define CLK_INFRA_AO_AUXADC		26
+#define CLK_INFRA_AO_CPUM		27
+#define CLK_INFRA_AO_CCIF1_AP		28
+#define CLK_INFRA_AO_CCIF1_MD		29
+#define CLK_INFRA_AO_MSDC1_SRC		30
+#define CLK_INFRA_AO_AP_DMA_PS		31
+#define CLK_INFRA_AO_DEVICE_APC		32
+#define CLK_INFRA_AO_CCIF_AP		33
+#define CLK_INFRA_AO_AUDIO		34
+#define CLK_INFRA_AO_CCIF_MD		35
+#define CLK_INFRA_AO_DXCC_SEC_CORE	36
+#define CLK_INFRA_AO_SSUSB		37
+#define CLK_INFRA_AO_DISP_PWM		38
+#define CLK_INFRA_AO_DPMAIF		39
+#define CLK_INFRA_AO_AUDIO_26M_BCLK	40
+#define CLK_INFRA_AO_SPI1		41
+#define CLK_INFRA_AO_I2C4		42
+#define CLK_INFRA_AO_SPI2		43
+#define CLK_INFRA_AO_SPI3		44
+#define CLK_INFRA_AO_UNIPRO_SYSCLK	45
+#define CLK_INFRA_AO_UFS_MP_SAP_BCLK	46
+#define CLK_INFRA_AO_I2C5		47
+#define CLK_INFRA_AO_I2C5_ARBITER	48
+#define CLK_INFRA_AO_I2C5_IMM		49
+#define CLK_INFRA_AO_I2C1_ARBITER	50
+#define CLK_INFRA_AO_I2C1_IMM		51
+#define CLK_INFRA_AO_I2C2_ARBITER	52
+#define CLK_INFRA_AO_I2C2_IMM		53
+#define CLK_INFRA_AO_SPI4		54
+#define CLK_INFRA_AO_SPI5		55
+#define CLK_INFRA_AO_CQ_DMA		56
+#define CLK_INFRA_AO_UFS		57
+#define CLK_INFRA_AO_AES		58
+#define CLK_INFRA_AO_SSUSB_XHCI		59
+#define CLK_INFRA_AO_MSDC0_SELF		60
+#define CLK_INFRA_AO_MSDC1_SELF		61
+#define CLK_INFRA_AO_MSDC2_SELF		62
+#define CLK_INFRA_AO_I2C6		63
+#define CLK_INFRA_AO_AP_MSDC0		64
+#define CLK_INFRA_AO_MD_MSDC0		65
+#define CLK_INFRA_AO_I2C7		66
+#define CLK_INFRA_AO_I2C8		67
+#define CLK_INFRA_AO_FBIST2FPC		68
+#define CLK_INFRA_AO_DEVICE_DAPC_SYNC	69
+#define CLK_INFRA_AO_DPMAIF_MAIN	70
+#define CLK_INFRA_AO_SPI6_CK		71
+#define CLK_INFRA_AO_SPI7_CK		72
+#define CLK_INFRA_AO_APDMA		73
+
+/* APMIXEDSYS */
+#define CLK_APMIXED_ARMPLL_LL		0
+#define CLK_APMIXED_ARMPLL_BL0		1
+#define CLK_APMIXED_ARMPLL_BL1		2
+#define CLK_APMIXED_ARMPLL_BL2		3
+#define CLK_APMIXED_ARMPLL_BL3		4
+#define CLK_APMIXED_CCIPLL		5
+#define CLK_APMIXED_MAINPLL		6
+#define CLK_APMIXED_UNIVPLL		7
+#define CLK_APMIXED_MSDCPLL		8
+#define CLK_APMIXED_MMPLL		9
+#define CLK_APMIXED_ADSPPLL		10
+#define CLK_APMIXED_MFGPLL		11
+#define CLK_APMIXED_TVDPLL		12
+#define CLK_APMIXED_APLL1		13
+#define CLK_APMIXED_APLL2		14
+#define CLK_APMIXED_MPLL		15
+#define CLK_APMIXED_APUPLL		16
+
+/* SCP_ADSP */
+#define CLK_SCP_ADSP_AUDIODSP	0
+
+/* IMP_IIC_WRAP_C */
+#define CLK_IMP_IIC_WRAP_C_AP_I2C0		0
+#define CLK_IMP_IIC_WRAP_C_AP_I2C10		1
+#define CLK_IMP_IIC_WRAP_C_AP_I2C11		2
+#define CLK_IMP_IIC_WRAP_C_AP_I2C12		3
+#define CLK_IMP_IIC_WRAP_C_AP_I2C13		4
+
+/* IMP_IIC_WRAP_E */
+#define CLK_IMP_IIC_WRAP_E_AP_I2C3		0
+#define CLK_IMP_IIC_WRAP_E_AP_I2C9		1
+
+/* IMP_IIC_WRAP_S */
+#define CLK_IMP_IIC_WRAP_S_AP_I2C1		0
+#define CLK_IMP_IIC_WRAP_S_AP_I2C2		1
+#define CLK_IMP_IIC_WRAP_S_AP_I2C4		2
+#define CLK_IMP_IIC_WRAP_S_AP_I2C7		3
+#define CLK_IMP_IIC_WRAP_S_AP_I2C8		4
+
+/* IMP_IIC_WRAP_N */
+#define CLK_IMP_IIC_WRAP_N_AP_I2C5		0
+#define CLK_IMP_IIC_WRAP_N_AP_I2C6		1
+
+/* MFGCFG */
+#define CLK_MFGCFG_BG3D			0
+
+/* MMSYS_CONFIG */
+#define CLK_MM_DISP_RSZ0		0
+#define CLK_MM_DISP_RSZ1		1
+#define CLK_MM_DISP_OVL0		2
+#define CLK_MM_INLINE			3
+#define CLK_MM_MDP_TDSHP4		4
+#define CLK_MM_MDP_TDSHP5		5
+#define CLK_MM_MDP_AAL4			6
+#define CLK_MM_MDP_AAL5			7
+#define CLK_MM_MDP_HDR4			8
+#define CLK_MM_MDP_HDR5			9
+#define CLK_MM_MDP_RSZ4			10
+#define CLK_MM_MDP_RSZ5			11
+#define CLK_MM_MDP_RDMA4		12
+#define CLK_MM_MDP_RDMA5		13
+#define CLK_MM_DISP_FAKE_ENG0		14
+#define CLK_MM_DISP_FAKE_ENG1		15
+#define CLK_MM_DISP_OVL0_2L		16
+#define CLK_MM_DISP_OVL1_2L		17
+#define CLK_MM_DISP_OVL2_2L		18
+#define CLK_MM_DISP_MUTEX		19
+#define CLK_MM_DISP_OVL1		20
+#define CLK_MM_DISP_OVL3_2L		21
+#define CLK_MM_DISP_CCORR0		22
+#define CLK_MM_DISP_CCORR1		23
+#define CLK_MM_DISP_COLOR0		24
+#define CLK_MM_DISP_COLOR1		25
+#define CLK_MM_DISP_POSTMASK0		26
+#define CLK_MM_DISP_POSTMASK1		27
+#define CLK_MM_DISP_DITHER0		28
+#define CLK_MM_DISP_DITHER1		29
+#define CLK_MM_DSI0_MM_CLK		30
+#define CLK_MM_DSI1_MM_CLK		31
+#define CLK_MM_DISP_GAMMA0		32
+#define CLK_MM_DISP_GAMMA1		33
+#define CLK_MM_DISP_AAL0		34
+#define CLK_MM_DISP_AAL1		35
+#define CLK_MM_DISP_WDMA0		36
+#define CLK_MM_DISP_WDMA1		37
+#define CLK_MM_DISP_UFBC_WDMA0		38
+#define CLK_MM_DISP_UFBC_WDMA1		39
+#define CLK_MM_DISP_RDMA0		40
+#define CLK_MM_DISP_RDMA1		41
+#define CLK_MM_DISP_RDMA4		42
+#define CLK_MM_DISP_RDMA5		43
+#define CLK_MM_DISP_DSC_WRAP		44
+#define CLK_MM_DP_INTF_MM_CLK		45
+#define CLK_MM_DISP_MERGE0		46
+#define CLK_MM_DISP_MERGE1		47
+#define CLK_MM_SMI_COMMON		48
+#define CLK_MM_SMI_GALS			49
+#define CLK_MM_SMI_INFRA		50
+#define CLK_MM_SMI_IOMMU		51
+#define CLK_MM_DSI0_INTF_CLK		52
+#define CLK_MM_DSI1_INTF_CLK		53
+#define CLK_MM_DP_INTF_INTF_CLK		54
+#define CLK_MM_CK_26_MHZ		55
+#define CLK_MM_CK_32_KHZ		56
+
+/* VDEC_SOC_GCON */
+#define CLK_VDEC_SOC_LARB1		0
+#define CLK_VDEC_SOC_LAT		1
+#define CLK_VDEC_SOC_LAT_ACTIVE		2
+#define CLK_VDEC_SOC_LAT_ENG		3
+#define CLK_VDEC_SOC_VDEC		4
+#define CLK_VDEC_SOC_VDEC_ACTIVE	5
+#define CLK_VDEC_SOC_VDEC_ENG		6
+
+/* VDEC_GCON */
+#define CLK_VDEC_LARB1			0
+#define CLK_VDEC_LAT			1
+#define CLK_VDEC_LAT_ACTIVE		2
+#define CLK_VDEC_LAT_ENG		3
+#define CLK_VDEC_VDEC			4
+#define CLK_VDEC_ACTIVE			5
+#define CLK_VDEC_VDEC_ENG		6
+
+/* VENC_GCON */
+#define CLK_VENC0_SET0_LARB		0
+#define CLK_VENC0_SET1_VENC		1
+#define CLK_VENC0_SET2_JPGENC		2
+#define CLK_VENC0_SET3_JPGDEC		3
+#define CLK_VENC0_SET4_JPGDEC_C1	4
+#define CLK_VENC0_SET5_GALS		5
+
+/* VENC_C1_GCON */
+#define CLK_VENC1_SET0_LARB		0
+#define CLK_VENC1_SET1_VENC		1
+#define CLK_VENC1_SET2_JPGENC		2
+#define CLK_VENC1_SET3_JPGDEC		3
+#define CLK_VENC1_SET4_JPGDEC_C1	4
+#define CLK_VENC1_SET5_GALS		5
+
+/* MDPSYS_CONFIG */
+#define CLK_MDP_RDMA0			0
+#define CLK_MDP_FG0			1
+#define CLK_MDP_HDR0			2
+#define CLK_MDP_AAL0			3
+#define CLK_MDP_RSZ0			4
+#define CLK_MDP_TDSHP0			5
+#define CLK_MDP_TCC0			6
+#define CLK_MDP_WROT0			7
+#define CLK_MDP_RDMA2			8
+#define CLK_MDP_AAL2			9
+#define CLK_MDP_RSZ2			10
+#define CLK_MDP_COLOR0			11
+#define CLK_MDP_TDSHP2			12
+#define CLK_MDP_TCC2			13
+#define CLK_MDP_WROT2			14
+#define CLK_MDP_MUTEX0			15
+#define CLK_MDP_RDMA1			16
+#define CLK_MDP_FG1			17
+#define CLK_MDP_HDR1			18
+#define CLK_MDP_AAL1			19
+#define CLK_MDP_RSZ1			20
+#define CLK_MDP_TDSHP1			21
+#define CLK_MDP_TCC1			22
+#define CLK_MDP_WROT1			23
+#define CLK_MDP_RDMA3			24
+#define CLK_MDP_AAL3			25
+#define CLK_MDP_RSZ3			26
+#define CLK_MDP_COLOR1			27
+#define CLK_MDP_TDSHP3			28
+#define CLK_MDP_TCC3			29
+#define CLK_MDP_WROT3			30
+#define CLK_MDP_APB_BUS			31
+#define CLK_MDP_MMSYSRAM		32
+#define CLK_MDP_APMCU_GALS		33
+#define CLK_MDP_SMI0			36
+#define CLK_MDP_IMG_DL_ASYNC0		37
+#define CLK_MDP_IMG_DL_ASYNC1		38
+#define CLK_MDP_IMG_DL_ASYNC2		39
+#define CLK_MDP_SMI1			40
+#define CLK_MDP_IMG_DL_ASYNC3		41
+#define CLK_MDP_SMI2			44
+#define CLK_MDP_IMG0_IMG_DL_ASYNC0	48
+#define CLK_MDP_IMG0_IMG_DL_ASYNC1	49
+#define CLK_MDP_IMG1_IMG_DL_ASYNC2	50
+#define CLK_MDP_IMG1_IMG_DL_ASYNC3	51
+
+#endif /* _DT_BINDINGS_CLK_MT6893_H */
-- 
2.49.0

Re: [PATCH v1 1/3] dt-bindings: clock: mediatek: Describe MT6893 Clock Controllers

[Rob Herring]

On Thu, Apr 10, 2025 at 04:41:08PM +0200, AngeloGioacchino Del Regno wrote:
> Add bindings to describe both the System Clock Controllers,
> providing PLLs and main clocks, and the functional clock
> controllers, providing peripheral clocks (i2c, multimedia, etc),
> as found in the MediaTek Dimensity 1200 (MT6893) SoC.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  .../bindings/clock/mediatek,mt6893-clock.yaml |  56 +++
>  .../clock/mediatek,mt6893-sys-clock.yaml      |  68 +++

These just duplicate the same schema as the mt8365 bindings. Just add 
compatibles there.

Or I'm open to other options. The only variation among all of these 
seems to be whether or not they have 'syscon' compatible or 
'#reset-cells'. And for mt8188 it seems we have that wrong (see below)


In general, it would be nice to see more clean-ups of the existing 
Mediatek stuff before a new SoC. It makes me sad when I appear to be the 
only one that cares.

For reference, here's the top warnings for Mediatek on arm64 (999 total, 
182 unique (stripping the dtb name), 27 undocumented compatibles). This 
information is available daily from my CI job
(https://gitlab.com/robherring/linux-dt/-/jobs).

Mediatek has the most warnings with 182. 

arch/arm64/boot/dts/mediatek:999:182
     29  syscon@13000000 (mediatek,mt8183-mfgcfg): 'power-domains' does not match any of the regexes: 'pinctrl-[0-9]+'
     27  pinctrl@10005000 (mediatek,mt8183-pinctrl): panel-pins-default: 'panel-reset' does not match any of the regexes: '^pins', 'pinctrl-[0-9]+'
     27  pinctrl@10005000 (mediatek,mt8183-pinctrl): mmc1-pins-uhs:pins-cmd-dat:mediatek,pull-up-adv: 10 is not one of [0, 1, 2, 3]
     27  pinctrl@10005000 (mediatek,mt8183-pinctrl): mmc1-pins-uhs:pins-clk:mediatek,pull-down-adv: 10 is not one of [0, 1, 2, 3]
     27  pinctrl@10005000 (mediatek,mt8183-pinctrl): mmc1-pins-default:pins-cmd-dat:mediatek,pull-up-adv: 10 is not one of [0, 1, 2, 3]
     27  pinctrl@10005000 (mediatek,mt8183-pinctrl): mmc1-pins-default:pins-clk:mediatek,pull-down-adv: 10 is not one of [0, 1, 2, 3]
     27  pinctrl@10005000 (mediatek,mt8183-pinctrl): mmc0-pins-uhs:pins-ds:mediatek,pull-down-adv: 10 is not one of [0, 1, 2, 3]
     27  pinctrl@10005000 (mediatek,mt8183-pinctrl): mmc0-pins-uhs:pins-clk:mediatek,pull-down-adv: 10 is not one of [0, 1, 2, 3]
     27  pinctrl@10005000 (mediatek,mt8183-pinctrl): mmc0-pins-default:pins-clk:mediatek,pull-down-adv: 10 is not one of [0, 1, 2, 3]
     27  dsi@14014000 (mediatek,mt8183-dsi): ports: 'port@1' is a required property
     27  dsi@14014000 (mediatek,mt8183-dsi): ports: 'port@0' is a required property
     27  dsi@14014000 (mediatek,mt8183-dsi): Unevaluated properties are not allowed ('ports' was unexpected)
     27  bt-sco (linux,bt-sco): '#sound-dai-cells' is a required property
     22  pmic (mediatek,mt6359): regulators: 'compatible' is a required property
     22  pmic (mediatek,mt6359): '#sound-dai-cells', 'mt6359rtc' do not match any of the regexes: 'pinctrl-[0-9]+'
     17  pinctrl@10005000 (mediatek,mt8183-pinctrl): volume-button-pins: 'voldn-btn-odl', 'volup-btn-odl' do not match any of the regexes: '^pins', 'pinctrl-[0-9]+'
     17  pinctrl@10005000 (mediatek,mt8183-pinctrl): trackpad-pins: 'trackpad-int' does not match any of the regexes: '^pins', 'pinctrl-[0-9]+'
     17  pinctrl@10005000 (mediatek,mt8183-pinctrl): touchscreen-pins: 'touch-int-odl', 'touch-rst-l' do not match any of the regexes: '^pins', 'pinctrl-[0-9]+'
     17  pinctrl@10005000 (mediatek,mt8183-pinctrl): pp3300-panel-pins: 'panel-3v3-enable' does not match any of the regexes: '^pins', 'pinctrl-[0-9]+'
     12  sound (mediatek,mt8186-mt6366-rt1019-rt5682s-sound): 'model' is a required property
     11  pinctrl@10005000 (mediatek,mt8183-pinctrl): 'audiopins', 'audiotdmoutoff', 'audiotdmouton', 'ec-ap-int-odl', 'gpio-line-names', 'h1-int-od-l', 'i2c0', 'i2c1', 'i2c2', 'i2c3', 'i2c4', 'i2c5', 'i2c6', 'pp1000-mipibrdg-en', 'pp1800-mipibrdg-en', 'pp3300-mipibrdg-en', 'ppvarn-lcd-en', 'ppvarp-lcd-en', 'pwm0-pin-default', 'scp', 'spi0', 'spi1', 'spi2', 'spi3', 'spi4', 'spi5', 'ts3a227e_pins' do not match any of the regexes: '-pins(-[a-z]+)?$', 'pinctrl-[0-9]+'
     11  mailbox@10330000 (mediatek,mt8188-gce): 'clock-names' is a required property
     11  mailbox@10320000 (mediatek,mt8188-gce): 'clock-names' is a required property
     11  clock-controller@160af000 (mediatek,mt8188-camsys-yuvb): '#reset-cells' is a required property
     11  clock-controller@1608f000 (mediatek,mt8188-camsys-rawb): '#reset-cells' is a required property
     11  clock-controller@1606f000 (mediatek,mt8188-camsys-yuva): '#reset-cells' is a required property
     11  clock-controller@1604f000 (mediatek,mt8188-camsys-rawa): '#reset-cells' is a required property
     11  clock-controller@15620000 (mediatek,mt8188-imgsys-wpe3): '#reset-cells' is a required property
     11  clock-controller@15520000 (mediatek,mt8188-imgsys-wpe2): '#reset-cells' is a required property
     11  clock-controller@15330000 (mediatek,mt8188-ipesys): '#reset-cells' is a required property

arch/arm64/boot/dts/mediatek:27
['dlg,da9211']
['marvell,sd8897-bt']
['mediatek,mt2712-pcie']
['mediatek,mt2712-scpsys', 'syscon']
['mediatek,mt6331-regulator']
['mediatek,mt6380-regulator']
['mediatek,mt6779-audio', 'syscon']
['mediatek,mt6795-timer', 'mediatek,mt6577-timer']
['mediatek,mt6797-scpsys']
['mediatek,mt7622-pcie']
['mediatek,mt7622-scpsys', 'syscon']
['mediatek,mt8173-afe-pcm']
['mediatek,mt8173-mdp-rdma', 'mediatek,mt8173-mdp']
['mediatek,mt8173-mdp-rdma']
['mediatek,mt8173-mdp-rsz']
['mediatek,mt8173-mdp-wdma']
['mediatek,mt8173-mdp-wrot']
['mediatek,mt8173-rt5650']
['mediatek,mt8173-vpu']
['mediatek,mt8183-audio']
['mediatek,mt8183-audiosys', 'syscon']
['mediatek,mt8183_da7219_max98357']
['mediatek,mt8183_da7219_rt1015p']
['mediatek,mt8183_mt6358_ts3a227_max98357']
['mediatek,mt8183_mt6358_ts3a227_rt1015p']
['melfas,mip4_ts']
['winbond,w25q64jwm', 'jedec,spi-nor']

[PATCH v1 2/3] clk: mediatek: Add main clocks drivers for Dimensity 1200 MT6893

[AngeloGioacchino Del Regno]

Add drivers for the main system clock controllers present in the
MediaTek Dimensity 1200 (MT6893) SoC.
This adds support for the PLLs and topck/infra muxes and gates.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/Kconfig                 |   9 +
 drivers/clk/mediatek/Makefile                |   3 +
 drivers/clk/mediatek/clk-mt6893-apmixedsys.c | 137 +++
 drivers/clk/mediatek/clk-mt6893-infra_ao.c   | 185 ++++
 drivers/clk/mediatek/clk-mt6893-topckgen.c   | 880 +++++++++++++++++++
 5 files changed, 1214 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt6893-apmixedsys.c
 create mode 100644 drivers/clk/mediatek/clk-mt6893-infra_ao.c
 create mode 100644 drivers/clk/mediatek/clk-mt6893-topckgen.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 5f8e6d68fa14..64204e07ed47 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -373,6 +373,15 @@ config COMMON_CLK_MT6797_VENCSYS
 	help
 	  This driver supports MediaTek MT6797 vencsys clocks.
 
+config COMMON_CLK_MT6893
+	tristate "System clock driver for MediaTek Dimensity 1200 MT6893"
+	depends on ARM64 || COMPILE_TEST
+	select COMMON_CLK_MEDIATEK
+	select COMMON_CLK_MEDIATEK_FHCTL
+	default ARM64
+	help
+	  This driver supports MediaTek Dimensity 1200 MT6893 basic clocks.
+
 config COMMON_CLK_MT7622
 	tristate "Clock driver for MediaTek MT7622"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 6efec95406bd..b9b101eceda0 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -34,6 +34,9 @@ obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o
 obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o
 obj-$(CONFIG_COMMON_CLK_MT6797_VDECSYS) += clk-mt6797-vdec.o
 obj-$(CONFIG_COMMON_CLK_MT6797_VENCSYS) += clk-mt6797-venc.o
+obj-$(CONFIG_COMMON_CLK_MT6893) += clk-mt6893-apmixedsys.o clk-mt6893-topckgen.o \
+				   clk-mt6893-infra_ao.o
+
 obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
 obj-$(CONFIG_COMMON_CLK_MT2701_AUDSYS) += clk-mt2701-aud.o
 obj-$(CONFIG_COMMON_CLK_MT2701_BDPSYS) += clk-mt2701-bdp.o
diff --git a/drivers/clk/mediatek/clk-mt6893-apmixedsys.c b/drivers/clk/mediatek/clk-mt6893-apmixedsys.c
new file mode 100644
index 000000000000..044f275acd4f
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6893-apmixedsys.c
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 Collabora Ltd
+ *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mediatek,mt6893-clk.h>
+
+#include "clk-fhctl.h"
+#include "clk-mtk.h"
+#include "clk-pll.h"
+#include "clk-pllfh.h"
+
+#define MT6893_PLL_FMAX		(3800UL * MHZ)
+#define MT6893_PLL_FMIN		(1500UL * MHZ)
+#define MT6893_INTEGER_BITS	(8)
+
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags,		\
+	     _rst_bar_mask, _pcwbits, _pd_reg,				\
+	     _tuner_reg, _tuner_en_reg, _tuner_en_bit, _pcw_reg) {	\
+		.id = _id,						\
+		.name = _name,						\
+		.reg = _reg,						\
+		.pwr_reg = _pwr_reg,					\
+		.en_mask = _en_mask,					\
+		.flags = _flags,					\
+		.rst_bar_mask = _rst_bar_mask,				\
+		.fmax = MT6893_PLL_FMAX,				\
+		.fmin = MT6893_PLL_FMIN,				\
+		.pcwbits = _pcwbits,					\
+		.pcwibits = MT6893_INTEGER_BITS,			\
+		.pd_reg = _pd_reg,					\
+		.pd_shift = 24,						\
+		.tuner_reg = _tuner_reg,				\
+		.tuner_en_reg = _tuner_en_reg,				\
+		.tuner_en_bit = _tuner_en_bit,				\
+		.pcw_reg = _pcw_reg,					\
+		.pcw_shift = 0,						\
+		.pcw_chg_reg = 0,					\
+		.en_reg = 0,						\
+		.pll_en_bit = 0,					\
+	}
+
+static const struct mtk_pll_data plls[] = {
+	/*
+	 * armpll_ll/armpll_bl(x)/ccipll are main clock source of AP MCU,
+	 * should not be closed in Linux world.
+	 */
+	PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x208, 0x214, 0,
+	    PLL_AO, BIT(0), 22, 0x020c, 0, 0, 0, 0x20c),
+	PLL(CLK_APMIXED_ARMPLL_BL0, "armpll_bl0", 0x218, 0x224, 0,
+	    PLL_AO, BIT(0), 22, 0x021c, 0, 0, 0, 0x21c),
+	PLL(CLK_APMIXED_ARMPLL_BL1, "armpll_bl1", 0x228, 0x234, 0,
+	    PLL_AO, BIT(0), 22, 0x022c, 0, 0, 0, 0x22c),
+	PLL(CLK_APMIXED_ARMPLL_BL2, "armpll_bl2", 0x238, 0x244, 0,
+	    PLL_AO, BIT(0), 22, 0x023c, 0, 0, 0, 0x23c),
+	PLL(CLK_APMIXED_ARMPLL_BL3, "armpll_bl3", 0x248, 0x254, 0,
+	    PLL_AO, BIT(0), 22, 0x024c, 0, 0, 0, 0x24c),
+	PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x258, 0x264, 0,
+	    PLL_AO, BIT(0), 22, 0x025c, 0, 0, 0, 0x25c),
+	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x340, 0x34c, GENMASK(31, 24),
+	    HAVE_RST_BAR | PLL_AO, BIT(23), 22, 0x0344, 0, 0, 0, 0x344),
+	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x308, 0x314, GENMASK(31, 24),
+	    HAVE_RST_BAR, BIT(23), 22, 0x030c, 0, 0, 0, 0x30c),
+	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x350, 0x35c, 0,
+	    0, BIT(0), 22, 0x354, 0, 0, 0, 0x354),
+	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x360, 0x36c, GENMASK(31, 24),
+	    HAVE_RST_BAR, BIT(23), 22, 0x364, 0, 0, 0, 0x364),
+	PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x370, 0x37c, 0,
+	    0, BIT(0), 22, 0x374, 0, 0, 0, 0x374),
+	PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x268, 0x274, 0,
+	    0, BIT(0), 22, 0x26c, 0, 0, 0, 0x26c),
+	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x380, 0x38c, 0,
+	    0, BIT(0), 22, 0x384, 0, 0, 0, 0x384),
+	PLL(CLK_APMIXED_APLL1, "apll1", 0x318, 0x328, 0,
+	    0, BIT(0), 32, 0x31c, 0x040, 0x00c, 0, 0x320),
+	PLL(CLK_APMIXED_APLL2, "apll2", 0x32c, 0x33c, 0,
+	    0, BIT(0), 32, 0x330, 0x044, 0x00c, 5, 0x334),
+	PLL(CLK_APMIXED_MPLL, "mpll", 0x32c, 0x39c, 0,
+	    PLL_AO, BIT(0), 22, 0x394, 0, 0, 0, 0x394),
+	PLL(CLK_APMIXED_APUPLL, "apupll", 0x3a0, 0x3ac, 0,
+	    0, BIT(0), 22, 0x3a4, 0, 0, 0, 0x3a4),
+};
+
+static const struct of_device_id of_match_clk_mt6893_apmixed[] = {
+	{ .compatible = "mediatek,mt6893-apmixedsys", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt6893_apmixed);
+
+static int clk_mt6893_apmixed_probe(struct platform_device *pdev)
+{
+	struct clk_hw_onecell_data *clk_data;
+	struct device_node *node = pdev->dev.of_node;
+	int ret;
+
+	clk_data = mtk_devm_alloc_clk_data(&pdev->dev, ARRAY_SIZE(plls));
+	if (!clk_data)
+		return -ENOMEM;
+
+	ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+	if (ret)
+		return ret;
+
+	ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+	if (ret)
+		return ret;
+
+	platform_set_drvdata(pdev, clk_data);
+
+	return 0;
+}
+
+static void clk_mt6893_apmixed_remove(struct platform_device *pdev)
+{
+	struct device_node *node = pdev->dev.of_node;
+	struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
+
+	of_clk_del_provider(node);
+	mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
+}
+
+static struct platform_driver clk_mt6893_apmixed_drv = {
+	.probe = clk_mt6893_apmixed_probe,
+	.remove = clk_mt6893_apmixed_remove,
+	.driver = {
+		.name = "clk-mt6893-apmixed",
+		.of_match_table = of_match_clk_mt6893_apmixed,
+	},
+};
+module_platform_driver(clk_mt6893_apmixed_drv);
+
+MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
+MODULE_DESCRIPTION("MediaTek MT6893 apmixedsys clocks driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/clk-mt6893-infra_ao.c b/drivers/clk/mediatek/clk-mt6893-infra_ao.c
new file mode 100644
index 000000000000..bc73e5d2146f
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6893-infra_ao.c
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 Collabora Ltd
+ *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#include <dt-bindings/clock/mediatek,mt6893-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs infra_ao0_cg_regs = {
+	.set_ofs = 0x80,
+	.clr_ofs = 0x84,
+	.sta_ofs = 0x90,
+};
+
+static const struct mtk_gate_regs infra_ao1_cg_regs = {
+	.set_ofs = 0x88,
+	.clr_ofs = 0x8c,
+	.sta_ofs = 0x94,
+};
+
+static const struct mtk_gate_regs infra_ao2_cg_regs = {
+	.set_ofs = 0xd0,
+	.clr_ofs = 0xd4,
+	.sta_ofs = 0xd8,
+};
+
+static const struct mtk_gate_regs infra_ao3_cg_regs = {
+	.set_ofs = 0xa4,
+	.clr_ofs = 0xa8,
+	.sta_ofs = 0xac,
+};
+
+static const struct mtk_gate_regs infra_ao4_cg_regs = {
+	.set_ofs = 0xc0,
+	.clr_ofs = 0xc4,
+	.sta_ofs = 0xc8,
+};
+
+#define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag)                \
+	GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
+		&mtk_clk_gate_ops_setclr, _flag)
+
+#define GATE_INFRA_AO0(_id, _name, _parent, _shift)	\
+	GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag)		\
+	GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift,	\
+		&mtk_clk_gate_ops_setclr, _flag)
+
+#define GATE_INFRA_AO1(_id, _name, _parent, _shift)	\
+	GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_INFRA_AO2(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &infra_ao2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag)		\
+	GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift,	\
+		&mtk_clk_gate_ops_setclr, _flag)
+
+#define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag)		\
+	GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao3_cg_regs, _shift,	\
+		&mtk_clk_gate_ops_setclr, _flag)
+
+#define GATE_INFRA_AO3(_id, _name, _parent, _shift)	\
+	GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, _flag)		\
+	GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao4_cg_regs, _shift,	\
+		&mtk_clk_gate_ops_setclr, _flag)
+
+#define GATE_INFRA_AO4(_id, _name, _parent, _shift)	\
+	GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, 0)
+
+static const struct mtk_gate infra_ao_clks[] = {
+	/* INFRA_AO0 */
+	GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_TMR, "infra_ao_pmic_tmr", "pwrap_ulposc_sel", 0),
+	GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_AP, "infra_ao_pmic_ap", "pwrap_ulposc_sel", 1),
+	GATE_INFRA_AO0(CLK_INFRA_AO_GCE, "infra_ao_gce", "axi_sel", 8),
+	GATE_INFRA_AO0(CLK_INFRA_AO_GCE2, "infra_ao_gce2", "axi_sel", 9),
+	GATE_INFRA_AO0(CLK_INFRA_AO_THERM, "infra_ao_therm", "axi_sel", 10),
+	GATE_INFRA_AO0(CLK_INFRA_AO_I2C0, "infra_ao_i2c0", "i2c_sel", 11),
+	GATE_INFRA_AO0(CLK_INFRA_AO_I2C1, "infra_ao_i2c1", "i2c_sel", 12),
+	GATE_INFRA_AO0(CLK_INFRA_AO_I2C2, "infra_ao_i2c2", "i2c_sel", 13),
+	GATE_INFRA_AO0(CLK_INFRA_AO_I2C3, "infra_ao_i2c3", "i2c_sel", 14),
+	GATE_INFRA_AO0(CLK_INFRA_AO_PWM_HCLK, "infra_ao_pwm_hclk", "axi_sel", 15),
+	GATE_INFRA_AO0(CLK_INFRA_AO_PWM1, "infra_ao_pwm1", "pwm_sel", 16),
+	GATE_INFRA_AO0(CLK_INFRA_AO_PWM2, "infra_ao_pwm2", "pwm_sel", 17),
+	GATE_INFRA_AO0(CLK_INFRA_AO_PWM3, "infra_ao_pwm3", "pwm_sel", 18),
+	GATE_INFRA_AO0(CLK_INFRA_AO_PWM4, "infra_ao_pwm4", "pwm_sel", 19),
+	GATE_INFRA_AO0(CLK_INFRA_AO_PWM, "infra_ao_pwm", "pwm_sel", 21),
+	GATE_INFRA_AO0(CLK_INFRA_AO_UART0, "infra_ao_uart0", "uart_sel", 22),
+	GATE_INFRA_AO0(CLK_INFRA_AO_UART1, "infra_ao_uart1", "uart_sel", 23),
+	GATE_INFRA_AO0(CLK_INFRA_AO_UART2, "infra_ao_uart2", "uart_sel", 24),
+	GATE_INFRA_AO0(CLK_INFRA_AO_UART3, "infra_ao_uart3", "uart_sel", 25),
+	GATE_INFRA_AO0(CLK_INFRA_AO_GCE_26M, "infra_ao_gce_26m", "axi_sel", 27),
+	GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, "infra_ao_dma", "axi_sel", 28),
+	GATE_INFRA_AO0(CLK_INFRA_AO_BTIF, "infra_ao_btif", "axi_sel", 31),
+	/* INFRA_AO1 */
+	GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "spi_sel", 1),
+	GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, "infra_ao_msdc0", "axi_sel", 2),
+	GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, "infra_ao_msdc1", "axi_sel", 4),
+	GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0_SRC, "infra_ao_msdc0_clk", "msdc50_0_sel", 6),
+	GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC, "infra_ao_auxadc", "clk26m", 10),
+	GATE_INFRA_AO1(CLK_INFRA_AO_CPUM, "infra_ao_cpum", "axi_sel", 11),
+	GATE_INFRA_AO1(CLK_INFRA_AO_CCIF1_AP, "infra_ao_ccif1_ap", "axi_sel", 12),
+	GATE_INFRA_AO1(CLK_INFRA_AO_CCIF1_MD, "infra_ao_ccif1_md", "axi_sel", 13),
+	GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1_SRC, "infra_ao_msdc1_clk", "msdc30_1_sel", 16),
+	GATE_INFRA_AO1(CLK_INFRA_AO_AP_DMA_PS, "infra_ao_ap_dma_ps", "axi_sel", 18),
+	GATE_INFRA_AO1(CLK_INFRA_AO_DEVICE_APC, "infra_ao_dapc", "axi_sel", 20),
+	GATE_INFRA_AO1(CLK_INFRA_AO_CCIF_AP, "infra_ao_ccif_ap", "axi_sel", 23),
+	GATE_INFRA_AO1(CLK_INFRA_AO_AUDIO, "infra_ao_audio", "axi_sel", 25),
+	GATE_INFRA_AO1(CLK_INFRA_AO_CCIF_MD, "infra_ao_ccif_md", "axi_sel", 26),
+	GATE_INFRA_AO1(CLK_INFRA_AO_DXCC_SEC_CORE, "infra_ao_secore", "dxcc_sel", 27),
+	/* INFRA_AO2 */
+	GATE_INFRA_AO2(CLK_INFRA_AO_APDMA, "infra_ao_apdma", "infra_ao_ap_dma_ps", 31),
+	/* INFRA_AO3 */
+	GATE_INFRA_AO3(CLK_INFRA_AO_SSUSB, "infra_ao_ssusb", "usb_sel", 1),
+	GATE_INFRA_AO3(CLK_INFRA_AO_DISP_PWM, "infra_ao_disp_pwm", "disp_pwm_sel", 2),
+	GATE_INFRA_AO3(CLK_INFRA_AO_DPMAIF, "infra_ao_dpmaif_ck", "axi_sel", 3),
+	GATE_INFRA_AO3(CLK_INFRA_AO_AUDIO_26M_BCLK, "infra_ao_audio26m", "clk26m", 4),
+	GATE_INFRA_AO3(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "spi_sel", 6),
+	GATE_INFRA_AO3(CLK_INFRA_AO_I2C4, "infra_ao_i2c4", "i2c_sel", 7),
+	GATE_INFRA_AO3(CLK_INFRA_AO_SPI2, "infra_ao_spi2", "spi_sel", 9),
+	GATE_INFRA_AO3(CLK_INFRA_AO_SPI3, "infra_ao_spi3", "spi_sel", 10),
+	GATE_INFRA_AO3(CLK_INFRA_AO_UNIPRO_SYSCLK, "infra_ao_unipro_sysclk", "ufs_sel", 11),
+	GATE_INFRA_AO3(CLK_INFRA_AO_UFS_MP_SAP_BCLK, "infra_ao_ufs_bclk", "clk26m", 13),
+	GATE_INFRA_AO3(CLK_INFRA_AO_I2C5, "infra_ao_i2c5", "i2c_sel", 18),
+	GATE_INFRA_AO3(CLK_INFRA_AO_I2C5_ARBITER, "infra_ao_i2c5a", "i2c_sel", 19),
+	GATE_INFRA_AO3(CLK_INFRA_AO_I2C5_IMM, "infra_ao_i2c5_imm", "i2c_sel", 20),
+	GATE_INFRA_AO3(CLK_INFRA_AO_I2C1_ARBITER, "infra_ao_i2c1a", "i2c_sel", 21),
+	GATE_INFRA_AO3(CLK_INFRA_AO_I2C1_IMM, "infra_ao_i2c1_imm", "i2c_sel", 22),
+	GATE_INFRA_AO3(CLK_INFRA_AO_I2C2_ARBITER, "infra_ao_i2c2a", "i2c_sel", 23),
+	GATE_INFRA_AO3(CLK_INFRA_AO_I2C2_IMM, "infra_ao_i2c2_imm", "i2c_sel", 24),
+	GATE_INFRA_AO3(CLK_INFRA_AO_SPI4, "infra_ao_spi4", "spi_sel", 25),
+	GATE_INFRA_AO3(CLK_INFRA_AO_SPI5, "infra_ao_spi5", "spi_sel", 26),
+	GATE_INFRA_AO3(CLK_INFRA_AO_CQ_DMA, "infra_ao_cq_dma", "axi_sel", 27),
+	GATE_INFRA_AO3(CLK_INFRA_AO_UFS, "infra_ao_ufs", "ufs_sel", 28),
+	GATE_INFRA_AO3(CLK_INFRA_AO_AES, "infra_ao_aes", "aes_ufsfde_sel", 29),
+	GATE_INFRA_AO3(CLK_INFRA_AO_SSUSB_XHCI, "infra_ao_ssusb_xhci", "ssusb_xhci_sel", 31),
+	/* INFRA_AO4 */
+	GATE_INFRA_AO4(CLK_INFRA_AO_MSDC0_SELF, "infra_ao_msdc0sf", "msdc50_0_sel", 0),
+	GATE_INFRA_AO4(CLK_INFRA_AO_MSDC1_SELF, "infra_ao_msdc1sf", "msdc50_0_sel", 1),
+	GATE_INFRA_AO4(CLK_INFRA_AO_MSDC2_SELF, "infra_ao_msdc2sf", "msdc50_0_sel", 2),
+	GATE_INFRA_AO4(CLK_INFRA_AO_I2C6, "infra_ao_i2c6", "i2c_sel", 6),
+	GATE_INFRA_AO4(CLK_INFRA_AO_AP_MSDC0, "infra_ao_ap_msdc0", "axi_sel", 7),
+	GATE_INFRA_AO4(CLK_INFRA_AO_MD_MSDC0, "infra_ao_md_msdc0", "axi_sel", 8),
+	GATE_INFRA_AO4(CLK_INFRA_AO_I2C7, "infra_ao_i2c7", "i2c_sel", 22),
+	GATE_INFRA_AO4(CLK_INFRA_AO_I2C8, "infra_ao_i2c8", "i2c_sel", 23),
+	GATE_INFRA_AO4(CLK_INFRA_AO_FBIST2FPC, "infra_ao_fbist2fpc", "msdc50_0_sel", 24),
+	GATE_INFRA_AO4_FLAGS(CLK_INFRA_AO_DEVICE_DAPC_SYNC, "infra_ao_dapc_sync", "axi_sel", 25,
+			     CLK_IS_CRITICAL),
+	GATE_INFRA_AO4(CLK_INFRA_AO_DPMAIF_MAIN, "infra_ao_dpmaif_main", "dpmaif_main_sel", 26),
+	GATE_INFRA_AO4(CLK_INFRA_AO_SPI6_CK, "infra_ao_spi6_ck", "spi_sel", 30),
+	GATE_INFRA_AO4(CLK_INFRA_AO_SPI7_CK, "infra_ao_spi7_ck", "spi_sel", 31),
+};
+
+static const struct mtk_clk_desc infra_ao_desc = {
+	.clks = infra_ao_clks,
+	.num_clks = ARRAY_SIZE(infra_ao_clks),
+};
+
+static const struct of_device_id of_match_clk_mt6893_infra_ao[] = {
+	{ .compatible = "mediatek,mt6893-infracfg-ao", .data = &infra_ao_desc },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt6893_infra_ao);
+
+static struct platform_driver clk_mt6893_infra_ao_drv = {
+	.probe = mtk_clk_simple_probe,
+	.remove = mtk_clk_simple_remove,
+	.driver = {
+		.name = "clk-mt6893-infra_ao",
+		.of_match_table = of_match_clk_mt6893_infra_ao,
+	},
+};
+module_platform_driver(clk_mt6893_infra_ao_drv);
+
+MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
+MODULE_DESCRIPTION("MediaTek MT6893 infracfg clocks driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/clk-mt6893-topckgen.c b/drivers/clk/mediatek/clk-mt6893-topckgen.c
new file mode 100644
index 000000000000..69039623938e
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6893-topckgen.c
@@ -0,0 +1,880 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Copyright (c) 2025 Collabora Ltd.
+ *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#include <dt-bindings/clock/mediatek,mt6893-clk.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+#include "clk-mux.h"
+
+static DEFINE_SPINLOCK(mt6893_clk_lock);
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+	FIXED_CLK(CLK_TOP_ULPOSC, "ulposc", NULL, 260000000),
+};
+
+static const struct mtk_fixed_factor top_divs[] = {
+	FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
+	FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
+	FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll", 1, 8),
+	FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll", 1, 16),
+	FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll", 1, 32),
+	FACTOR(CLK_TOP_MAINPLL_D4_D16, "mainpll_d4_d16", "mainpll", 1, 64),
+	FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
+	FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll", 1, 10),
+	FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll", 1, 20),
+	FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll", 1, 40),
+	FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
+	FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll", 1, 12),
+	FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll", 1, 24),
+	FACTOR(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8", "mainpll", 1, 48),
+	FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
+	FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll", 1, 14),
+	FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll", 1, 28),
+	FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll", 1, 56),
+	FACTOR(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll", 1, 9),
+	FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
+	FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
+	FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
+	FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll", 1, 8),
+	FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll", 1, 16),
+	FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll", 1, 32),
+	FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
+	FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll", 1, 10),
+	FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll", 1, 20),
+	FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll", 1, 40),
+	FACTOR(CLK_TOP_UNIVPLL_D5_D16, "univpll_d5_d16", "univpll", 1, 80),
+	FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
+	FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll", 1, 12),
+	FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll", 1, 24),
+	FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll", 1, 48),
+	FACTOR(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll", 1, 96),
+	FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
+	FACTOR(CLK_TOP_UNIVPLL_D7_D2, "univpll_d7_d2", "univpll", 1, 14),
+	FACTOR(CLK_TOP_UNIVPLL_192M_D2, "univpll_192m_d2", "univpll", 1, 26),
+	FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll", 1, 52),
+	FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll", 1, 104),
+	FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll", 1, 208),
+	FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll", 1, 416),
+	FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck", "univpll", 1, 13),
+	FACTOR(CLK_TOP_USB20_PLL_D2, "usb20_pll_d2", "univpll", 1, 26),
+	FACTOR(CLK_TOP_USB20_PLL_D4, "usb20_pll_d4", "univpll", 1, 52),
+	FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2),
+	FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4),
+	FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
+	FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
+	FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
+	FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
+	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
+	FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8),
+	FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1, 4),
+	FACTOR(CLK_TOP_ADSPPLL_D5, "adsppll_d5", "adsppll", 1, 5),
+	FACTOR(CLK_TOP_ADSPPLL_D6, "adsppll_d6", "adsppll", 1, 6),
+	FACTOR(CLK_TOP_MMPLL_D3, "mmpll_d3", "mmpll", 1, 3),
+	FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
+	FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll", 1, 8),
+	FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll", 1, 16),
+	FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
+	FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll", 1, 10),
+	FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll", 1, 20),
+	FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
+	FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12),
+	FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
+	FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll", 1, 9),
+	FACTOR(CLK_TOP_APUPLL_D2, "apupll_d2", "apupll", 1, 2),
+	FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
+	FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
+	FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8),
+	FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16),
+	FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
+	FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
+	FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
+	FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
+	FACTOR(CLK_TOP_OSC_D2, "osc_d2", "ulposc", 1, 2),
+	FACTOR(CLK_TOP_OSC_D4, "osc_d4", "ulposc", 1, 4),
+	FACTOR(CLK_TOP_OSC_D8, "osc_d8", "ulposc", 1, 8),
+	FACTOR(CLK_TOP_OSC_D16, "osc_d16", "ulposc", 1, 16),
+	FACTOR(CLK_TOP_OSC_D10, "osc_d10", "ulposc", 1, 10),
+	FACTOR(CLK_TOP_OSC_D20, "osc_d20", "ulposc", 1, 20),
+	FACTOR(CLK_TOP_TVDPLL_MAINPLL_D2, "tvdpll_mainpll_d2_ck", "mainpll", 1, 2),
+};
+
+static const char * const axi_parents[] = {
+	"clk26m",
+	"mainpll_d4_d4",
+	"mainpll_d7_d2",
+	"mainpll_d4_d2",
+	"mainpll_d5_d2",
+	"mainpll_d6_d2",
+	"osc_d4"
+};
+
+static const char * const spm_parents[] = {
+	"clk26m",
+	"osc_d10",
+	"mainpll_d7_d4",
+	"clk32k"
+};
+
+static const char * const scp_parents[] = {
+	"clk26m",
+	"univpll_d5",
+	"mainpll_d6_d2",
+	"mainpll_d6",
+	"univpll_d6",
+	"mainpll_d4_d2",
+	"mainpll_d5_d2",
+	"univpll_d4_d2"
+};
+
+static const char * const bus_aximem_parents[] = {
+	"clk26m",
+	"mainpll_d7_d2",
+	"mainpll_d4_d2",
+	"mainpll_d5_d2",
+	"mainpll_d6"
+};
+
+static const char * const disp_parents[] = {
+	"clk26m",
+	"univpll_d6_d2",
+	"mainpll_d5_d2",
+	"mmpll_d6_d2",
+	"univpll_d5_d2",
+	"univpll_d4_d2",
+	"mmpll_d7",
+	"univpll_d6",
+	"mainpll_d4",
+	"mmpll_d5_d2"
+};
+
+static const char * const mdp_parents[] = {
+	"clk26m",
+	"mainpll_d5_d2",
+	"mmpll_d6_d2",
+	"mainpll_d4_d2",
+	"univpll_d4_d2",
+	"mainpll_d6",
+	"univpll_d6",
+	"mainpll_d4",
+	"tvdpll",
+	"univpll_d4",
+	"mmpll_d5_d2"
+};
+
+static const char * const img_parents[] = {
+	"clk26m",
+	"univpll_d4",
+	"tvdpll",
+	"mainpll_d4",
+	"univpll_d5",
+	"mmpll_d6",
+	"univpll_d6",
+	"mainpll_d6",
+	"mmpll_d4_d2",
+	"mainpll_d4_d2",
+	"mmpll_d6_d2",
+	"mmpll_d5_d2"
+};
+
+static const char * const ipe_parents[] = {
+	"clk26m",
+	"mainpll_d4",
+	"mmpll_d6",
+	"univpll_d6",
+	"mainpll_d6",
+	"univpll_d4_d2",
+	"mainpll_d4_d2",
+	"mmpll_d6_d2",
+	"mmpll_d5_d2"
+};
+
+static const char * const dpe_parents[] = {
+	"clk26m",
+	"mainpll_d4",
+	"mmpll_d6",
+	"univpll_d6",
+	"mainpll_d6",
+	"univpll_d4_d2",
+	"univpll_d5_d2",
+	"mmpll_d6_d2"
+};
+
+static const char * const cam_parents[] = {
+	"clk26m",
+	"mainpll_d4",
+	"mmpll_d6",
+	"univpll_d4",
+	"univpll_d5",
+	"univpll_d6",
+	"mmpll_d7",
+	"univpll_d4_d2",
+	"mainpll_d4_d2",
+	"univpll_d6_d2"
+};
+
+static const char * const ccu_parents[] = {
+	"clk26m",
+	"mainpll_d4",
+	"mmpll_d6",
+	"mainpll_d6",
+	"mmpll_d7",
+	"univpll_d4_d2",
+	"mmpll_d6_d2",
+	"mmpll_d5_d2",
+	"univpll_d5",
+	"univpll_d6_d2"
+};
+
+static const char * const dsp_parents[] = {
+	"clk26m",
+	"mainpll_d4_d4",
+	"univpll_d6_d2",
+	"mainpll_d4_d2",
+	"univpll_d4_d2",
+	"mainpll_d6",
+	"mmpll_d7",
+	"mmpll_d6",
+	"univpll_d5",
+	"mmpll_d5",
+	"tvdpll",
+	"tvdpll_mainpll_d2_ck",
+	"univpll_d4",
+	"mainpll_d3",
+	"apupll_d2",
+	"mmpll_d4"
+};
+
+static const char * const dsp1_parents[] = {
+	"clk26m",
+	"mainpll_d4_d4",
+	"univpll_d6_d2",
+	"mainpll_d4_d2",
+	"univpll_d4_d2",
+	"mainpll_d6",
+	"mmpll_d7",
+	"mmpll_d6",
+	"univpll_d5",
+	"mmpll_d5",
+	"tvdpll",
+	"tvdpll_mainpll_d2_ck",
+	"univpll_d4",
+	"mainpll_d3",
+	"apupll_d2",
+	"univpll_d3"
+};
+
+static const char * const dsp5_parents[] = {
+	"clk26m",
+	"mainpll_d4_d4",
+	"univpll_d6_d2",
+	"mainpll_d4_d2",
+	"univpll_d4_d2",
+	"mainpll_d6",
+	"univpll_d6",
+	"mmpll_d6",
+	"univpll_d5",
+	"mainpll_d4",
+	"tvdpll",
+	"univpll_d4",
+	"mmpll_d4",
+	"mainpll_d3",
+	"univpll_d3",
+	"apupll_d2"
+};
+
+static const char * const dsp7_parents[] = {
+	"clk26m",
+	"mainpll_d4_d4",
+	"univpll_d6_d2",
+	"mainpll_d4_d2",
+	"univpll_d4_d2",
+	"mainpll_d6",
+	"mmpll_d7",
+	"univpll_d6",
+	"mmpll_d6",
+	"univpll_d5",
+	"mmpll_d5",
+	"tvdpll",
+	"tvdpll_mainpll_d2_ck",
+	"univpll_d4",
+	"mainpll_d3",
+	"univpll_d3"
+};
+
+static const char * const ipu_if_parents[] = {
+	"clk26m",
+	"univpll_d6_d4",
+	"mainpll_d4_d4",
+	"univpll_d6_d2",
+	"mainpll_d4_d2",
+	"univpll_d4_d2",
+	"mainpll_d6",
+	"mmpll_d7",
+	"univpll_d6",
+	"mmpll_d6",
+	"univpll_d5",
+	"mmpll_d5",
+	"tvdpll",
+	"tvdpll_mainpll_d2_ck",
+	"univpll_d4",
+	"apupll_d2"
+};
+
+static const char * const mfg_parents[] = {
+	"clk26m",
+	"mfgpll",
+	"univpll_d6",
+	"mainpll_d5_d2"
+};
+
+static const char * const camtg_parents[] = {
+	"clk26m",
+	"univpll_192m_d8",
+	"univpll_d6_d8",
+	"univpll_192m_d4",
+	"univpll_d6_d16",
+	"clk13m",
+	"univpll_192m_d16",
+	"univpll_192m_d32"
+};
+
+static const char * const uart_parents[] = {
+	"clk26m",
+	"univpll_d6_d8"
+};
+
+static const char * const spi_parents[] = {
+	"clk26m",
+	"mainpll_d5_d4",
+	"mainpll_d6_d4",
+	"msdcpll_d4"
+};
+
+static const char * const msdc50_0_h_parents[] = {
+	"clk26m",
+	"mainpll_d4_d2",
+	"mainpll_d6_d2"
+};
+
+static const char * const msdc50_0_parents[] = {
+	"clk26m",
+	"msdcpll",
+	"msdcpll_d2",
+	"univpll_d4_d4",
+	"mainpll_d6_d2",
+	"univpll_d4_d2"
+};
+
+static const char * const msdc30_1_parents[] = {
+	"clk26m",
+	"univpll_d6_d2",
+	"mainpll_d6_d2",
+	"mainpll_d7_d2",
+	"msdcpll_d2"
+};
+
+static const char * const audio_parents[] = {
+	"clk26m",
+	"mainpll_d5_d8",
+	"mainpll_d7_d8",
+	"mainpll_d4_d16"
+};
+
+static const char * const aud_intbus_parents[] = {
+	"clk26m",
+	"mainpll_d4_d4",
+	"mainpll_d7_d4"
+};
+
+static const char * const pwrap_ulposc_parents[] = {
+	"osc_d10",
+	"clk26m",
+	"osc_d4",
+	"osc_d8",
+	"osc_d16"
+};
+
+static const char * const atb_parents[] = {
+	"clk26m",
+	"mainpll_d4_d2",
+	"mainpll_d5_d2"
+};
+
+static const char * const sspm_parents[] = {
+	"clk26m",
+	"mainpll_d5_d2",
+	"univpll_d5_d2",
+	"mainpll_d4_d2",
+	"univpll_d4_d2",
+	"mainpll_d6"
+};
+
+static const char * const dp_parents[] = {
+	"clk26m",
+	"tvdpll_d2",
+	"tvdpll_d4",
+	"tvdpll_d8",
+	"tvdpll_d16"
+};
+
+static const char * const scam_parents[] = {
+	"clk26m",
+	"mainpll_d5_d4"
+};
+
+static const char * const disp_pwm_parents[] = {
+	"clk26m",
+	"univpll_d6_d4",
+	"osc_d2",
+	"osc_d4",
+	"osc_d16"
+};
+
+static const char * const usb_parents[] = {
+	"clk26m",
+	"univpll_d5_d4",
+	"univpll_d6_d4",
+	"univpll_d5_d2"
+};
+
+static const char * const i2c_parents[] = {
+	"clk26m",
+	"mainpll_d4_d8",
+	"univpll_d5_d4"
+};
+
+static const char * const seninf_parents[] = {
+	"clk26m",
+	"univpll_d4_d4",
+	"univpll_d6_d2",
+	"univpll_d4_d2",
+	"univpll_d7",
+	"univpll_d6",
+	"mmpll_d6",
+	"univpll_d5"
+};
+
+static const char * const dxcc_parents[] = {
+	"clk26m",
+	"mainpll_d4_d2",
+	"mainpll_d4_d4",
+	"mainpll_d4_d8"
+};
+
+static const char * const aud_engen1_parents[] = {
+	"clk26m",
+	"apll1_d2",
+	"apll1_d4",
+	"apll1_d8"
+};
+
+static const char * const aud_engen2_parents[] = {
+	"clk26m",
+	"apll2_d2",
+	"apll2_d4",
+	"apll2_d8"
+};
+
+static const char * const aes_ufsfde_parents[] = {
+	"clk26m",
+	"mainpll_d4",
+	"mainpll_d4_d2",
+	"mainpll_d6",
+	"mainpll_d4_d4",
+	"univpll_d4_d2",
+	"univpll_d6"
+};
+
+static const char * const ufs_parents[] = {
+	"clk26m",
+	"mainpll_d4_d4",
+	"mainpll_d4_d8",
+	"univpll_d4_d4",
+	"mainpll_d6_d2",
+	"mainpll_d5_d2",
+	"msdcpll_d2"
+};
+
+static const char * const aud_1_parents[] = {
+	"clk26m",
+	"apll1"
+};
+
+static const char * const aud_2_parents[] = {
+	"clk26m",
+	"apll2"
+};
+
+static const char * const adsp_parents[] = {
+	"clk26m",
+	"mainpll_d6",
+	"mainpll_d5_d2",
+	"univpll_d4_d4",
+	"univpll_d4",
+	"univpll_d6",
+	"adsppll"
+};
+
+static const char * const dpmaif_main_parents[] = {
+	"clk26m",
+	"univpll_d4_d4",
+	"mainpll_d6",
+	"mainpll_d4_d2",
+	"univpll_d4_d2"
+};
+
+static const char * const venc_parents[] = {
+	"clk26m",
+	"mmpll_d7",
+	"mainpll_d6",
+	"univpll_d4_d2",
+	"mainpll_d4_d2",
+	"univpll_d6",
+	"mmpll_d6",
+	"mainpll_d5_d2",
+	"mainpll_d6_d2",
+	"mmpll_d9",
+	"univpll_d4_d4",
+	"mainpll_d4",
+	"univpll_d4",
+	"univpll_d5",
+	"univpll_d5_d2",
+	"tvdpll_mainpll_d2_ck"
+};
+
+static const char * const vdec_parents[] = {
+	"clk26m",
+	"univpll_192m_d2",
+	"univpll_d5_d4",
+	"mainpll_d5",
+	"mainpll_d5_d2",
+	"mmpll_d6_d2",
+	"univpll_d5_d2",
+	"mainpll_d4_d2",
+	"univpll_d4_d2",
+	"univpll_d7",
+	"mmpll_d7",
+	"mmpll_d6",
+	"univpll_d5",
+	"mainpll_d4",
+	"univpll_d4",
+	"univpll_d6"
+};
+
+static const char * const camtm_parents[] = {
+	"clk26m",
+	"univpll_d7",
+	"univpll_d6_d2",
+	"univpll_d4_d2"
+};
+
+static const char * const pwm_parents[] = {
+	"clk26m",
+	"univpll_d4_d8"
+};
+
+static const char * const audio_h_parents[] = {
+	"clk26m",
+	"univpll_d7",
+	"apll1",
+	"apll2"
+};
+
+static const char * const mcupm_parents[] = {
+	"clk26m",
+	"mainpll_d7_d2",
+	"mainpll_d7_d4"
+};
+
+static const char * const spmi_mst_parents[] = {
+	"clk26m",
+	"clk13m",
+	"osc_d8",
+	"osc_d10",
+	"osc_d16",
+	"osc_d20",
+	"clk32k"
+};
+
+static const char * const dvfsrc_parents[] = {
+	"clk26m",
+	"osc_d10"
+};
+
+static const char * const apll_mck_parents[] = {
+	"aud_1_sel",
+	"aud_2_sel"
+};
+
+static const struct mtk_mux top_mtk_muxes[] = {
+	/*
+	 * CLK_CFG_0
+	 * axi_sel and bus_aximem_sel are bus clocks, should not be closed by Linux.
+	 * spm_sel and scp_sel are main clocks in always-on co-processor.
+	 */
+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
+				   0x010, 0x014, 0x018, 0, 3, 7, 0x04, 0,
+				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel", spm_parents,
+				   0x010, 0x014, 0x018, 8, 2, 15, 0x04, 1,
+				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
+				   0x010, 0x014, 0x018, 16, 3, 23, 0x04, 2,
+				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM_SEL, "bus_aximem_sel", bus_aximem_parents,
+				   0x010, 0x014, 0x018, 24, 3, 31, 0x04, 3,
+				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+	/* CLK_CFG_1 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_SEL, "disp_sel",
+			     disp_parents, 0x020, 0x024, 0x028, 0, 4, 7, 0x04, 4),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP_SEL, "mdp_sel",
+			     mdp_parents, 0x020, 0x024, 0x028, 8, 4, 15, 0x04, 5),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1_SEL, "img1_sel",
+			     img_parents, 0x020, 0x024, 0x028, 16, 4, 23, 0x04, 6),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG2_SEL, "img2_sel",
+			     img_parents, 0x020, 0x024, 0x028, 24, 4, 31, 0x04, 7),
+	/* CLK_CFG_2 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, "ipe_sel",
+			     ipe_parents, 0x030, 0x034, 0x038, 0, 4, 7, 0x04, 8),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE_SEL, "dpe_sel",
+			     dpe_parents, 0x030, 0x034, 0x038, 8, 3, 15, 0x04, 9),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL, "cam_sel",
+			     cam_parents, 0x030, 0x034, 0x038, 16, 4, 23, 0x04, 10),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_SEL, "ccu_sel",
+			     ccu_parents, 0x030, 0x034, 0x038, 24, 4, 31, 0x04, 11),
+	/* CLK_CFG_3 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, "dsp_sel",
+			     dsp_parents, 0x040, 0x044, 0x048, 0, 4, 7, 0x04, 12),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1_SEL, "dsp1_sel",
+			     dsp1_parents, 0x040, 0x044, 0x048, 8, 4, 15, 0x04, 13),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2_SEL, "dsp2_sel",
+			     dsp1_parents, 0x040, 0x044, 0x048, 16, 4, 23, 0x04, 14),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3_SEL, "dsp3_sel",
+			     dsp1_parents, 0x040, 0x044, 0x048, 24, 4, 31, 0x04, 15),
+	/* CLK_CFG_4 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP4_SEL, "dsp4_sel",
+			     dsp1_parents, 0x050, 0x054, 0x058, 0, 4, 7, 0x04, 16),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP5_SEL, "dsp5_sel",
+			     dsp5_parents, 0x050, 0x054, 0x058, 8, 4, 15, 0x04, 17),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP6_SEL, "dsp6_sel",
+			     dsp5_parents, 0x050, 0x054, 0x058, 16, 4, 23, 0x04, 18),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7_SEL, "dsp7_sel",
+			     dsp7_parents, 0x050, 0x054, 0x058, 24, 4, 31, 0x04, 19),
+	/* CLK_CFG_5 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF_SEL, "ipu_if_sel",
+			     ipu_if_parents, 0x060, 0x064, 0x068, 0, 4, 7, 0x04, 20),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel",
+			     mfg_parents, 0x060, 0x064, 0x068, 8, 2, 15, 0x04, 21),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
+			     camtg_parents, 0x060, 0x064, 0x068, 16, 3, 23, 0x04, 22),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel",
+			     camtg_parents, 0x060, 0x064, 0x068, 24, 3, 31, 0x04, 23),
+	/* CLK_CFG_6 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel",
+			     camtg_parents, 0x070, 0x074, 0x078, 0, 3, 7, 0x04, 24),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4_SEL, "camtg4_sel",
+			     camtg_parents, 0x070, 0x074, 0x078, 8, 3, 15, 0x04, 25),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel",
+			     uart_parents, 0x070, 0x074, 0x078, 16, 1, 23, 0x04, 26),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel",
+			     spi_parents, 0x070, 0x074, 0x078, 24, 2, 31, 0x04, 27),
+	/* CLK_CFG_7 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel",
+			     msdc50_0_h_parents, 0x080, 0x084, 0x088, 0, 2, 7, 0x04, 28),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
+			     msdc50_0_parents, 0x080, 0x084, 0x088, 8, 3, 15, 0x04, 29),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
+			     msdc30_1_parents, 0x080, 0x084, 0x088, 16, 3, 23, 0x04, 30),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel",
+			     audio_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x08, 0),
+	/* CLK_CFG_8 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
+			     aud_intbus_parents, 0x090, 0x094, 0x098, 0, 2, 7, 0x08, 1),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC_SEL, "pwrap_ulposc_sel",
+			     pwrap_ulposc_parents, 0x090, 0x094, 0x098, 8, 3, 15, 0x08, 2),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel",
+			     atb_parents, 0x090, 0x094, 0x098, 16, 2, 23, 0x08, 3),
+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SSPM_SEL, "sspm_sel", sspm_parents,
+				   0x090, 0x094, 0x098, 24, 3, 31, 0x08, 4,
+				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+	/* CLK_CFG_9 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DP_SEL, "dp_sel",
+			     dp_parents, 0x0a0, 0x0a4, 0x0a8, 0, 3, 7, 0x08, 5),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM_SEL, "scam_sel",
+			     scam_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x08, 6),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel",
+			     disp_pwm_parents, 0x0a0, 0x0a4, 0x0a8, 16, 3, 23, 0x08, 7),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL, "usb_sel",
+			     usb_parents, 0x0a0, 0x0a4, 0x0a8, 24, 2, 31, 0x08, 8),
+	/* CLK_CFG_10 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL, "ssusb_xhci_sel",
+			     usb_parents, 0x0b0, 0x0b4, 0x0b8, 0, 2, 7, 0x08, 9),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel",
+			     i2c_parents, 0x0b0, 0x0b4, 0x0b8, 8, 2, 15, 0x08, 10),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel",
+			     seninf_parents, 0x0b0, 0x0b4, 0x0b8, 16, 3, 23, 0x08, 11),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1_SEL, "seninf1_sel",
+			     seninf_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, 0x08, 12),
+	/* CLK_CFG_11 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2_SEL, "seninf2_sel",
+			     seninf_parents, 0x0c0, 0x0c4, 0x0c8, 0, 3, 7, 0x08, 13),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3_SEL, "seninf3_sel",
+			     seninf_parents, 0x0c0, 0x0c4, 0x0c8, 8, 3, 15, 0x08, 14),
+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents,
+				   0x0c0, 0x0c4, 0x0c8, 16, 2, 23, 0x08, 15,
+				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
+			     aud_engen1_parents, 0x0c0, 0x0c4, 0x0c8, 24, 2, 31, 0x08, 16),
+	/* CLK_CFG_12 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel",
+			     aud_engen2_parents, 0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x08, 17),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE_SEL, "aes_ufsfde_sel",
+			     aes_ufsfde_parents, 0x0d0, 0x0d4, 0x0d8, 8, 3, 15, 0x08, 18),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_SEL, "ufs_sel",
+			     ufs_parents, 0x0d0, 0x0d4, 0x0d8, 16, 3, 23, 0x08, 19),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel",
+			     aud_1_parents, 0x0d0, 0x0d4, 0x0d8, 24, 1, 31, 0x08, 20),
+	/* CLK_CFG_13 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel",
+			     aud_2_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7, 0x08, 21),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP_SEL, "adsp_sel",
+			     adsp_parents, 0x0e0, 0x0e4, 0x0e8, 8, 3, 15, 0x08, 22),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN_SEL, "dpmaif_main_sel",
+			     dpmaif_main_parents, 0x0e0, 0x0e4, 0x0e8, 16, 3, 23, 0x08, 23),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, "venc_sel",
+			     venc_parents, 0x0e0, 0x0e4, 0x0e8, 24, 4, 31, 0x08, 24),
+	/* CLK_CFG_14 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, "vdec_sel",
+			     vdec_parents, 0x0f0, 0x0f4, 0x0f8, 0, 4, 7, 0x08, 25),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_LAT_SEL, "vdec_lat_sel",
+			     vdec_parents, 0x0f0, 0x0f4, 0x0f8, 8, 4, 15, 0x08, 26),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel",
+			     camtm_parents, 0x0f0, 0x0f4, 0x0f8, 16, 2, 23, 0x08, 27),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel",
+			     pwm_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1, 31, 0x08, 28),
+	/* CLK_CFG_15 */
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H_SEL, "audio_h_sel",
+			     audio_h_parents, 0x100, 0x104, 0x108, 0, 2, 7, 0x08, 29),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5_SEL, "camtg5_sel",
+			     camtg_parents, 0x100, 0x104, 0x108, 8, 3, 15, 0x0c, 30),
+	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG6_SEL, "camtg6_sel",
+			     camtg_parents, 0x100, 0x104, 0x108, 16, 3, 23, 0x0c, 0),
+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MCUPM_SEL, "mcupm_sel", mcupm_parents,
+				   0x100, 0x104, 0x108, 24, 2, 31, 0x0c, 1,
+				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+	/* CLK_CFG_16 */
+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPMI_MST_SEL, "spmi_mst_sel", spmi_mst_parents,
+				   0x110, 0x114, 0x118, 0, 3, 7, 0x0c, 2,
+				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DVFSRC_SEL, "dvfsrc_sel", dvfsrc_parents,
+				   0x110, 0x114, 0x118, 8, 1, 15, 0x0c, 3,
+				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+};
+
+static const struct mtk_clk_divider top_adj_divs[] = {
+	DIV_ADJ(CLK_TOP_APLL1_CK_DIV0, "apll1_div0", "aud_engen1_sel", 0x320, 24, 4),
+	DIV_ADJ(CLK_TOP_APLL2_CK_DIV0, "apll2_div0", "aud_engen2_sel", 0x320, 28, 4),
+};
+
+static const struct mtk_composite top_composites[] = {
+	MUX(CLK_TOP_APLL_I2S0_MCK_SEL, "apll_i2s0_mck_sel", apll_mck_parents, 0x320, 8, 1),
+	MUX(CLK_TOP_APLL_I2S1_MCK_SEL, "apll_i2s1_mck_sel", apll_mck_parents, 0x320, 9, 1),
+	MUX(CLK_TOP_APLL_I2S2_MCK_SEL, "apll_i2s2_mck_sel", apll_mck_parents, 0x320, 10, 1),
+	MUX(CLK_TOP_APLL_I2S3_MCK_SEL, "apll_i2s3_mck_sel", apll_mck_parents, 0x320, 11, 1),
+	MUX(CLK_TOP_APLL_I2S4_MCK_SEL, "apll_i2s4_mck_sel", apll_mck_parents, 0x320, 12, 1),
+	MUX(CLK_TOP_APLL_I2S5_MCK_SEL, "apll_i2s5_mck_sel", apll_mck_parents, 0x328, 20, 1),
+	MUX(CLK_TOP_APLL_I2S6_MCK_SEL, "apll_i2s6_mck_sel", apll_mck_parents, 0x334, 24, 1),
+	MUX(CLK_TOP_APLL_I2S7_MCK_SEL, "apll_i2s7_mck_sel", apll_mck_parents, 0x334, 25, 1),
+	MUX(CLK_TOP_APLL_I2S8_MCK_SEL, "apll_i2s8_mck_sel", apll_mck_parents, 0x334, 26, 1),
+	MUX(CLK_TOP_APLL_I2S9_MCK_SEL, "apll_i2s9_mck_sel", apll_mck_parents, 0x334, 27, 1),
+
+	DIV_GATE(CLK_TOP_APLL12_CK_DIV0, "apll12_div0", "apll_i2s0_mck_sel",
+		 0x320, 2, 0x324, 8, 0),
+	DIV_GATE(CLK_TOP_APLL12_CK_DIV1, "apll12_div1", "apll_i2s1_mck_sel",
+		 0x320, 3, 0x324, 8, 8),
+	DIV_GATE(CLK_TOP_APLL12_CK_DIV2, "apll12_div2", "apll_i2s2_mck_sel",
+		 0x320, 4, 0x324, 8, 16),
+	DIV_GATE(CLK_TOP_APLL12_CK_DIV3, "apll12_div3", "apll_i2s3_mck_sel",
+		 0x320, 5, 0x324, 8, 24),
+	DIV_GATE(CLK_TOP_APLL12_CK_DIV4, "apll12_div4", "apll_i2s4_mck_sel",
+		 0x320, 6, 0x328, 8, 0),
+	DIV_GATE(CLK_TOP_APLL12_CK_DIVB, "apll12_divb", "apll12_div4",
+		 0x320, 7, 0x328, 8, 8),
+	DIV_GATE(CLK_TOP_APLL12_CK_DIV5_LSB, "apll12_div5_lsb", "apll_i2s5_mck_sel",
+		 0x0328, 16, 0x328, 4, 28),
+	DIV_GATE(CLK_TOP_APLL12_CK_DIV5_MSB, "apll12_div5_msb", "apll_i2s5_mck_sel",
+		 0x0328, 16, 0x334, 4, 0),
+	DIV_GATE(CLK_TOP_APLL12_CK_DIV6, "apll12_div6", "apll_i2s6_mck_sel",
+		 0x0334, 20, 0x338, 8, 0),
+	DIV_GATE(CLK_TOP_APLL12_CK_DIV7, "apll12_div7", "apll_i2s7_mck_sel",
+		 0x0334, 21, 0x338, 8, 8),
+	DIV_GATE(CLK_TOP_APLL12_CK_DIV8, "apll12_div8", "apll_i2s8_mck_sel",
+		 0x0334, 22, 0x338, 8, 16),
+	DIV_GATE(CLK_TOP_APLL12_CK_DIV9, "apll12_div9", "apll_i2s9_mck_sel",
+		 0x0334, 23, 0x338, 8, 24),
+};
+
+/* Register mux notifier for MFG mux */
+static int clk_mt6893_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
+{
+	struct mtk_mux_nb *mfg_mux_nb;
+	int i;
+
+	mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL);
+	if (!mfg_mux_nb)
+		return -ENOMEM;
+
+	for (i = 0; i < ARRAY_SIZE(top_mtk_muxes); i++)
+		if (top_mtk_muxes[i].id == CLK_TOP_MFG_SEL)
+			break;
+	if (i == ARRAY_SIZE(top_mtk_muxes))
+		return -EINVAL;
+
+	mfg_mux_nb->ops = top_mtk_muxes[i].ops;
+	mfg_mux_nb->bypass_index = 0; /* Bypass to 26M crystal */
+
+	return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb);
+}
+
+static const struct mtk_clk_desc topck_desc = {
+	.fixed_clks = top_fixed_clks,
+	.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
+	.factor_clks = top_divs,
+	.num_factor_clks = ARRAY_SIZE(top_divs),
+	.mux_clks = top_mtk_muxes,
+	.num_mux_clks = ARRAY_SIZE(top_mtk_muxes),
+	.composite_clks = top_composites,
+	.num_composite_clks = ARRAY_SIZE(top_composites),
+	.divider_clks = top_adj_divs,
+	.num_divider_clks = ARRAY_SIZE(top_adj_divs),
+	.clk_lock = &mt6893_clk_lock,
+	.clk_notifier_func = clk_mt6893_reg_mfg_mux_notifier,
+	.mfg_clk_idx = CLK_TOP_MFG_SEL,
+};
+
+static const struct of_device_id of_match_clk_mt6893_topck[] = {
+	{ .compatible = "mediatek,mt6893-topckgen", .data = &topck_desc },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt6893_topck);
+
+static struct platform_driver clk_mt6893_topck_drv = {
+	.probe = mtk_clk_simple_probe,
+	.remove = mtk_clk_simple_remove,
+	.driver = {
+		.name = "clk-mt6893-topck",
+		.of_match_table = of_match_clk_mt6893_topck,
+	},
+};
+module_platform_driver(clk_mt6893_topck_drv);
+
+MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
+MODULE_DESCRIPTION("MediaTek MT6893 top clock generators driver");
+MODULE_LICENSE("GPL");
-- 
2.49.0

[PATCH v1 3/3] clk: mediatek: mt6893: Add peripheral and multimedia clock drivers

[AngeloGioacchino Del Regno]

Add support for the peripheral (imp_iic_wrap for i2c, scp_adsp for
the System Companion Processor's AudioDSP clock output) and
multimedia clock drivers (Multimedia Data Path, Display, GPU and
video encoders/decoders) that are present in the MediaTek
Dimensity 1200 (MT6893) SoC.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/Kconfig                  |  49 +++++++
 drivers/clk/mediatek/Makefile                 |   7 +
 .../clk/mediatek/clk-mt6893-imp_iic_wrap.c    |  94 +++++++++++++
 drivers/clk/mediatek/clk-mt6893-mdp.c         | 116 ++++++++++++++++
 drivers/clk/mediatek/clk-mt6893-mfg.c         |  51 +++++++
 drivers/clk/mediatek/clk-mt6893-mm.c          | 129 ++++++++++++++++++
 drivers/clk/mediatek/clk-mt6893-scp_adsp.c    |  52 +++++++
 drivers/clk/mediatek/clk-mt6893-vdec.c        |  98 +++++++++++++
 drivers/clk/mediatek/clk-mt6893-venc.c        |  72 ++++++++++
 9 files changed, 668 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt6893-imp_iic_wrap.c
 create mode 100644 drivers/clk/mediatek/clk-mt6893-mdp.c
 create mode 100644 drivers/clk/mediatek/clk-mt6893-mfg.c
 create mode 100644 drivers/clk/mediatek/clk-mt6893-mm.c
 create mode 100644 drivers/clk/mediatek/clk-mt6893-scp_adsp.c
 create mode 100644 drivers/clk/mediatek/clk-mt6893-vdec.c
 create mode 100644 drivers/clk/mediatek/clk-mt6893-venc.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 64204e07ed47..ff8a87112969 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -382,6 +382,55 @@ config COMMON_CLK_MT6893
 	help
 	  This driver supports MediaTek Dimensity 1200 MT6893 basic clocks.
 
+config COMMON_CLK_MT6893_IMP_IIC_WRAP
+	tristate "Clock driver for MediaTek MT6893 imp_iic_wrap"
+	depends on COMMON_CLK_MT6893
+	default COMMON_CLK_MT6893
+	help
+	  This driver supports MediaTek MT6893 imp_iic_wrap clocks.
+
+config COMMON_CLK_MT6893_MDPSYS
+	tristate "Clock driver for MediaTek MT6893 mdpsys"
+	depends on COMMON_CLK_MT6893
+	default COMMON_CLK_MT6893
+	help
+	  This driver supports MediaTek MT6893 mdpsys clocks.
+
+config COMMON_CLK_MT6893_MFGCFG
+	tristate "Clock driver for MediaTek MT6893 mfgcfg"
+	depends on COMMON_CLK_MT6893
+	default COMMON_CLK_MT6893
+	help
+	  This driver supports MediaTek MT6893 mfgcfg clocks.
+
+config COMMON_CLK_MT6893_MMSYS
+	tristate "Clock driver for MediaTek MT6893 mmsys"
+	depends on COMMON_CLK_MT6893
+	default COMMON_CLK_MT6893
+	help
+	  This driver supports MediaTek MT6893 mmsys clocks.
+
+config COMMON_CLK_MT6893_SCP_ADSP
+	tristate "Clock driver for MediaTek MT6893 scp_adsp"
+	depends on COMMON_CLK_MT6893
+	default COMMON_CLK_MT6893
+	help
+	  This driver supports MediaTek MT6893 scp_adsp clocks.
+
+config COMMON_CLK_MT6893_VDECSYS
+	tristate "Clock driver for MediaTek MT6893 vdecsys"
+	depends on COMMON_CLK_MT6893
+	default COMMON_CLK_MT6893
+	help
+	  This driver supports MediaTek MT6893 vdecsys and vdecsys_soc clocks.
+
+config COMMON_CLK_MT6893_VENCSYS
+	tristate "Clock driver for MediaTek MT6893 vencsys"
+	depends on COMMON_CLK_MT6893
+	default COMMON_CLK_MT6893
+	help
+	  This driver supports MediaTek MT6893 vencsys clocks.
+
 config COMMON_CLK_MT7622
 	tristate "Clock driver for MediaTek MT7622"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index b9b101eceda0..73004e318702 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -36,6 +36,13 @@ obj-$(CONFIG_COMMON_CLK_MT6797_VDECSYS) += clk-mt6797-vdec.o
 obj-$(CONFIG_COMMON_CLK_MT6797_VENCSYS) += clk-mt6797-venc.o
 obj-$(CONFIG_COMMON_CLK_MT6893) += clk-mt6893-apmixedsys.o clk-mt6893-topckgen.o \
 				   clk-mt6893-infra_ao.o
+obj-$(CONFIG_COMMON_CLK_MT6893_IMP_IIC_WRAP) += clk-mt6893-imp_iic_wrap.o
+obj-$(CONFIG_COMMON_CLK_MT6893_MDPSYS) += clk-mt6893-mdp.o
+obj-$(CONFIG_COMMON_CLK_MT6893_MFGCFG) += clk-mt6893-mfg.o
+obj-$(CONFIG_COMMON_CLK_MT6893_MMSYS) += clk-mt6893-mm.o
+obj-$(CONFIG_COMMON_CLK_MT6893_SCP_ADSP) += clk-mt6893-scp_adsp.o
+obj-$(CONFIG_COMMON_CLK_MT6893_VDECSYS) += clk-mt6893-vdec.o
+obj-$(CONFIG_COMMON_CLK_MT6893_VENCSYS) += clk-mt6893-venc.o
 
 obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
 obj-$(CONFIG_COMMON_CLK_MT2701_AUDSYS) += clk-mt2701-aud.o
diff --git a/drivers/clk/mediatek/clk-mt6893-imp_iic_wrap.c b/drivers/clk/mediatek/clk-mt6893-imp_iic_wrap.c
new file mode 100644
index 000000000000..49416ba7b768
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6893-imp_iic_wrap.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Copyright (c) 2025 Collabora Ltd
+ *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/mediatek,mt6893-clk.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs imp_iic_wrap_cg_regs = {
+	.set_ofs = 0xe08,
+	.clr_ofs = 0xe04,
+	.sta_ofs = 0xe00,
+};
+
+#define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift)				\
+	GATE_MTK_FLAGS(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift,	\
+		&mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
+
+static const struct mtk_gate imp_iic_wrap_c_clks[] = {
+	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_AP_I2C0, "imp_iic_wrap_c_ap_i2c0", "i2c_sel", 0),
+	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_AP_I2C10, "imp_iic_wrap_c_ap_i2c10", "i2c_sel", 1),
+	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_AP_I2C11, "imp_iic_wrap_c_ap_i2c11", "i2c_sel", 2),
+	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_AP_I2C12, "imp_iic_wrap_c_ap_i2c12", "i2c_sel", 3),
+	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_AP_I2C13, "imp_iic_wrap_c_ap_i2c13", "i2c_sel", 4),
+};
+
+static const struct mtk_gate imp_iic_wrap_e_clks[] = {
+	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_E_AP_I2C3, "imp_iic_wrap_e_ap_i2c3", "i2c_sel", 0),
+	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_E_AP_I2C9, "imp_iic_wrap_e_ap_i2c9", "i2c_sel", 1),
+};
+
+static const struct mtk_gate imp_iic_wrap_n_clks[] = {
+	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_N_AP_I2C5, "imp_iic_wrap_n_ap_i2c5", "i2c_sel", 0),
+	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_N_AP_I2C6, "imp_iic_wrap_n_ap_i2c6", "i2c_sel", 1),
+};
+
+static const struct mtk_gate imp_iic_wrap_s_clks[] = {
+	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_AP_I2C1, "imp_iic_wrap_s_ap_i2c1", "i2c_sel", 0),
+	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_AP_I2C2, "imp_iic_wrap_s_ap_i2c2", "i2c_sel", 1),
+	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_AP_I2C4, "imp_iic_wrap_s_ap_i2c4", "i2c_sel", 2),
+	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_AP_I2C7, "imp_iic_wrap_s_ap_i2c7", "i2c_sel", 3),
+	GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_AP_I2C8, "imp_iic_wrap_s_ap_i2c8", "i2c_sel", 4),
+};
+
+static const struct mtk_clk_desc imp_iic_wrap_c_desc = {
+	.clks = imp_iic_wrap_c_clks,
+	.num_clks = ARRAY_SIZE(imp_iic_wrap_c_clks),
+};
+
+static const struct mtk_clk_desc imp_iic_wrap_e_desc = {
+	.clks = imp_iic_wrap_e_clks,
+	.num_clks = ARRAY_SIZE(imp_iic_wrap_e_clks),
+};
+
+static const struct mtk_clk_desc imp_iic_wrap_n_desc = {
+	.clks = imp_iic_wrap_n_clks,
+	.num_clks = ARRAY_SIZE(imp_iic_wrap_n_clks),
+};
+
+static const struct mtk_clk_desc imp_iic_wrap_s_desc = {
+	.clks = imp_iic_wrap_s_clks,
+	.num_clks = ARRAY_SIZE(imp_iic_wrap_s_clks),
+};
+
+static const struct of_device_id of_match_clk_mt6893_imp_iic_wrap[] = {
+	{ .compatible = "mediatek,mt6893-imp-iic-wrap-c", .data = &imp_iic_wrap_c_desc },
+	{ .compatible = "mediatek,mt6893-imp-iic-wrap-e", .data = &imp_iic_wrap_e_desc },
+	{ .compatible = "mediatek,mt6893-imp-iic-wrap-n", .data = &imp_iic_wrap_n_desc },
+	{ .compatible = "mediatek,mt6893-imp-iic-wrap-s", .data = &imp_iic_wrap_s_desc },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt6893_imp_iic_wrap);
+
+static struct platform_driver clk_mt6893_imp_iic_wrap_drv = {
+	.probe = mtk_clk_simple_probe,
+	.remove = mtk_clk_simple_remove,
+	.driver = {
+		.name = "clk-mt6893-imp_iic_wrap",
+		.of_match_table = of_match_clk_mt6893_imp_iic_wrap,
+	},
+};
+module_platform_driver(clk_mt6893_imp_iic_wrap_drv);
+
+MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
+MODULE_DESCRIPTION("MediaTek MT6893 I2C Wrapper clocks driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/clk-mt6893-mdp.c b/drivers/clk/mediatek/clk-mt6893-mdp.c
new file mode 100644
index 000000000000..73ccded6447a
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6893-mdp.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Copyright (c) 2025 Collabora Ltd
+ *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mediatek,mt6893-clk.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs mdp0_cg_regs = {
+	.set_ofs = 0x104,
+	.clr_ofs = 0x108,
+	.sta_ofs = 0x100,
+};
+
+static const struct mtk_gate_regs mdp1_cg_regs = {
+	.set_ofs = 0x114,
+	.clr_ofs = 0x118,
+	.sta_ofs = 0x110,
+};
+
+static const struct mtk_gate_regs mdp2_cg_regs = {
+	.set_ofs = 0x124,
+	.clr_ofs = 0x128,
+	.sta_ofs = 0x120,
+};
+
+#define GATE_MDP0(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &mdp0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_MDP1(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &mdp1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_MDP2(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &mdp2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate mdp_clks[] = {
+	/* MDP0 */
+	GATE_MDP0(CLK_MDP_RDMA0, "mdp_rdma0", "mdp_sel", 0),
+	GATE_MDP0(CLK_MDP_FG0, "mdp_fg0", "mdp_sel", 1),
+	GATE_MDP0(CLK_MDP_HDR0, "mdp_hdr0", "mdp_sel", 2),
+	GATE_MDP0(CLK_MDP_AAL0, "mdp_aal0", "mdp_sel", 3),
+	GATE_MDP0(CLK_MDP_RSZ0, "mdp_rsz0", "mdp_sel", 4),
+	GATE_MDP0(CLK_MDP_TDSHP0, "mdp_tdshp0", "mdp_sel", 5),
+	GATE_MDP0(CLK_MDP_TCC0, "mdp_tcc0", "mdp_sel", 6),
+	GATE_MDP0(CLK_MDP_WROT0, "mdp_wrot0", "mdp_sel", 7),
+	GATE_MDP0(CLK_MDP_RDMA2, "mdp_rdma2", "mdp_sel", 8),
+	GATE_MDP0(CLK_MDP_AAL2, "mdp_aal2", "mdp_sel", 9),
+	GATE_MDP0(CLK_MDP_RSZ2, "mdp_rsz2", "mdp_sel", 10),
+	GATE_MDP0(CLK_MDP_COLOR0, "mdp_color0", "mdp_sel", 11),
+	GATE_MDP0(CLK_MDP_TDSHP2, "mdp_tdshp2", "mdp_sel", 12),
+	GATE_MDP0(CLK_MDP_TCC2, "mdp_tcc2", "mdp_sel", 13),
+	GATE_MDP0(CLK_MDP_WROT2, "mdp_wrot2", "mdp_sel", 14),
+	GATE_MDP0(CLK_MDP_MUTEX0, "mdp_mutex0", "mdp_sel", 15),
+	GATE_MDP0(CLK_MDP_RDMA1, "mdp_rdma1", "mdp_sel", 16),
+	GATE_MDP0(CLK_MDP_FG1, "mdp_fg1", "mdp_sel", 17),
+	GATE_MDP0(CLK_MDP_HDR1, "mdp_hdr1", "mdp_sel", 18),
+	GATE_MDP0(CLK_MDP_AAL1, "mdp_aal1", "mdp_sel", 19),
+	GATE_MDP0(CLK_MDP_RSZ1, "mdp_rsz1", "mdp_sel", 20),
+	GATE_MDP0(CLK_MDP_TDSHP1, "mdp_tdshp1", "mdp_sel", 21),
+	GATE_MDP0(CLK_MDP_TCC1, "mdp_tcc1", "mdp_sel", 22),
+	GATE_MDP0(CLK_MDP_WROT1, "mdp_wrot1", "mdp_sel", 23),
+	GATE_MDP0(CLK_MDP_RDMA3, "mdp_rdma3", "mdp_sel", 24),
+	GATE_MDP0(CLK_MDP_AAL3, "mdp_aal3", "mdp_sel", 25),
+	GATE_MDP0(CLK_MDP_RSZ3, "mdp_rsz3", "mdp_sel", 26),
+	GATE_MDP0(CLK_MDP_COLOR1, "mdp_color1", "mdp_sel", 27),
+	GATE_MDP0(CLK_MDP_TDSHP3, "mdp_tdshp3", "mdp_sel", 28),
+	GATE_MDP0(CLK_MDP_TCC3, "mdp_tcc3", "mdp_sel", 29),
+	GATE_MDP0(CLK_MDP_WROT3, "mdp_wrot3", "mdp_sel", 30),
+	GATE_MDP0(CLK_MDP_APB_BUS, "mdp_apb_bus", "mdp_sel", 31),
+	/* MDP1 */
+	GATE_MDP1(CLK_MDP_MMSYSRAM, "mdp_mmsysram", "mdp_sel", 0),
+	GATE_MDP1(CLK_MDP_APMCU_GALS, "mdp_apmcu_gals", "mdp_sel", 1),
+	GATE_MDP1(CLK_MDP_SMI0, "mdp_smi0", "mdp_sel", 4),
+	GATE_MDP1(CLK_MDP_IMG_DL_ASYNC0, "mdp_img_dl_async0", "mdp_sel", 5),
+	GATE_MDP1(CLK_MDP_IMG_DL_ASYNC1, "mdp_img_dl_async1", "mdp_sel", 6),
+	GATE_MDP1(CLK_MDP_IMG_DL_ASYNC2, "mdp_img_dl_async2", "mdp_sel", 7),
+	GATE_MDP1(CLK_MDP_SMI1, "mdp_smi1", "mdp_sel", 8),
+	GATE_MDP1(CLK_MDP_IMG_DL_ASYNC3, "mdp_img_dl_async3", "mdp_sel", 9),
+	GATE_MDP1(CLK_MDP_SMI2, "mdp_smi2", "mdp_sel", 12),
+	/* MDP2 */
+	GATE_MDP2(CLK_MDP_IMG0_IMG_DL_ASYNC0, "mdp_img0_dl_as0", "img1_sel", 0),
+	GATE_MDP2(CLK_MDP_IMG0_IMG_DL_ASYNC1, "mdp_img0_dl_as1", "img1_sel", 1),
+	GATE_MDP2(CLK_MDP_IMG1_IMG_DL_ASYNC2, "mdp_img1_dl_as2", "img2_sel", 8),
+	GATE_MDP2(CLK_MDP_IMG1_IMG_DL_ASYNC3, "mdp_img1_dl_as3", "img2_sel", 9),
+};
+
+static const struct mtk_clk_desc mdp_desc = {
+	.clks = mdp_clks,
+	.num_clks = ARRAY_SIZE(mdp_clks),
+};
+
+static const struct of_device_id of_match_clk_mt6893_mdp[] = {
+	{ .compatible = "mediatek,mt6893-mdpsys", .data = &mdp_desc },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt6893_mdp);
+
+static struct platform_driver clk_mt6893_mdp_drv = {
+	.probe = mtk_clk_simple_probe,
+	.remove = mtk_clk_simple_remove,
+	.driver = {
+		.name = "clk-mt6893-mdp",
+		.of_match_table = of_match_clk_mt6893_mdp,
+	},
+};
+module_platform_driver(clk_mt6893_mdp_drv);
+
+MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
+MODULE_DESCRIPTION("MediaTek MT6893 Multimedia Data Path clocks driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/clk-mt6893-mfg.c b/drivers/clk/mediatek/clk-mt6893-mfg.c
new file mode 100644
index 000000000000..37e7db835440
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6893-mfg.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Copyright (c) 2025 Collabora Ltd
+ */
+
+#include <dt-bindings/clock/mediatek,mt6893-clk.h>
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+static const struct mtk_gate_regs mfgcfg_cg_regs = {
+	.set_ofs = 0x4,
+	.clr_ofs = 0x8,
+	.sta_ofs = 0x0,
+};
+
+#define GATE_MFG(_id, _name, _parent, _shift)				\
+	GATE_MTK_FLAGS(_id, _name, _parent, &mfgcfg_cg_regs, _shift,	\
+		       &mtk_clk_gate_ops_setclr, CLK_SET_RATE_PARENT)
+
+static const struct mtk_gate mfgcfg_clks[] = {
+	GATE_MFG(CLK_MFGCFG_BG3D, "mfgcfg_bg3d", "mfg_pll_sel", 0),
+};
+
+static const struct mtk_clk_desc mfgcfg_desc = {
+	.clks = mfgcfg_clks,
+	.num_clks = ARRAY_SIZE(mfgcfg_clks),
+};
+
+static const struct of_device_id of_match_clk_mt6893_mfgcfg[] = {
+	{ .compatible = "mediatek,mt6893-mfgcfg", .data = &mfgcfg_desc },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt6893_mfgcfg);
+
+static struct platform_driver clk_mt6893_mfgcfg_drv = {
+	.probe = mtk_clk_simple_probe,
+	.remove = mtk_clk_simple_remove,
+	.driver = {
+		.name = "clk-mt6893-mfgcfg",
+		.of_match_table = of_match_clk_mt6893_mfgcfg,
+	},
+};
+
+module_platform_driver(clk_mt6893_mfgcfg_drv);
+
+MODULE_DESCRIPTION("MediaTek MT6893 GPU mfg clocks driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/clk-mt6893-mm.c b/drivers/clk/mediatek/clk-mt6893-mm.c
new file mode 100644
index 000000000000..b41dde6f3149
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6893-mm.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Copyright (c) 2025 Collabora Ltd
+ *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mediatek,mt6893-clk.h>
+
+static const struct mtk_gate_regs mm0_cg_regs = {
+	.set_ofs = 0x104,
+	.clr_ofs = 0x108,
+	.sta_ofs = 0x100,
+};
+
+static const struct mtk_gate_regs mm1_cg_regs = {
+	.set_ofs = 0x114,
+	.clr_ofs = 0x118,
+	.sta_ofs = 0x110,
+};
+
+static const struct mtk_gate_regs mm2_cg_regs = {
+	.set_ofs = 0x1a4,
+	.clr_ofs = 0x1a8,
+	.sta_ofs = 0x1a0,
+};
+
+#define GATE_MM0(_id, _name, _parent, _shift)	\
+	GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_MM1(_id, _name, _parent, _shift)	\
+	GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_MM2(_id, _name, _parent, _shift)	\
+	GATE_MTK(_id, _name, _parent, &mm2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate mm_clks[] = {
+	/* MM0 */
+	GATE_MM0(CLK_MM_DISP_RSZ0, "mm_disp_rsz0", "disp_sel", 0),
+	GATE_MM0(CLK_MM_DISP_RSZ1, "mm_disp_rsz1", "disp_sel", 1),
+	GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "disp_sel", 2),
+	GATE_MM0(CLK_MM_INLINE, "mm_inline", "disp_sel", 3),
+	GATE_MM0(CLK_MM_MDP_TDSHP4, "mm_mdp_tdshp4", "disp_sel", 4),
+	GATE_MM0(CLK_MM_MDP_TDSHP5, "mm_mdp_tdshp5", "disp_sel", 5),
+	GATE_MM0(CLK_MM_MDP_AAL4, "mm_mdp_aal4", "disp_sel", 6),
+	GATE_MM0(CLK_MM_MDP_AAL5, "mm_mdp_aal5", "disp_sel", 7),
+	GATE_MM0(CLK_MM_MDP_HDR4, "mm_mdp_hdr4", "disp_sel", 8),
+	GATE_MM0(CLK_MM_MDP_HDR5, "mm_mdp_hdr5", "disp_sel", 9),
+	GATE_MM0(CLK_MM_MDP_RSZ4, "mm_mdp_rsz4", "disp_sel", 10),
+	GATE_MM0(CLK_MM_MDP_RSZ5, "mm_mdp_rsz5", "disp_sel", 11),
+	GATE_MM0(CLK_MM_MDP_RDMA4, "mm_mdp_rdma4", "disp_sel", 12),
+	GATE_MM0(CLK_MM_MDP_RDMA5, "mm_mdp_rdma5", "disp_sel", 13),
+	GATE_MM0(CLK_MM_DISP_FAKE_ENG0, "mm_disp_fake_eng0", "disp_sel", 14),
+	GATE_MM0(CLK_MM_DISP_FAKE_ENG1, "mm_disp_fake_eng1", "disp_sel", 15),
+	GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "disp_sel", 16),
+	GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "disp_sel", 17),
+	GATE_MM0(CLK_MM_DISP_OVL2_2L, "mm_disp_ovl2_2l", "disp_sel", 18),
+	GATE_MM0(CLK_MM_DISP_MUTEX, "mm_disp_mutex", "disp_sel", 19),
+	GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "disp_sel", 20),
+	GATE_MM0(CLK_MM_DISP_OVL3_2L, "mm_disp_ovl3_2l", "disp_sel", 21),
+	GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "disp_sel", 22),
+	GATE_MM0(CLK_MM_DISP_CCORR1, "mm_disp_ccorr1", "disp_sel", 23),
+	GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "disp_sel", 24),
+	GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "disp_sel", 25),
+	GATE_MM0(CLK_MM_DISP_POSTMASK0, "mm_disp_postmask0", "disp_sel", 26),
+	GATE_MM0(CLK_MM_DISP_POSTMASK1, "mm_disp_postmask1", "disp_sel", 27),
+	GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "disp_sel", 28),
+	GATE_MM0(CLK_MM_DISP_DITHER1, "mm_disp_dither1", "disp_sel", 29),
+	GATE_MM0(CLK_MM_DSI0_MM_CLK, "mm_dsi0_mm_clk", "disp_sel", 30),
+	GATE_MM0(CLK_MM_DSI1_MM_CLK, "mm_dsi1_mm_clk", "disp_sel", 31),
+	/* MM1 */
+	GATE_MM1(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "disp_sel", 0),
+	GATE_MM1(CLK_MM_DISP_GAMMA1, "mm_disp_gamma1", "disp_sel", 1),
+	GATE_MM1(CLK_MM_DISP_AAL0, "mm_disp_aal0", "disp_sel", 2),
+	GATE_MM1(CLK_MM_DISP_AAL1, "mm_disp_aal1", "disp_sel", 3),
+	GATE_MM1(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "disp_sel", 4),
+	GATE_MM1(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "disp_sel", 5),
+	GATE_MM1(CLK_MM_DISP_UFBC_WDMA0, "mm_disp_ufbc_wdma0", "disp_sel", 6),
+	GATE_MM1(CLK_MM_DISP_UFBC_WDMA1, "mm_disp_ufbc_wdma1", "disp_sel", 7),
+	GATE_MM1(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "disp_sel", 8),
+	GATE_MM1(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "disp_sel", 9),
+	GATE_MM1(CLK_MM_DISP_RDMA4, "mm_disp_rdma4", "disp_sel", 10),
+	GATE_MM1(CLK_MM_DISP_RDMA5, "mm_disp_rdma5", "disp_sel", 11),
+	GATE_MM1(CLK_MM_DISP_DSC_WRAP, "mm_disp_dsc_wrap", "disp_sel", 12),
+	GATE_MM1(CLK_MM_DP_INTF_MM_CLK, "mm_dp_intf_mm_clk", "disp_sel", 13),
+	GATE_MM1(CLK_MM_DISP_MERGE0, "mm_disp_merge0", "disp_sel", 14),
+	GATE_MM1(CLK_MM_DISP_MERGE1, "mm_disp_merge1", "disp_sel", 15),
+	GATE_MM1(CLK_MM_SMI_COMMON, "mm_smi_common", "disp_sel", 19),
+	GATE_MM1(CLK_MM_SMI_GALS, "mm_smi_gals", "disp_sel", 23),
+	GATE_MM1(CLK_MM_SMI_INFRA, "mm_smi_infra", "disp_sel", 27),
+	GATE_MM1(CLK_MM_SMI_IOMMU, "mm_smi_iommu", "disp_sel", 31),
+	/* MM2 */
+	GATE_MM2(CLK_MM_DSI0_INTF_CLK, "mm_dsi0_intf_clk", "disp_sel", 0),
+	GATE_MM2(CLK_MM_DSI1_INTF_CLK, "mm_dsi1_intf_clk", "disp_sel", 8),
+	GATE_MM2(CLK_MM_DP_INTF_INTF_CLK, "mm_dp_intf_intf_clk", "dp_sel", 16),
+	GATE_MM2(CLK_MM_CK_26_MHZ, "mm_26_mhz", "clk26m", 24),
+	GATE_MM2(CLK_MM_CK_32_KHZ, "mm_32_khz", "clk32k", 25),
+};
+
+static const struct mtk_clk_desc mm_desc = {
+	.clks = mm_clks,
+	.num_clks = ARRAY_SIZE(mm_clks),
+};
+
+static const struct platform_device_id clk_mt6893_mm_id_table[] = {
+	{ .name = "clk-mt6893-mm", .driver_data = (kernel_ulong_t)&mm_desc },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(platform, clk_mt6893_mm_id_table);
+
+static struct platform_driver clk_mt6893_mm_drv = {
+	.probe = mtk_clk_pdev_probe,
+	.remove = mtk_clk_pdev_remove,
+	.driver = {
+		.name = "clk-mt6893-mm",
+	},
+	.id_table = clk_mt6893_mm_id_table,
+};
+module_platform_driver(clk_mt6893_mm_drv);
+
+MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
+MODULE_DESCRIPTION("MediaTek MT6893 MultiMedia clocks driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/clk-mt6893-scp_adsp.c b/drivers/clk/mediatek/clk-mt6893-scp_adsp.c
new file mode 100644
index 000000000000..9a02c54c2e5b
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6893-scp_adsp.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Copyright (c) 2025 Collabora Ltd
+ *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mediatek,mt6893-clk.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+static const struct mtk_gate_regs scp_adsp_cg_regs = {
+	.set_ofs = 0x180,
+	.clr_ofs = 0x180,
+	.sta_ofs = 0x180,
+};
+
+#define GATE_SCP_ADSP(_id, _name, _parent, _shift)	\
+	GATE_MTK(_id, _name, _parent, &scp_adsp_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
+
+static const struct mtk_gate scp_adsp_clks[] = {
+	GATE_SCP_ADSP(CLK_SCP_ADSP_AUDIODSP, "scp_adsp_audiodsp", "adsp_sel", 0),
+};
+
+static const struct mtk_clk_desc scp_adsp_desc = {
+	.clks = scp_adsp_clks,
+	.num_clks = ARRAY_SIZE(scp_adsp_clks),
+};
+
+static const struct of_device_id of_match_clk_mt6893_scp_adsp[] = {
+	{ .compatible = "mediatek,mt6893-scp-adsp", .data = &scp_adsp_desc },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt6893_scp_adsp);
+
+static struct platform_driver clk_mt6893_scp_adsp_drv = {
+	.probe = mtk_clk_simple_probe,
+	.remove = mtk_clk_simple_remove,
+	.driver = {
+		.name = "clk-mt6893-scp_adsp",
+		.of_match_table = of_match_clk_mt6893_scp_adsp,
+	},
+};
+module_platform_driver(clk_mt6893_scp_adsp_drv);
+
+MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
+MODULE_DESCRIPTION("MediaTek MT6893 SCP AudioDSP clocks driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/clk-mt6893-vdec.c b/drivers/clk/mediatek/clk-mt6893-vdec.c
new file mode 100644
index 000000000000..4816f7710d9e
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6893-vdec.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Copyright (c) 2025 Collabora Ltd
+ *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mediatek,mt6893-clk.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+static const struct mtk_gate_regs vdec0_cg_regs = {
+	.set_ofs = 0x0,
+	.clr_ofs = 0x4,
+	.sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs vdec1_cg_regs = {
+	.set_ofs = 0x200,
+	.clr_ofs = 0x204,
+	.sta_ofs = 0x200,
+};
+
+static const struct mtk_gate_regs vdec2_cg_regs = {
+	.set_ofs = 0x8,
+	.clr_ofs = 0xc,
+	.sta_ofs = 0x8,
+};
+
+#define GATE_VDEC0(_id, _name, _parent, _shift)	\
+	GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
+
+#define GATE_VDEC1(_id, _name, _parent, _shift)	\
+	GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
+
+#define GATE_VDEC2(_id, _name, _parent, _shift)	\
+	GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
+
+static const struct mtk_gate vdec_clks[] = {
+	/* VDEC0 */
+	GATE_VDEC0(CLK_VDEC_VDEC, "vdec_vdec", "vdec_sel", 0),
+	GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "vdec_sel", 4),
+	GATE_VDEC0(CLK_VDEC_VDEC_ENG, "vdec_vdec_eng", "vdec_sel", 8),
+	/* VDEC1 */
+	GATE_VDEC1(CLK_VDEC_LAT, "vdec_lat", "vdec_sel", 0),
+	GATE_VDEC1(CLK_VDEC_LAT_ACTIVE, "vdec_lat_active", "vdec_sel", 4),
+	GATE_VDEC1(CLK_VDEC_LAT_ENG, "vdec_lat_eng", "vdec_sel", 8),
+	/* VDEC2 */
+	GATE_VDEC2(CLK_VDEC_LARB1, "vdec_larb1", "vdec_sel", 0),
+};
+
+static const struct mtk_gate vdec_soc_clks[] = {
+	/* VDEC_SOC0 */
+	GATE_VDEC0(CLK_VDEC_SOC_VDEC, "vdec_soc_vdec", "vdec_sel", 0),
+	GATE_VDEC0(CLK_VDEC_SOC_VDEC_ACTIVE, "vdec_soc_vdec_active", "vdec_sel", 4),
+	GATE_VDEC0(CLK_VDEC_SOC_VDEC_ENG, "vdec_soc_vdec_cken_eng", "vdec_sel", 8),
+	/* VDEC_SOC1 */
+	GATE_VDEC1(CLK_VDEC_SOC_LAT, "vdec_soc_lat", "vdec_sel", 0),
+	GATE_VDEC1(CLK_VDEC_SOC_LAT_ACTIVE, "vdec_soc_lat_active", "vdec_sel", 4),
+	GATE_VDEC1(CLK_VDEC_SOC_LAT_ENG, "vdec_soc_lat_eng", "vdec_sel", 8),
+	/* VDEC_SOC2 */
+	GATE_VDEC2(CLK_VDEC_SOC_LARB1, "vdec_soc_larb1", "vdec_sel", 0),
+};
+
+static const struct mtk_clk_desc vdec_desc = {
+	.clks = vdec_clks,
+	.num_clks = ARRAY_SIZE(vdec_clks),
+};
+
+static const struct mtk_clk_desc vdec_soc_desc = {
+	.clks = vdec_soc_clks,
+	.num_clks = ARRAY_SIZE(vdec_soc_clks),
+};
+
+static const struct of_device_id of_match_clk_mt6893_vdec[] = {
+	{ .compatible = "mediatek,mt6893-vdecsys", .data = &vdec_desc },
+	{ .compatible = "mediatek,mt6893-vdecsys-soc", .data = &vdec_soc_desc },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt6893_vdec);
+
+static struct platform_driver clk_mt6893_vdec_drv = {
+	.probe = mtk_clk_simple_probe,
+	.remove = mtk_clk_simple_remove,
+	.driver = {
+		.name = "clk-mt6893-vdec",
+		.of_match_table = of_match_clk_mt6893_vdec,
+	},
+};
+module_platform_driver(clk_mt6893_vdec_drv);
+
+MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
+MODULE_DESCRIPTION("MediaTek MT6893 Video Decoders clocks driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/clk-mt6893-venc.c b/drivers/clk/mediatek/clk-mt6893-venc.c
new file mode 100644
index 000000000000..d0e88ef3778d
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6893-venc.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Copyright (c) 2025 Collabora Ltd
+ *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/mediatek,mt6893-clk.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+static const struct mtk_gate_regs venc_cg_regs = {
+	.set_ofs = 0x4,
+	.clr_ofs = 0x8,
+	.sta_ofs = 0x0,
+};
+
+#define GATE_VENC(_id, _name, _parent, _shift)	\
+	GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
+
+static const struct mtk_gate venc0_clks[] = {
+	GATE_VENC(CLK_VENC0_SET0_LARB, "venc0_set0_larb", "venc_sel", 0),
+	GATE_VENC(CLK_VENC0_SET1_VENC, "venc0_set1_venc", "venc_sel", 4),
+	GATE_VENC(CLK_VENC0_SET2_JPGENC, "venc0_set2_jpgenc", "venc_sel", 8),
+	GATE_VENC(CLK_VENC0_SET3_JPGDEC, "venc0_set2_jpgdec", "venc_sel", 12),
+	GATE_VENC(CLK_VENC0_SET4_JPGDEC_C1, "venc0_set2_jpgdec_c1", "venc_sel", 16),
+	GATE_VENC(CLK_VENC0_SET5_GALS, "venc0_set5_gals", "venc_sel", 28),
+};
+
+static const struct mtk_clk_desc venc0_desc = {
+	.clks = venc0_clks,
+	.num_clks = ARRAY_SIZE(venc0_clks),
+};
+
+static const struct mtk_gate venc1_clks[] = {
+	GATE_VENC(CLK_VENC1_SET0_LARB, "venc1_set0_larb", "venc_sel", 0),
+	GATE_VENC(CLK_VENC1_SET1_VENC, "venc1_set1_venc", "venc_sel", 4),
+	GATE_VENC(CLK_VENC1_SET2_JPGENC, "venc1_set2_jpgenc", "venc_sel", 8),
+	GATE_VENC(CLK_VENC1_SET3_JPGDEC, "venc1_set2_jpgdec", "venc_sel", 12),
+	GATE_VENC(CLK_VENC1_SET4_JPGDEC_C1, "venc1_set2_jpgdec_c1", "venc_sel", 16),
+	GATE_VENC(CLK_VENC1_SET5_GALS, "venc1_set5_gals", "venc_sel", 28),
+};
+
+static const struct mtk_clk_desc venc1_desc = {
+	.clks = venc1_clks,
+	.num_clks = ARRAY_SIZE(venc1_clks),
+};
+
+static const struct of_device_id of_match_clk_mt6893_venc[] = {
+	{ .compatible = "mediatek,mt6893-vencsys-c0", .data = &venc0_desc },
+	{ .compatible = "mediatek,mt6893-vencsys-c1", .data = &venc1_desc },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt6893_venc);
+
+static struct platform_driver clk_mt6893_venc_drv = {
+	.probe = mtk_clk_simple_probe,
+	.remove = mtk_clk_simple_remove,
+	.driver = {
+		.name = "clk-mt6893-venc",
+		.of_match_table = of_match_clk_mt6893_venc,
+	},
+};
+module_platform_driver(clk_mt6893_venc_drv);
+
+MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
+MODULE_DESCRIPTION("MediaTek MT6893 Video Encoders clocks driver");
+MODULE_LICENSE("GPL");
-- 
2.49.0