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From: Siddharth Vadapalli <s-vadapalli@ti.com>
To: <nm@ti.com>, <vigneshr@ti.com>, <kristo@kernel.org>,
	<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>
Cc: <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>, <srk@ti.com>,
	<s-vadapalli@ti.com>
Subject: [PATCH 1/7] arm64: dts: ti: k3-am64-main: switch to 64-bit address space for PCIe0
Date: Thu, 17 Apr 2025 17:34:01 +0530	[thread overview]
Message-ID: <20250417120407.2646929-2-s-vadapalli@ti.com> (raw)
In-Reply-To: <20250417120407.2646929-1-s-vadapalli@ti.com>

The PCIe0 instance of PCIe in AM64 SoC supports:
1. 128 MB address region in the 32-bit address space
2. 4 GB address region in the 64-bit address space

The default configuration is that of a 128 MB address region in the
32-bit address space. While this might be sufficient for most use-cases,
it is insufficient for supporting use-cases which require larger address
spaces. Therefore, switch to using the 64-bit address space with a 4 GB
address region.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 324eb44c258d..1a6e5ea65f9a 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -1031,7 +1031,7 @@ pcie0_rc: pcie@f102000 {
 		reg = <0x00 0x0f102000 0x00 0x1000>,
 		      <0x00 0x0f100000 0x00 0x400>,
 		      <0x00 0x0d000000 0x00 0x00800000>,
-		      <0x00 0x68000000 0x00 0x00001000>;
+		      <0x06 0x00000000 0x00 0x00001000>;
 		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
 		interrupt-names = "link_state";
 		interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
@@ -1049,8 +1049,9 @@ pcie0_rc: pcie@f102000 {
 		vendor-id = <0x104c>;
 		device-id = <0xb010>;
 		msi-map = <0x0 &gic_its 0x0 0x10000>;
-		ranges = <0x01000000 0x00 0x68001000  0x00 0x68001000  0x00 0x0010000>,
-			 <0x02000000 0x00 0x68011000  0x00 0x68011000  0x00 0x7fef000>;
+		ranges = <0x01000000 0x00 0x00001000 0x06 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
+			 <0x02000000 0x00 0x00101000 0x06 0x00101000 0x00 0x08000000>, /* 32-bit Non-Prefetchable MEM (128 MB) */
+			 <0x43000000 0x06 0x08101000 0x06 0x08101000 0x00 0xf7eff000>; /* 64-bit Prefetchable MEM (4 GB - (129 MB + 4 KB)) */
 		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;
 		status = "disabled";
 	};
-- 
2.34.1



  reply	other threads:[~2025-04-17 12:22 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-17 12:04 [PATCH 0/7] AM64 and J7X DT: Enable PCIe 64-bit Address Space Siddharth Vadapalli
2025-04-17 12:04 ` Siddharth Vadapalli [this message]
2025-04-17 12:04 ` [PATCH 2/7] arm64: dts: ti: k3-j7200-main: switch to 64-bit address space for PCIe1 Siddharth Vadapalli
2025-04-19 18:05   ` Kumar, Udit
2025-04-20  3:03     ` Siddharth Vadapalli
2025-04-20  4:47       ` Kumar, Udit
2025-04-20 14:18         ` Siddharth Vadapalli
2025-04-21  7:59           ` Kumar, Udit
2025-04-22 10:27             ` Siddharth Vadapalli
2025-04-17 12:04 ` [PATCH 3/7] arm64: dts: ti: k3-j721e: add ranges for PCIe0 DAT1 and PCIe1 DAT1 Siddharth Vadapalli
2025-04-19 18:09   ` Kumar, Udit
2025-04-20  3:05     ` Siddharth Vadapalli
2025-04-17 12:04 ` [PATCH 4/7] arm64: dts: ti: k3-j721e-main: switch to 64-bit address space for PCIe0 and PCIe1 Siddharth Vadapalli
2025-04-17 12:04 ` [PATCH 5/7] arm64: dts: ti: k3-j721s2-main: switch to 64-bit address space for PCIe1 Siddharth Vadapalli
2025-04-17 12:04 ` [PATCH 6/7] arm64: dts: ti: k3-j722s-main: switch to 64-bit address space for PCIe0 Siddharth Vadapalli
2025-04-17 12:04 ` [PATCH 7/7] arm64: dts: ti: k3-j784s4-j742s2-main-common: switch to 64-bit address space for PCIe0 and PCIe1 Siddharth Vadapalli

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