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Fri, 18 Apr 2025 14:04:30 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 18 Apr 2025 14:04:30 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 18 Apr 2025 14:04:30 -0500 Received: from localhost (uda0133052.dhcp.ti.com [128.247.81.232]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53IJ4Tth126391; Fri, 18 Apr 2025 14:04:29 -0500 Date: Fri, 18 Apr 2025 14:04:30 -0500 From: Nishanth Menon To: Bjorn Helgaas CC: , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v7 0/8] soc: ti: Add and use PVU on K3-AM65 for DMA isolation Message-ID: <20250418190430.onhuowuu4bwtlm5f@sequel> References: <20250418134324.ewsfnze2btnx2r2w@country> <20250418163401.GA159541@bhelgaas> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20250418163401.GA159541@bhelgaas> X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250418_120444_720519_2050BACE X-CRM114-Status: GOOD ( 20.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 11:34-20250418, Bjorn Helgaas wrote: > On Fri, Apr 18, 2025 at 08:43:24AM -0500, Nishanth Menon wrote: > > On 15:30-20250418, huaqian.li@siemens.com wrote: > > > > > > Jan Kiszka (7): > > > dt-bindings: soc: ti: Add AM65 peripheral virtualization unit > > > dt-bindings: PCI: ti,am65: Extend for use with PVU > > > soc: ti: Add IOMMU-like PVU driver > > > PCI: keystone: Add support for PVU-based DMA isolation on AM654 > > > arm64: dts: ti: k3-am65-main: Add PVU nodes > > > arm64: dts: ti: k3-am65-main: Add VMAP registers to PCI root complexes > > > arm64: dts: ti: iot2050: Add overlay for DMA isolation for devices > > > behind PCI RC > > > > > > Li Hua Qian (1): > > > swiotlb: Make IO_TLB_SEGSIZE configurable > > > > I see at least 3 or 4 maintainers needing to co-ordinate, gets > > complicated as I am not sure which maintainer needs to pick up what > > patches in what dependency order. This looks like a mixed bag. Can > > we split this patch into independent series for each maintainer with > > clear indication of dependencies that is spread around a couple of > > kernel windows (maybe dts comes in last?) > > The keystone patch ("[4/8] PCI: keystone: Add support for PVU-based > DMA isolation on AM654") depends on interfaces added by "[3/8] soc: > ti: Add IOMMU-like PVU driver", so I can't really take 4/8 by itself. > > But I've acked 4/8, so it can be merged along with the rest of the > series. I assumed the easiest would be via the drivers/soc/ti/ > maintainer, i.e., you, Nisanth :) > > Let me know if I can do anything. Thanks Bjorn, the swiotlb probably is one of the first to go in, I guess.. I will let Li Hua/Jan suggest how they'd like to queue this. -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D