From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7F303C369D1 for ; Fri, 25 Apr 2025 09:01:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Y6EftXxKjeJiYdb5hysJMTkENF1e1R9UlPS8QZvib7E=; b=wYV8U4Ce38vfdosFTvfyCLUF2Z GAk/Xo/s5l+/yxipvLrMG/W7F0Yi3jFdVUhdF0clH4XUyyQPVfX4F01VOgnCXeL4eEDPRobmPgitr UYhGKruMtUALIOcITLi2k2sSnbORcA2jwRWQhdCL1a93aef563t/tQHiMnLsLW77CR0rkf8kfwJ4a YQsPhZB9uO2k9mH5Lb5pG1Id+zecCEn0LW9ma8aN9v1asltzr2qkKXt/EGDNMUZx6DIj1sTK6SOkX 5R+5kACRohMkJmVU66rMUiO/XKQOLIaKQiORDj6nsOl77TJpgn5YXsLzUeWi7Xgd62rwh4UK1j31R fWogQX5w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1u8Evt-0000000GScX-3Ili; Fri, 25 Apr 2025 09:01:17 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1u8EoZ-0000000GQPs-2uwU; Fri, 25 Apr 2025 08:53:45 +0000 X-UUID: c7062f9c21b211f0a2405d5ef59ce188-20250425 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Y6EftXxKjeJiYdb5hysJMTkENF1e1R9UlPS8QZvib7E=; b=UJXGuASy6d+yVChTb2gCn6YrboECym6DVfmhJASArxQ+WHnGYPyRzp4XChIiyWvSiKDRKXHhHXD4MT7ct7eMvNyOHGT5KoQL4G7uDGnWm7vGeb+SWkhSIlQ4qgsT9U1GFdemhrS9fdHUtQEwSqE1My1eG+tN3W04IZw/nOGQdAQ=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.1,REQID:408a36c0-2b10-4640-b997-16e3ad84787c,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:0ef645f,CLOUDID:a557dd6f-e08c-41ab-89e8-3ba0a33da853,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 5,DFT|NGT X-CID-BAS: 5,DFT|NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: c7062f9c21b211f0a2405d5ef59ce188-20250425 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1311784457; Fri, 25 Apr 2025 01:53:37 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Fri, 25 Apr 2025 16:53:35 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Fri, 25 Apr 2025 16:53:35 +0800 From: Kyrie Wu To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , kyrie wu , , , , , CC: Kyrie Wu Subject: [PATCH v3 04/12] media: mediatek: jpeg: add jpeg smmu sid setting Date: Fri, 25 Apr 2025 16:53:20 +0800 Message-ID: <20250425085328.16929-5-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250425085328.16929-1-kyrie.wu@mediatek.com> References: <20250425085328.16929-1-kyrie.wu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250425_015343_743251_B81E0381 X-CRM114-Status: GOOD ( 18.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a configuration to set jpeg dec & enc smmu sid Change-Id: Id753ce17138c363bcb597e7023d79e3c39b240da Signed-off-by: Kyrie Wu --- .../platform/mediatek/jpeg/mtk_jpeg_core.c | 37 +++++++++++++++++++ .../platform/mediatek/jpeg/mtk_jpeg_core.h | 15 ++++++++ .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 23 ++++++++++++ .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c | 23 ++++++++++++ 4 files changed, 98 insertions(+) diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c index e89ccb8c904c..ea890f01fa9e 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -1584,6 +1585,20 @@ static irqreturn_t mtk_jpeg_enc_done(struct mtk_jpeg_dev *jpeg) return IRQ_HANDLED; } +static void mtk_jpeg_enc_set_smmu_sid(struct mtk_jpegenc_comp_dev *jpeg) +{ + struct mtk_jpeg_dev *mjpeg = jpeg->master_dev; + + if (!mjpeg->variant->support_smmu || !jpeg->smmu_regmap) + return; + + regmap_update_bits(jpeg->smmu_regmap, JPEG_ENC_SMMU_SID, + JPG_REG_GUSER_ID_MASK << + JPG_REG_ENC_GUSER_ID_SHIFT, + JPG_REG_GUSER_ID_ENC_SID << + JPG_REG_ENC_GUSER_ID_SHIFT); +} + static void mtk_jpegenc_worker(struct work_struct *work) { struct mtk_jpegenc_comp_dev *comp_jpeg[MTK_JPEGENC_HW_MAX]; @@ -1655,6 +1670,9 @@ static void mtk_jpegenc_worker(struct work_struct *work) jpeg_dst_buf->frame_num = ctx->total_frame_num; ctx->total_frame_num++; mtk_jpeg_enc_reset(comp_jpeg[hw_id]->reg_base); + + mtk_jpeg_enc_set_smmu_sid(comp_jpeg[hw_id]); + mtk_jpeg_set_enc_dst(ctx, comp_jpeg[hw_id]->reg_base, &dst_buf->vb2_buf); @@ -1679,6 +1697,20 @@ static void mtk_jpegenc_worker(struct work_struct *work) v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx); } +static void mtk_jpeg_dec_set_smmu_sid(struct mtk_jpegdec_comp_dev *jpeg) +{ + struct mtk_jpeg_dev *mjpeg = jpeg->master_dev; + + if (!mjpeg->variant->support_smmu || !jpeg->smmu_regmap) + return; + + regmap_update_bits(jpeg->smmu_regmap, JPEG_DEC_SMMU_SID, + JPG_REG_GUSER_ID_MASK << + JPG_REG_DEC_GUSER_ID_SHIFT, + JPG_REG_GUSER_ID_DEC_SID << + JPG_REG_DEC_GUSER_ID_SHIFT); +} + static void mtk_jpegdec_worker(struct work_struct *work) { struct mtk_jpeg_ctx *ctx = container_of(work, struct mtk_jpeg_ctx, @@ -1771,6 +1803,9 @@ static void mtk_jpegdec_worker(struct work_struct *work) spin_lock_irqsave(&comp_jpeg[hw_id]->hw_lock, flags); ctx->total_frame_num++; mtk_jpeg_dec_reset(comp_jpeg[hw_id]->reg_base); + + mtk_jpeg_dec_set_smmu_sid(comp_jpeg[hw_id]); + mtk_jpeg_dec_set_config(comp_jpeg[hw_id]->reg_base, jpeg->variant->support_34bit, &jpeg_src_buf->dec_param, @@ -1929,6 +1964,7 @@ static struct mtk_jpeg_variant mtk8196_jpegenc_drvdata = { .cap_q_default_fourcc = V4L2_PIX_FMT_JPEG, .multi_core = true, .jpeg_worker = mtk_jpegenc_worker, + .support_smmu = true, }; static const struct mtk_jpeg_variant mtk8195_jpegdec_drvdata = { @@ -1955,6 +1991,7 @@ static const struct mtk_jpeg_variant mtk8196_jpegdec_drvdata = { .cap_q_default_fourcc = V4L2_PIX_FMT_YUV420M, .multi_core = true, .jpeg_worker = mtk_jpegdec_worker, + .support_smmu = true, }; static const struct of_device_id mtk_jpeg_match[] = { diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h index 02ed0ed5b736..46899512a5e6 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.h @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -34,6 +35,14 @@ #define MTK_JPEG_MAX_EXIF_SIZE (64 * 1024) +#define JPEG_DEC_SMMU_SID 0 +#define JPEG_ENC_SMMU_SID 0 +#define JPG_REG_GUSER_ID_MASK 0x7 +#define JPG_REG_GUSER_ID_DEC_SID 0x4 +#define JPG_REG_GUSER_ID_ENC_SID 0x5 +#define JPG_REG_DEC_GUSER_ID_SHIFT 8 +#define JPG_REG_ENC_GUSER_ID_SHIFT 4 + #define MTK_JPEG_ADDR_MASK GENMASK(1, 0) /** @@ -65,6 +74,7 @@ enum mtk_jpeg_ctx_state { * @multi_core: mark jpeg hw is multi_core or not * @jpeg_worker: jpeg dec or enc worker * @support_34bit: flag to check support for 34-bit DMA address + * @support_smmu: flag to check if support smmu */ struct mtk_jpeg_variant { struct clk_bulk_data *clks; @@ -82,6 +92,7 @@ struct mtk_jpeg_variant { bool multi_core; void (*jpeg_worker)(struct work_struct *work); bool support_34bit; + bool support_smmu; }; struct mtk_jpeg_src_buf { @@ -150,6 +161,7 @@ struct mtk_jpegdec_clk { * @hw_param: jpeg encode hw parameters * @hw_state: record hw state * @hw_lock: spinlock protecting the hw device resource + * @smmu_regmap: SMMU registers mapping */ struct mtk_jpegenc_comp_dev { struct device *dev; @@ -163,6 +175,7 @@ struct mtk_jpegenc_comp_dev { enum mtk_jpeg_hw_state hw_state; /* spinlock protecting the hw device resource */ spinlock_t hw_lock; + struct regmap *smmu_regmap; }; /** @@ -177,6 +190,7 @@ struct mtk_jpegenc_comp_dev { * @hw_param: jpeg decode hw parameters * @hw_state: record hw state * @hw_lock: spinlock protecting hw + * @smmu_regmap: SMMU registers mapping */ struct mtk_jpegdec_comp_dev { struct device *dev; @@ -190,6 +204,7 @@ struct mtk_jpegdec_comp_dev { enum mtk_jpeg_hw_state hw_state; /* spinlock protecting the hw device resource */ spinlock_t hw_lock; + struct regmap *smmu_regmap; }; /** diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c index 20553bf541df..059377805706 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c @@ -616,6 +616,25 @@ static int mtk_jpegdec_hw_init_irq(struct mtk_jpegdec_comp_dev *dev) return 0; } +static int mtk_jpegdec_smmu_init(struct mtk_jpegdec_comp_dev *dev) +{ + struct mtk_jpeg_dev *master_dev = dev->master_dev; + + if (!master_dev->variant->support_smmu) + return 0; + + dev->smmu_regmap = + syscon_regmap_lookup_by_phandle(dev->plat_dev->dev.of_node, + "mediatek,smmu-config"); + if (IS_ERR(dev->smmu_regmap)) { + return dev_err_probe(dev->dev, dev->smmu_regmap, + "mmap smmu_base failed(%ld)\n", + PTR_ERR(dev->smmu_regmap)); + } + + return 0; +} + static int mtk_jpegdec_hw_probe(struct platform_device *pdev) { struct mtk_jpegdec_clk *jpegdec_clk; @@ -668,6 +687,10 @@ static int mtk_jpegdec_hw_probe(struct platform_device *pdev) master_dev->reg_decbase[i] = dev->reg_base; dev->master_dev = master_dev; + ret = mtk_jpegdec_smmu_init(dev); + if (ret) + return ret; + platform_set_drvdata(pdev, dev); pm_runtime_enable(&pdev->dev); diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c index 69c95113f205..73c55e1546aa 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c @@ -340,6 +340,25 @@ static int mtk_jpegenc_hw_init_irq(struct mtk_jpegenc_comp_dev *dev) return 0; } +static int mtk_jpegenc_smmu_init(struct mtk_jpegenc_comp_dev *dev) +{ + struct mtk_jpeg_dev *master_dev = dev->master_dev; + + if (!master_dev->variant->support_smmu) + return 0; + + dev->smmu_regmap = + syscon_regmap_lookup_by_phandle(dev->plat_dev->dev.of_node, + "mediatek,smmu-config"); + if (IS_ERR(dev->smmu_regmap)) { + return dev_err_probe(dev->dev, dev->smmu_regmap, + "mmap smmu_base failed(%ld)\n", + PTR_ERR(dev->smmu_regmap)); + } + + return 0; +} + static int mtk_jpegenc_hw_probe(struct platform_device *pdev) { struct mtk_jpegenc_clk *jpegenc_clk; @@ -390,6 +409,10 @@ static int mtk_jpegenc_hw_probe(struct platform_device *pdev) master_dev->reg_encbase[i] = dev->reg_base; dev->master_dev = master_dev; + ret = mtk_jpegenc_smmu_init(dev); + if (ret) + return ret; + platform_set_drvdata(pdev, dev); pm_runtime_enable(&pdev->dev); -- 2.46.0