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Fri, 25 Apr 2025 15:31:31 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 25 Apr 2025 15:31:31 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 25 Apr 2025 15:31:31 -0500 Received: from localhost (uda0133052.dhcp.ti.com [128.247.81.232]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53PKVVJD064112; Fri, 25 Apr 2025 15:31:31 -0500 Date: Fri, 25 Apr 2025 15:31:31 -0500 From: Nishanth Menon To: Matt Coster CC: Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Frank Binns , Alessio Belle , Alexandru Dadu , Luigi Santivetti , Randolph Sapp , Darren Etheridge Subject: Re: [PATCH v3 2/2] arm64: dts: ti: k3-j721s2: Add GPU node Message-ID: <20250425203131.ueswwq2kifozt7m2@footwear> References: <20250422-bxs-4-64-dts-v3-0-ec6657bde135@imgtec.com> <20250422-bxs-4-64-dts-v3-2-ec6657bde135@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20250422-bxs-4-64-dts-v3-2-ec6657bde135@imgtec.com> X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250425_133138_562595_0DDC518A X-CRM114-Status: GOOD ( 19.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 16:26-20250422, Matt Coster wrote: > The J721S2 binding is based on the TI downstream binding in commit > 54b0f2a00d92 ("arm64: dts: ti: k3-j721s2-main: add gpu node") from [1] > but with updated compatible strings. > > The clock[2] and power[3] indices were verified from HTML docs, while > the intterupt index comes from the TRM[4] (appendix ^^ spell check interrupt (please use checkpatch.pl --strict --codespell to catch these minor nuisance bugs) > "J721S2_Appendix_20241106_Public.xlsx", "Interrupts (inputs)", > "GPU_BXS464_WRAP0_GPU_SS_0_OS_IRQ_OUT_0"). > > [1]: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel > [2]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/clocks.html > [3]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/devices.html > [4]: https://www.ti.com/lit/zip/spruj28 (revision E) > > Reviewed-by: Randolph Sapp > Signed-off-by: Matt Coster > --- > Changes in v3: > - Use assigned-clocks to pre-load the frequency of the core clock > - Link to v2: https://lore.kernel.org/r/20250417-bxs-4-64-dts-v2-2-9f8c09233114@imgtec.com > Changes in v2: > - Add interrupt reference details > - Add Randolph's Rb > - Link to v1: https://lore.kernel.org/r/20250415-bxs-4-64-dts-v1-2-f7d3fa06625d@imgtec.com > > This patch was previously sent as [DO NOT MERGE]: > https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-18-eda620c5865f@imgtec.com > --- > arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi > index 92bf48fdbeba45ecca8c854db5f72fd3666239c5..9e36cbbe0ea2fefceedcc95b78068ded7ef395f0 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi > @@ -2048,4 +2048,18 @@ watchdog8: watchdog@23f0000 { > /* reserved for MAIN_R5F1_1 */ > status = "reserved"; > }; > + > + gpu: gpu@4e20000000 { > + compatible = "ti,j721s2-gpu", "img,img-bxs-4-64", "img,img-rogue"; > + reg = <0x4e 0x20000000 0x00 0x80000>; > + clocks = <&k3_clks 130 1>; > + clock-names = "core"; > + assigned-clocks = <&k3_clks 130 1>; > + assigned-clock-rates = <800000000>; > + interrupts = ; > + power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>, > + <&k3_pds 373 TI_SCI_PD_EXCLUSIVE>; > + power-domain-names = "a", "b"; > + dma-coherent; > + }; > }; > > -- > 2.49.0 > -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D