* Re: [PATCH] arm64: errata: Add missing sentinels to Spectre-BHB MIDR arrays
2025-05-01 10:47 [PATCH] arm64: errata: Add missing sentinels to Spectre-BHB MIDR arrays Will Deacon
@ 2025-05-01 11:33 ` Lee Jones
2025-05-01 14:12 ` Doug Anderson
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Lee Jones @ 2025-05-01 11:33 UTC (permalink / raw)
To: Will Deacon
Cc: linux-arm-kernel, James Morse, Doug Anderson, Shameer Kolothum,
Catalin Marinas, Greg Kroah-Hartman
On Thu, 01 May 2025, Will Deacon wrote:
> Commit a5951389e58d ("arm64: errata: Add newer ARM cores to the
> spectre_bhb_loop_affected() lists") added some additional CPUs to the
> Spectre-BHB workaround, including some new arrays for designs that
> require new 'k' values for the workaround to be effective.
>
> Unfortunately, the new arrays omitted the sentinel entry and so
> is_midr_in_range_list() will walk off the end when it doesn't find a
> match. With UBSAN enabled, this leads to a crash during boot when
> is_midr_in_range_list() is inlined (which was more common prior to
> c8c2647e69be ("arm64: Make _midr_in_range_list() an exported
> function")):
>
> | Internal error: aarch64 BRK: 00000000f2000001 [#1] PREEMPT SMP
> | pstate: 804000c5 (Nzcv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> | pc : spectre_bhb_loop_affected+0x28/0x30
> | lr : is_spectre_bhb_affected+0x170/0x190
> | [...]
> | Call trace:
> | spectre_bhb_loop_affected+0x28/0x30
> | update_cpu_capabilities+0xc0/0x184
> | init_cpu_features+0x188/0x1a4
> | cpuinfo_store_boot_cpu+0x4c/0x60
> | smp_prepare_boot_cpu+0x38/0x54
> | start_kernel+0x8c/0x478
> | __primary_switched+0xc8/0xd4
> | Code: 6b09011f 54000061 52801080 d65f03c0 (d4200020)
> | ---[ end trace 0000000000000000 ]---
> | Kernel panic - not syncing: aarch64 BRK: Fatal exception
>
> Add the missing sentinel entries.
>
> Cc: Lee Jones <lee@kernel.org>
> Cc: James Morse <james.morse@arm.com>
> Cc: Doug Anderson <dianders@chromium.org>
> Cc: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Reported-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Fixes: a5951389e58d ("arm64: errata: Add newer ARM cores to the spectre_bhb_loop_affected() lists")
> Signed-off-by: Will Deacon <will@kernel.org>
> ---
> arch/arm64/kernel/proton-pack.c | 2 ++
> 1 file changed, 2 insertions(+)
Nice catch!
Reviewed-by: Lee Jones <lee@kernel.org>
> diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pack.c
> index b198dde79e59..b607f6dfc5e6 100644
> --- a/arch/arm64/kernel/proton-pack.c
> +++ b/arch/arm64/kernel/proton-pack.c
> @@ -879,10 +879,12 @@ static u8 spectre_bhb_loop_affected(void)
> static const struct midr_range spectre_bhb_k132_list[] = {
> MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),
> MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),
> + {},
> };
> static const struct midr_range spectre_bhb_k38_list[] = {
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A715),
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),
> + {},
> };
> static const struct midr_range spectre_bhb_k32_list[] = {
> MIDR_ALL_VERSIONS(MIDR_CORTEX_A78),
> --
> 2.49.0.906.g1f30a19c02-goog
>
--
Lee Jones [李琼斯]
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] arm64: errata: Add missing sentinels to Spectre-BHB MIDR arrays
2025-05-01 10:47 [PATCH] arm64: errata: Add missing sentinels to Spectre-BHB MIDR arrays Will Deacon
2025-05-01 11:33 ` Lee Jones
@ 2025-05-01 14:12 ` Doug Anderson
2025-05-01 15:43 ` Greg Kroah-Hartman
2025-05-01 16:46 ` Catalin Marinas
3 siblings, 0 replies; 5+ messages in thread
From: Doug Anderson @ 2025-05-01 14:12 UTC (permalink / raw)
To: Will Deacon
Cc: linux-arm-kernel, Lee Jones, James Morse, Shameer Kolothum,
Catalin Marinas, Greg Kroah-Hartman
Hi,
On Thu, May 1, 2025 at 3:48 AM Will Deacon <will@kernel.org> wrote:
>
> Commit a5951389e58d ("arm64: errata: Add newer ARM cores to the
> spectre_bhb_loop_affected() lists") added some additional CPUs to the
> Spectre-BHB workaround, including some new arrays for designs that
> require new 'k' values for the workaround to be effective.
>
> Unfortunately, the new arrays omitted the sentinel entry and so
> is_midr_in_range_list() will walk off the end when it doesn't find a
> match. With UBSAN enabled, this leads to a crash during boot when
> is_midr_in_range_list() is inlined (which was more common prior to
> c8c2647e69be ("arm64: Make _midr_in_range_list() an exported
> function")):
>
> | Internal error: aarch64 BRK: 00000000f2000001 [#1] PREEMPT SMP
> | pstate: 804000c5 (Nzcv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> | pc : spectre_bhb_loop_affected+0x28/0x30
> | lr : is_spectre_bhb_affected+0x170/0x190
> | [...]
> | Call trace:
> | spectre_bhb_loop_affected+0x28/0x30
> | update_cpu_capabilities+0xc0/0x184
> | init_cpu_features+0x188/0x1a4
> | cpuinfo_store_boot_cpu+0x4c/0x60
> | smp_prepare_boot_cpu+0x38/0x54
> | start_kernel+0x8c/0x478
> | __primary_switched+0xc8/0xd4
> | Code: 6b09011f 54000061 52801080 d65f03c0 (d4200020)
> | ---[ end trace 0000000000000000 ]---
> | Kernel panic - not syncing: aarch64 BRK: Fatal exception
>
> Add the missing sentinel entries.
>
> Cc: Lee Jones <lee@kernel.org>
> Cc: James Morse <james.morse@arm.com>
> Cc: Doug Anderson <dianders@chromium.org>
> Cc: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Reported-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Fixes: a5951389e58d ("arm64: errata: Add newer ARM cores to the spectre_bhb_loop_affected() lists")
> Signed-off-by: Will Deacon <will@kernel.org>
> ---
> arch/arm64/kernel/proton-pack.c | 2 ++
> 1 file changed, 2 insertions(+)
Crud. Thanks for the fix.
Reviewed-by: Douglas Anderson <dianders@chromium.org>
-Doug
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] arm64: errata: Add missing sentinels to Spectre-BHB MIDR arrays
2025-05-01 10:47 [PATCH] arm64: errata: Add missing sentinels to Spectre-BHB MIDR arrays Will Deacon
2025-05-01 11:33 ` Lee Jones
2025-05-01 14:12 ` Doug Anderson
@ 2025-05-01 15:43 ` Greg Kroah-Hartman
2025-05-01 16:46 ` Catalin Marinas
3 siblings, 0 replies; 5+ messages in thread
From: Greg Kroah-Hartman @ 2025-05-01 15:43 UTC (permalink / raw)
To: Will Deacon
Cc: linux-arm-kernel, Lee Jones, James Morse, Doug Anderson,
Shameer Kolothum, Catalin Marinas
On Thu, May 01, 2025 at 11:47:47AM +0100, Will Deacon wrote:
> Commit a5951389e58d ("arm64: errata: Add newer ARM cores to the
> spectre_bhb_loop_affected() lists") added some additional CPUs to the
> Spectre-BHB workaround, including some new arrays for designs that
> require new 'k' values for the workaround to be effective.
>
> Unfortunately, the new arrays omitted the sentinel entry and so
> is_midr_in_range_list() will walk off the end when it doesn't find a
> match. With UBSAN enabled, this leads to a crash during boot when
> is_midr_in_range_list() is inlined (which was more common prior to
> c8c2647e69be ("arm64: Make _midr_in_range_list() an exported
> function")):
>
> | Internal error: aarch64 BRK: 00000000f2000001 [#1] PREEMPT SMP
> | pstate: 804000c5 (Nzcv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> | pc : spectre_bhb_loop_affected+0x28/0x30
> | lr : is_spectre_bhb_affected+0x170/0x190
> | [...]
> | Call trace:
> | spectre_bhb_loop_affected+0x28/0x30
> | update_cpu_capabilities+0xc0/0x184
> | init_cpu_features+0x188/0x1a4
> | cpuinfo_store_boot_cpu+0x4c/0x60
> | smp_prepare_boot_cpu+0x38/0x54
> | start_kernel+0x8c/0x478
> | __primary_switched+0xc8/0xd4
> | Code: 6b09011f 54000061 52801080 d65f03c0 (d4200020)
> | ---[ end trace 0000000000000000 ]---
> | Kernel panic - not syncing: aarch64 BRK: Fatal exception
>
> Add the missing sentinel entries.
>
> Cc: Lee Jones <lee@kernel.org>
> Cc: James Morse <james.morse@arm.com>
> Cc: Doug Anderson <dianders@chromium.org>
> Cc: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Reported-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Fixes: a5951389e58d ("arm64: errata: Add newer ARM cores to the spectre_bhb_loop_affected() lists")
> Signed-off-by: Will Deacon <will@kernel.org>
> ---
> arch/arm64/kernel/proton-pack.c | 2 ++
> 1 file changed, 2 insertions(+)
Cc: stable <stable@kernel.org>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] arm64: errata: Add missing sentinels to Spectre-BHB MIDR arrays
2025-05-01 10:47 [PATCH] arm64: errata: Add missing sentinels to Spectre-BHB MIDR arrays Will Deacon
` (2 preceding siblings ...)
2025-05-01 15:43 ` Greg Kroah-Hartman
@ 2025-05-01 16:46 ` Catalin Marinas
3 siblings, 0 replies; 5+ messages in thread
From: Catalin Marinas @ 2025-05-01 16:46 UTC (permalink / raw)
To: linux-arm-kernel, Will Deacon
Cc: Lee Jones, James Morse, Doug Anderson, Shameer Kolothum,
Greg Kroah-Hartman
On Thu, 01 May 2025 11:47:47 +0100, Will Deacon wrote:
> Commit a5951389e58d ("arm64: errata: Add newer ARM cores to the
> spectre_bhb_loop_affected() lists") added some additional CPUs to the
> Spectre-BHB workaround, including some new arrays for designs that
> require new 'k' values for the workaround to be effective.
>
> Unfortunately, the new arrays omitted the sentinel entry and so
> is_midr_in_range_list() will walk off the end when it doesn't find a
> match. With UBSAN enabled, this leads to a crash during boot when
> is_midr_in_range_list() is inlined (which was more common prior to
> c8c2647e69be ("arm64: Make _midr_in_range_list() an exported
> function")):
>
> [...]
Applied to arm64 (for-next/fixes), thanks!
[1/1] arm64: errata: Add missing sentinels to Spectre-BHB MIDR arrays
https://git.kernel.org/arm64/c/fee4d171451c
--
Catalin
^ permalink raw reply [flat|nested] 5+ messages in thread