From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 80796C3ABAC for ; Tue, 6 May 2025 15:52:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=+hKZIA+D2QHChYlx8x2iKgNjsn6+0BDfx+Ur4DoIGak=; b=lPWJDdVJuubAlgMl+0/x0tWAMe I0F+1JwzJtRz2wM0VSq6/Kjl4c7/O+ZLcQgbOxMHI1Q54fUb92m3ZeVDi/nnSy/7qhWkPHmk7Dsvc fQm3uqQiYYAixHMogrx4AZ5kncCb2guSNIRON4mWkB7pr17CgUosmI++C3fDWfC/8J0ow+wAWE6ZC 61vlWLq8galFEwMguwDUAKh0KO4CmbgUHS9/IA5dbUJjcj4nQUd05lhsJsqQLEg4VVEXHL+Gu/kmJ bsRGav1hV2ceDlJ8OYrp3qGzzM1HtLviOONXgrxJoeI6Q3X2xxJcGtNUXfuYeg5Gz+1iC0rZ3SLyg e1A1AglA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uCKai-0000000CYlm-2jJN; Tue, 06 May 2025 15:52:20 +0000 Received: from tor.source.kernel.org ([2600:3c04:e001:324:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uCHMJ-0000000BtdE-3eag for linux-arm-kernel@lists.infradead.org; Tue, 06 May 2025 12:25:15 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 50C996154C; Tue, 6 May 2025 12:25:15 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 20921C4CEED; Tue, 6 May 2025 12:25:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1746534315; bh=dDrbPic70xFVMnGI2U6eslEy81yc+v4juJuGar89STY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=LbjSjXAVhVSlEHcrJzX7tgIA89wQSsrb4eBKyzvPN3BFVrT5I+VhjxmR93MK4f8xk vBsXVFaL9vnObqFl9NCj7nCsNX2+T4Hky5kCCk8pW5om9qUQmAuei/8mhic7+yXnAV YrEtF1Lnq5CCc6UinWafNu7i7SVBcAYrqZoVMJX7uZ4r61CMupczbQJrICKbzDItF1 YXg9mPeQhKV0CflYou/kMFz4Cq8p8v5QBAb3onCj2dK0mQ/cVwVBV8EPN1Ol0Klh5w 1g8cXa0DDA/RHiXHhIbG+18fx2CR+sCESRONWTtAJYWAeP88wbMq7/SMCpS0fSmGKV vRb5G+7I54q+A== From: Lorenzo Pieralisi Date: Tue, 06 May 2025 14:23:46 +0200 Subject: [PATCH v3 17/25] arm64: cpucaps: Add GICv5 CPU interface (GCIE) capability MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250506-gicv5-host-v3-17-6edd5a92fd09@kernel.org> References: <20250506-gicv5-host-v3-0-6edd5a92fd09@kernel.org> In-Reply-To: <20250506-gicv5-host-v3-0-6edd5a92fd09@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , Jiri Slaby , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Implement the GCIE capability as a strict boot cpu capability to detect whether architectural GICv5 support is available in HW. Plug it in with a naming consistent with the existing GICv3 CPU interface capability. Signed-off-by: Lorenzo Pieralisi Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier --- arch/arm64/kernel/cpufeature.c | 7 +++++++ arch/arm64/tools/cpucaps | 1 + 2 files changed, 8 insertions(+) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index cbb49de451f45fbee3100ea01e77b06352bd55ac..4d5163a20ee0fb09380ea5f1f2d37afb7257edfb 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -3041,6 +3041,13 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_pmuv3, }, #endif + { + .desc = "GICv5 CPU interface", + .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, + .capability = ARM64_HAS_GICV5_CPUIF, + .matches = has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, GCIE, IMP) + }, {}, }; diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 860ec49cc0530885c138b7dc7f67d58cd69b2593..c36f4165e2bb460abde81baf453199f62dd265b0 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -35,6 +35,7 @@ HAS_GENERIC_AUTH_ARCH_QARMA3 HAS_GENERIC_AUTH_ARCH_QARMA5 HAS_GENERIC_AUTH_IMP_DEF HAS_GICV3_CPUIF +HAS_GICV5_CPUIF HAS_GIC_PRIO_MASKING HAS_GIC_PRIO_RELAXED_SYNC HAS_HCR_NV1 -- 2.48.0