* [PATCH 1/4] arm64: dts: ti: k3-am62-phycore-som: Enable Co-processors
2025-05-06 11:54 [PATCH 0/4] {am62,am62a}-phycore-som: Add R5F and C7xv device nodes Daniel Schultz
@ 2025-05-06 11:54 ` Daniel Schultz
2025-05-06 14:16 ` Andrew Davis
2025-05-06 11:55 ` [PATCH 2/4] arm64: dts: ti: k3-am62a-phycore-som: " Daniel Schultz
` (4 subsequent siblings)
5 siblings, 1 reply; 8+ messages in thread
From: Daniel Schultz @ 2025-05-06 11:54 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt, linux-arm-kernel,
devicetree, linux-kernel
Cc: upstream, Daniel Schultz
For every remote processor, set up dedicated memory regions and
associate the required mailbox channels. Allocate two memory areas
per remote core: one 1MB region for vring shared buffers, and
another for external memory used by the remote processor for its
resource table and trace buffer.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
---
.../boot/dts/ti/k3-am62-phycore-som.dtsi | 35 +++++++++++++++----
1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi
index 2ef4cbaec789..71d165a7abe0 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi
@@ -57,6 +57,18 @@ mcu_m4fss_memory_region: m4f-memory@9cc00000 {
no-map;
};
+ wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9da00000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0x9da00000 0x00 0x100000>;
+ no-map;
+ };
+
+ wkup_r5fss0_core0_memory_region: r5f-memory@9db00000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0x9db00000 0x00 0xc00000>;
+ no-map;
+ };
+
secure_tfa_ddr: tfa@9e780000 {
reg = <0x00 0x9e780000 0x00 0x80000>;
alignment = <0x1000>;
@@ -68,12 +80,6 @@ secure_ddr: optee@9e800000 {
alignment = <0x1000>;
no-map;
};
-
- wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0x9db00000 0x00 0x00c00000>;
- no-map;
- };
};
vcc_5v0_som: regulator-vcc-5v0-som {
@@ -226,10 +232,17 @@ cpsw3g_phy1: ethernet-phy@1 {
};
&mailbox0_cluster0 {
+ status = "okay";
+
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 0>;
ti,mbox-tx = <1 0 0>;
};
+
+ mbox_r5_0: mbox-r5-0 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
};
&main_i2c0 {
@@ -365,3 +378,13 @@ &sdhci0 {
non-removable;
status = "okay";
};
+
+&wkup_r5fss0 {
+ status = "okay";
+};
+
+&wkup_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
+ memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
+ <&wkup_r5fss0_core0_memory_region>;
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 1/4] arm64: dts: ti: k3-am62-phycore-som: Enable Co-processors
2025-05-06 11:54 ` [PATCH 1/4] arm64: dts: ti: k3-am62-phycore-som: Enable Co-processors Daniel Schultz
@ 2025-05-06 14:16 ` Andrew Davis
0 siblings, 0 replies; 8+ messages in thread
From: Andrew Davis @ 2025-05-06 14:16 UTC (permalink / raw)
To: Daniel Schultz, nm, vigneshr, kristo, robh, krzk+dt, conor+dt,
linux-arm-kernel, devicetree, linux-kernel
Cc: upstream
On 5/6/25 6:54 AM, Daniel Schultz wrote:
> For every remote processor, set up dedicated memory regions and
> associate the required mailbox channels. Allocate two memory areas
> per remote core: one 1MB region for vring shared buffers, and
> another for external memory used by the remote processor for its
> resource table and trace buffer.
>
> Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
> ---
Reviewed-by: Andrew Davis <afd@ti.com>
> .../boot/dts/ti/k3-am62-phycore-som.dtsi | 35 +++++++++++++++----
> 1 file changed, 29 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi
> index 2ef4cbaec789..71d165a7abe0 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi
> @@ -57,6 +57,18 @@ mcu_m4fss_memory_region: m4f-memory@9cc00000 {
> no-map;
> };
>
> + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9da00000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0x9da00000 0x00 0x100000>;
> + no-map;
> + };
> +
> + wkup_r5fss0_core0_memory_region: r5f-memory@9db00000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0x9db00000 0x00 0xc00000>;
> + no-map;
> + };
> +
> secure_tfa_ddr: tfa@9e780000 {
> reg = <0x00 0x9e780000 0x00 0x80000>;
> alignment = <0x1000>;
> @@ -68,12 +80,6 @@ secure_ddr: optee@9e800000 {
> alignment = <0x1000>;
> no-map;
> };
> -
> - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
> - compatible = "shared-dma-pool";
> - reg = <0x00 0x9db00000 0x00 0x00c00000>;
> - no-map;
> - };
> };
>
> vcc_5v0_som: regulator-vcc-5v0-som {
> @@ -226,10 +232,17 @@ cpsw3g_phy1: ethernet-phy@1 {
> };
>
> &mailbox0_cluster0 {
> + status = "okay";
> +
> mbox_m4_0: mbox-m4-0 {
> ti,mbox-rx = <0 0 0>;
> ti,mbox-tx = <1 0 0>;
> };
> +
> + mbox_r5_0: mbox-r5-0 {
> + ti,mbox-rx = <2 0 0>;
> + ti,mbox-tx = <3 0 0>;
> + };
> };
>
> &main_i2c0 {
> @@ -365,3 +378,13 @@ &sdhci0 {
> non-removable;
> status = "okay";
> };
> +
> +&wkup_r5fss0 {
> + status = "okay";
> +};
> +
> +&wkup_r5fss0_core0 {
> + mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
> + memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
> + <&wkup_r5fss0_core0_memory_region>;
> +};
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/4] arm64: dts: ti: k3-am62a-phycore-som: Enable Co-processors
2025-05-06 11:54 [PATCH 0/4] {am62,am62a}-phycore-som: Add R5F and C7xv device nodes Daniel Schultz
2025-05-06 11:54 ` [PATCH 1/4] arm64: dts: ti: k3-am62-phycore-som: Enable Co-processors Daniel Schultz
@ 2025-05-06 11:55 ` Daniel Schultz
2025-05-06 11:55 ` [PATCH 3/4] arm64: dts: ti: k3-am62a-phycore-som: Reserve main_rti4 for C7x DSP Daniel Schultz
` (3 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Daniel Schultz @ 2025-05-06 11:55 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt, linux-arm-kernel,
devicetree, linux-kernel
Cc: upstream, Daniel Schultz
For every remote processor, set up dedicated memory regions and
associate the required mailbox channels. Allocate two memory areas
per remote core: one 1MB region for vring shared buffers, and
another for external memory used by the remote processor for its
resource table and trace buffer.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
---
.../boot/dts/ti/k3-am62a-phycore-som.dtsi | 96 +++++++++++++++++--
1 file changed, 90 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
index a5aceaa39670..fc252543f18a 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
@@ -58,6 +58,42 @@ linux,cma {
linux,cma-default;
};
+ c7x_0_dma_memory_region: c7x-dma-memory@99800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0x99800000 0x00 0x100000>;
+ no-map;
+ };
+
+ c7x_0_memory_region: c7x-memory@99900000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0x99900000 0x00 0xf00000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0x9b800000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0x9b900000 0x00 0xf00000>;
+ no-map;
+ };
+
+ wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0x9c800000 0x00 0x100000>;
+ no-map;
+ };
+
+ wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0x9c900000 0x00 0xf00000>;
+ no-map;
+ };
+
secure_tfa_ddr: tfa@9e780000 {
reg = <0x00 0x9e780000 0x00 0x80000>;
alignment = <0x1000>;
@@ -69,12 +105,6 @@ secure_ddr: optee@9e800000 {
alignment = <0x1000>;
no-map;
};
-
- wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 {
- compatible = "shared-dma-pool";
- reg = <0x00 0x9c900000 0x00 0x01e00000>;
- no-map;
- };
};
vcc_5v0_som: regulator-vcc-5v0-som {
@@ -164,6 +194,13 @@ AM62AX_IOPAD(0x1f4, PIN_INPUT, 0) /* (D16) EXTINTn */
};
};
+&c7x_0 {
+ mboxes = <&mailbox0_cluster1>, <&mbox_c7x_0>;
+ memory-region = <&c7x_0_dma_memory_region>,
+ <&c7x_0_memory_region>;
+ status = "okay";
+};
+
&cpsw3g {
status = "okay";
pinctrl-names = "default";
@@ -192,6 +229,33 @@ &fss {
status = "okay";
};
+&mailbox0_cluster0 {
+ status = "okay";
+
+ mbox_r5_0: mbox-r5-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+};
+
+&mailbox0_cluster1 {
+ status = "okay";
+
+ mbox_c7x_0: mbox-c7x-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+};
+
+&mailbox0_cluster2 {
+ status = "okay";
+
+ mbox_mcu_r5_0: mbox-mcu-r5-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+};
+
&main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
@@ -302,6 +366,16 @@ &main_gpio_intr {
status = "okay";
};
+&mcu_r5fss0 {
+ status = "okay";
+};
+
+&mcu_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster2>, <&mbox_mcu_r5_0>;
+ memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+ <&mcu_r5fss0_core0_memory_region>;
+};
+
&ospi0 {
pinctrl-names = "default";
pinctrl-0 = <&ospi0_pins_default>;
@@ -328,3 +402,13 @@ &sdhci0 {
non-removable;
status = "okay";
};
+
+&wkup_r5fss0 {
+ status = "okay";
+};
+
+&wkup_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster0>, <&mbox_r5_0>;
+ memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
+ <&wkup_r5fss0_core0_memory_region>;
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 3/4] arm64: dts: ti: k3-am62a-phycore-som: Reserve main_rti4 for C7x DSP
2025-05-06 11:54 [PATCH 0/4] {am62,am62a}-phycore-som: Add R5F and C7xv device nodes Daniel Schultz
2025-05-06 11:54 ` [PATCH 1/4] arm64: dts: ti: k3-am62-phycore-som: Enable Co-processors Daniel Schultz
2025-05-06 11:55 ` [PATCH 2/4] arm64: dts: ti: k3-am62a-phycore-som: " Daniel Schultz
@ 2025-05-06 11:55 ` Daniel Schultz
2025-05-06 11:55 ` [PATCH 4/4] arm64: dts: ti: k3-am62a-phycore-som: Reserve main_timer2 " Daniel Schultz
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Daniel Schultz @ 2025-05-06 11:55 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt, linux-arm-kernel,
devicetree, linux-kernel
Cc: upstream, Daniel Schultz
The main rti4 watchdog timer is used by the C7x DSP, so reserve the
timer in the linux device tree.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
---
arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
index fc252543f18a..343118af448b 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
@@ -366,6 +366,11 @@ &main_gpio_intr {
status = "okay";
};
+/* main_rti4 is used by C7x DSP */
+&main_rti4 {
+ status = "reserved";
+};
+
&mcu_r5fss0 {
status = "okay";
};
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 4/4] arm64: dts: ti: k3-am62a-phycore-som: Reserve main_timer2 for C7x DSP
2025-05-06 11:54 [PATCH 0/4] {am62,am62a}-phycore-som: Add R5F and C7xv device nodes Daniel Schultz
` (2 preceding siblings ...)
2025-05-06 11:55 ` [PATCH 3/4] arm64: dts: ti: k3-am62a-phycore-som: Reserve main_rti4 for C7x DSP Daniel Schultz
@ 2025-05-06 11:55 ` Daniel Schultz
2025-05-06 13:31 ` [Upstream] [PATCH 0/4] {am62,am62a}-phycore-som: Add R5F and C7xv device nodes Wadim Egorov
2025-05-06 16:14 ` Judith Mendez
5 siblings, 0 replies; 8+ messages in thread
From: Daniel Schultz @ 2025-05-06 11:55 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt, linux-arm-kernel,
devicetree, linux-kernel
Cc: upstream, Daniel Schultz
C7x DSP uses main_timer2, so mark it as reserved in linux DT.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
---
arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
index 343118af448b..b6c46c410b78 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
@@ -371,6 +371,11 @@ &main_rti4 {
status = "reserved";
};
+/* main_timer2 is used by C7x DSP */
+&main_timer2 {
+ status = "reserved";
+};
+
&mcu_r5fss0 {
status = "okay";
};
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [Upstream] [PATCH 0/4] {am62,am62a}-phycore-som: Add R5F and C7xv device nodes
2025-05-06 11:54 [PATCH 0/4] {am62,am62a}-phycore-som: Add R5F and C7xv device nodes Daniel Schultz
` (3 preceding siblings ...)
2025-05-06 11:55 ` [PATCH 4/4] arm64: dts: ti: k3-am62a-phycore-som: Reserve main_timer2 " Daniel Schultz
@ 2025-05-06 13:31 ` Wadim Egorov
2025-05-06 16:14 ` Judith Mendez
5 siblings, 0 replies; 8+ messages in thread
From: Wadim Egorov @ 2025-05-06 13:31 UTC (permalink / raw)
To: Daniel Schultz, nm, vigneshr, kristo, robh, krzk+dt, conor+dt,
linux-arm-kernel, devicetree, linux-kernel
Cc: upstream
Am 06.05.25 um 14:54 schrieb Daniel Schultz:
> This patch series is based on [1] and adds these R5F and C7xv device nodes
> to the am62- and am62a-phycore-som device-trees. It also reserves main_timer2
> as well as main_rti4 for the C7 DSP firmware.
>
> 1: https://lore.kernel.org/linux-arm-kernel/20250502220325.3230653-1-jm@ti.com/T/#t
>
> Daniel Schultz (4):
> arm64: dts: ti: k3-am62-phycore-som: Enable Co-processors
> arm64: dts: ti: k3-am62a-phycore-som: Enable Co-processors
> arm64: dts: ti: k3-am62a-phycore-som: Reserve main_rti4 for C7x DSP
> arm64: dts: ti: k3-am62a-phycore-som: Reserve main_timer2 for C7x DSP
Patches do not apply on master
>
> .../boot/dts/ti/k3-am62-phycore-som.dtsi | 35 +++++-
> .../boot/dts/ti/k3-am62a-phycore-som.dtsi | 106 +++++++++++++++++-
> 2 files changed, 129 insertions(+), 12 deletions(-)
>
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 0/4] {am62,am62a}-phycore-som: Add R5F and C7xv device nodes
2025-05-06 11:54 [PATCH 0/4] {am62,am62a}-phycore-som: Add R5F and C7xv device nodes Daniel Schultz
` (4 preceding siblings ...)
2025-05-06 13:31 ` [Upstream] [PATCH 0/4] {am62,am62a}-phycore-som: Add R5F and C7xv device nodes Wadim Egorov
@ 2025-05-06 16:14 ` Judith Mendez
5 siblings, 0 replies; 8+ messages in thread
From: Judith Mendez @ 2025-05-06 16:14 UTC (permalink / raw)
To: Daniel Schultz, nm
Cc: upstream, vigneshr, kristo, robh, krzk+dt, conor+dt,
linux-arm-kernel, linux-kernel, devicetree
Hello Daniel,
On 5/6/25 6:54 AM, Daniel Schultz wrote:
> This patch series is based on [1] and adds these R5F and C7xv device nodes
> to the am62- and am62a-phycore-som device-trees. It also reserves main_timer2
> as well as main_rti4 for the C7 DSP firmware.
>
> 1: https://lore.kernel.org/linux-arm-kernel/20250502220325.3230653-1-jm@ti.com/T/#t
>
For the series,
Reviewed-by: Judith Mendez <jm@ti.com>
^ permalink raw reply [flat|nested] 8+ messages in thread