[PATCH 0/5] Support RK3528 variant of Rockchip naneng-combphy

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* [PATCH 0/5] Support RK3528 variant of Rockchip naneng-combphy
@ 2025-05-08 13:43 Yao Zi
  2025-05-08 13:43 ` [PATCH 1/5] dt-bindings: soc: rockchip: Add RK3528 pipe-phy GRF syscon Yao Zi
                   ` (4 more replies)
  0 siblings, 5 replies; 12+ messages in thread
From: Yao Zi @ 2025-05-08 13:43 UTC (permalink / raw)
  To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Yao Zi,
	Frank Wang, Andy Yan, Cristian Ciocaltea, Detlev Casanova,
	Shresth Prasad, Chukun Pan, Jonas Karlman
  Cc: linux-phy, devicetree, linux-arm-kernel, linux-rockchip,
	linux-kernel

Rockchip RK3528 ships a naneng-combphy that operates in either PCIe or
USB 3.0 mode. It has a similar control logic to previous generations of
naneng-combphy but an apparently different register layout.

This series prepares phy-rockchip-naneng-combphy.c for variants with a
different register layout and add RK3528 support.

Testing is done on both Radxa E20C and Radxa Rock 2A with downstream
devicetree changes, both USB 3 and PCIe modes are verified with mainline
driver and achives a reasonable link speed.

The devicetree change (PATCH 5) depend on v5 of the SD/SDIO series
("Support SD/SDIO controllers on RK3528")[1] for a clean apply. Thanks
for your time and review.

[1]: https://lore.kernel.org/all/20250506092206.46143-1-ziyao@disroot.org/

Yao Zi (5):
  dt-bindings: soc: rockchip: Add RK3528 pipe-phy GRF syscon
  dt-bindings: phy: rockchip: naneng-combphy: Add RK3528 variant
  phy: rockchip: naneng-combphy: Add SoC prefix to register definitions
  phy: rockchip: naneng-combphy: Add RK3528 support
  arm64: dts: rockchip: Add naneng-combphy for RK3528

 .../phy/phy-rockchip-naneng-combphy.yaml      |   5 +-
 .../devicetree/bindings/soc/rockchip/grf.yaml |   1 +
 arch/arm64/boot/dts/rockchip/rk3528.dtsi      |  23 +
 .../rockchip/phy-rockchip-naneng-combphy.c    | 740 +++++++++++-------
 4 files changed, 495 insertions(+), 274 deletions(-)

-- 
2.49.0

^ permalink raw reply	[flat|nested] 12+ messages in thread

* [PATCH 1/5] dt-bindings: soc: rockchip: Add RK3528 pipe-phy GRF syscon
  2025-05-08 13:43 [PATCH 0/5] Support RK3528 variant of Rockchip naneng-combphy Yao Zi
@ 2025-05-08 13:43 ` Yao Zi
  2025-05-08 14:40   ` Conor Dooley
  2025-05-08 13:43 ` [PATCH 2/5] dt-bindings: phy: rockchip: naneng-combphy: Add RK3528 variant Yao Zi
                   ` (3 subsequent siblings)
  4 siblings, 1 reply; 12+ messages in thread
From: Yao Zi @ 2025-05-08 13:43 UTC (permalink / raw)
  To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Yao Zi,
	Frank Wang, Andy Yan, Cristian Ciocaltea, Detlev Casanova,
	Shresth Prasad, Chukun Pan, Jonas Karlman
  Cc: linux-phy, devicetree, linux-arm-kernel, linux-rockchip,
	linux-kernel

Add compatible string for pipe-phy GRF found on RK3528 SoC, which
controls misc settings for the integrated naneng-combphy.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index 2f61c1b95fea..7e9321999435 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -16,6 +16,7 @@ properties:
           - enum:
               - rockchip,rk3288-sgrf
               - rockchip,rk3528-ioc-grf
+              - rockchip,rk3528-pipe-phy-grf
               - rockchip,rk3528-vo-grf
               - rockchip,rk3528-vpu-grf
               - rockchip,rk3566-pipe-grf
-- 
2.49.0



^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH 2/5] dt-bindings: phy: rockchip: naneng-combphy: Add RK3528 variant
  2025-05-08 13:43 [PATCH 0/5] Support RK3528 variant of Rockchip naneng-combphy Yao Zi
  2025-05-08 13:43 ` [PATCH 1/5] dt-bindings: soc: rockchip: Add RK3528 pipe-phy GRF syscon Yao Zi
@ 2025-05-08 13:43 ` Yao Zi
  2025-05-08 14:40   ` Conor Dooley
  2025-05-08 17:15   ` Heiko Stuebner
  2025-05-08 13:52 ` [PATCH 3/5] phy: rockchip: naneng-combphy: Add SoC prefix to register definitions Yao Zi
                   ` (2 subsequent siblings)
  4 siblings, 2 replies; 12+ messages in thread
From: Yao Zi @ 2025-05-08 13:43 UTC (permalink / raw)
  To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Yao Zi,
	Frank Wang, Andy Yan, Cristian Ciocaltea, Detlev Casanova,
	Shresth Prasad, Chukun Pan, Jonas Karlman
  Cc: linux-phy, devicetree, linux-arm-kernel, linux-rockchip,
	linux-kernel

Rockchip RK3528 ships one naneng-combphy which operates in either PCIe
or USB 3 mode. Document its compatible string.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 .../devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
index 888e6b2aac5a..bd064754e537 100644
--- a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
@@ -12,6 +12,7 @@ maintainers:
 properties:
   compatible:
     enum:
+      - rockchip,rk3528-naneng-combphy
       - rockchip,rk3562-naneng-combphy
       - rockchip,rk3568-naneng-combphy
       - rockchip,rk3576-naneng-combphy
@@ -102,7 +103,9 @@ allOf:
       properties:
         compatible:
           contains:
-            const: rockchip,rk3588-naneng-combphy
+            enum:
+             - rockchip,rk3528-naneng-combphy
+             - rockchip,rk3588-naneng-combphy
     then:
       properties:
         resets:
-- 
2.49.0



^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH 3/5] phy: rockchip: naneng-combphy: Add SoC prefix to register definitions
  2025-05-08 13:43 [PATCH 0/5] Support RK3528 variant of Rockchip naneng-combphy Yao Zi
  2025-05-08 13:43 ` [PATCH 1/5] dt-bindings: soc: rockchip: Add RK3528 pipe-phy GRF syscon Yao Zi
  2025-05-08 13:43 ` [PATCH 2/5] dt-bindings: phy: rockchip: naneng-combphy: Add RK3528 variant Yao Zi
@ 2025-05-08 13:52 ` Yao Zi
  2025-05-08 17:22   ` Heiko Stuebner
  2025-05-08 13:53 ` [PATCH 4/5] phy: rockchip: naneng-combphy: Add RK3528 support Yao Zi
  2025-05-08 13:53 ` [PATCH 5/5] arm64: dts: rockchip: Add naneng-combphy for RK3528 Yao Zi
  4 siblings, 1 reply; 12+ messages in thread
From: Yao Zi @ 2025-05-08 13:52 UTC (permalink / raw)
  To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Yao Zi,
	Frank Wang, Andy Yan, Cristian Ciocaltea, Detlev Casanova,
	Shresth Prasad, Chukun Pan, Jonas Karlman
  Cc: linux-phy, devicetree, linux-arm-kernel, linux-rockchip,
	linux-kernel

All supported variants of naneng-combphy follow a register layout
similar to the RK3568 variant with some exceptions of SoC-specific
registers.

Add RK3568 prefix for the common set of registers and the corresponding
SoC prefix for SoC-specific registers, making usage of definitions clear
and preparing for future COMBPHY variants with a different register
layout.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 .../rockchip/phy-rockchip-naneng-combphy.c    | 560 +++++++++---------
 1 file changed, 288 insertions(+), 272 deletions(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index ce91fb1d5167..1d1c7723584b 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -21,78 +21,80 @@
 #define REF_CLOCK_100MHz		(100 * HZ_PER_MHZ)
 
 /* COMBO PHY REG */
-#define PHYREG6				0x14
-#define PHYREG6_PLL_DIV_MASK		GENMASK(7, 6)
-#define PHYREG6_PLL_DIV_SHIFT		6
-#define PHYREG6_PLL_DIV_2		1
-
-#define PHYREG7				0x18
-#define PHYREG7_TX_RTERM_MASK		GENMASK(7, 4)
-#define PHYREG7_TX_RTERM_SHIFT		4
-#define PHYREG7_TX_RTERM_50OHM		8
-#define PHYREG7_RX_RTERM_MASK		GENMASK(3, 0)
-#define PHYREG7_RX_RTERM_SHIFT		0
-#define PHYREG7_RX_RTERM_44OHM		15
-
-#define PHYREG8				0x1C
-#define PHYREG8_SSC_EN			BIT(4)
-
-#define PHYREG10			0x24
-#define PHYREG10_SSC_PCM_MASK		GENMASK(3, 0)
-#define PHYREG10_SSC_PCM_3500PPM	7
-
-#define PHYREG11			0x28
-#define PHYREG11_SU_TRIM_0_7		0xF0
-
-#define PHYREG12			0x2C
-#define PHYREG12_PLL_LPF_ADJ_VALUE	4
-
-#define PHYREG13			0x30
-#define PHYREG13_RESISTER_MASK		GENMASK(5, 4)
-#define PHYREG13_RESISTER_SHIFT		0x4
-#define PHYREG13_RESISTER_HIGH_Z	3
-#define PHYREG13_CKRCV_AMP0		BIT(7)
-
-#define PHYREG14			0x34
-#define PHYREG14_CKRCV_AMP1		BIT(0)
-
-#define PHYREG15			0x38
-#define PHYREG15_CTLE_EN		BIT(0)
-#define PHYREG15_SSC_CNT_MASK		GENMASK(7, 6)
-#define PHYREG15_SSC_CNT_SHIFT		6
-#define PHYREG15_SSC_CNT_VALUE		1
-
-#define PHYREG16			0x3C
-#define PHYREG16_SSC_CNT_VALUE		0x5f
-
-#define PHYREG17			0x40
-
-#define PHYREG18			0x44
-#define PHYREG18_PLL_LOOP		0x32
-
-#define PHYREG21			0x50
-#define PHYREG21_RX_SQUELCH_VAL		0x0D
-
-#define PHYREG27			0x6C
-#define PHYREG27_RX_TRIM_RK3588		0x4C
-
-#define PHYREG30			0x74
-
-#define PHYREG32			0x7C
-#define PHYREG32_SSC_MASK		GENMASK(7, 4)
-#define PHYREG32_SSC_DIR_MASK		GENMASK(5, 4)
-#define PHYREG32_SSC_DIR_SHIFT		4
-#define PHYREG32_SSC_UPWARD		0
-#define PHYREG32_SSC_DOWNWARD		1
-#define PHYREG32_SSC_OFFSET_MASK	GENMASK(7, 6)
-#define PHYREG32_SSC_OFFSET_SHIFT	6
-#define PHYREG32_SSC_OFFSET_500PPM	1
-
-#define PHYREG33			0x80
-#define PHYREG33_PLL_KVCO_MASK		GENMASK(4, 2)
-#define PHYREG33_PLL_KVCO_SHIFT		2
-#define PHYREG33_PLL_KVCO_VALUE		2
-#define PHYREG33_PLL_KVCO_VALUE_RK3576	4
+#define RK3568_PHYREG6				0x14
+#define RK3568_PHYREG6_PLL_DIV_MASK		GENMASK(7, 6)
+#define RK3568_PHYREG6_PLL_DIV_SHIFT		6
+#define RK3568_PHYREG6_PLL_DIV_2		1
+
+#define RK3568_PHYREG7				0x18
+#define RK3568_PHYREG7_TX_RTERM_MASK		GENMASK(7, 4)
+#define RK3568_PHYREG7_TX_RTERM_SHIFT		4
+#define RK3568_PHYREG7_TX_RTERM_50OHM		8
+#define RK3568_PHYREG7_RX_RTERM_MASK		GENMASK(3, 0)
+#define RK3568_PHYREG7_RX_RTERM_SHIFT		0
+#define RK3568_PHYREG7_RX_RTERM_44OHM		15
+
+#define RK3568_PHYREG8				0x1C
+#define RK3568_PHYREG8_SSC_EN			BIT(4)
+
+#define RK3568_PHYREG11				0x28
+#define RK3568_PHYREG11_SU_TRIM_0_7		0xF0
+
+#define RK3568_PHYREG12				0x2C
+#define RK3568_PHYREG12_PLL_LPF_ADJ_VALUE	4
+
+#define RK3568_PHYREG13				0x30
+#define RK3568_PHYREG13_RESISTER_MASK		GENMASK(5, 4)
+#define RK3568_PHYREG13_RESISTER_SHIFT		0x4
+#define RK3568_PHYREG13_RESISTER_HIGH_Z		3
+#define RK3568_PHYREG13_CKRCV_AMP0		BIT(7)
+
+#define RK3568_PHYREG14				0x34
+#define RK3568_PHYREG14_CKRCV_AMP1		BIT(0)
+
+#define RK3568_PHYREG15				0x38
+#define RK3568_PHYREG15_CTLE_EN			BIT(0)
+#define RK3568_PHYREG15_SSC_CNT_MASK		GENMASK(7, 6)
+#define RK3568_PHYREG15_SSC_CNT_SHIFT		6
+#define RK3568_PHYREG15_SSC_CNT_VALUE		1
+
+#define RK3568_PHYREG16				0x3C
+#define RK3568_PHYREG16_SSC_CNT_VALUE		0x5f
+
+#define RK3568_PHYREG18				0x44
+#define RK3568_PHYREG18_PLL_LOOP		0x32
+
+#define RK3568_PHYREG32				0x7C
+#define RK3568_PHYREG32_SSC_MASK		GENMASK(7, 4)
+#define RK3568_PHYREG32_SSC_DIR_MASK		GENMASK(5, 4)
+#define RK3568_PHYREG32_SSC_DIR_SHIFT		4
+#define RK3568_PHYREG32_SSC_UPWARD		0
+#define RK3568_PHYREG32_SSC_DOWNWARD		1
+#define RK3568_PHYREG32_SSC_OFFSET_MASK	GENMASK(7, 6)
+#define RK3568_PHYREG32_SSC_OFFSET_SHIFT	6
+#define RK3568_PHYREG32_SSC_OFFSET_500PPM	1
+
+#define RK3568_PHYREG33				0x80
+#define RK3568_PHYREG33_PLL_KVCO_MASK		GENMASK(4, 2)
+#define RK3568_PHYREG33_PLL_KVCO_SHIFT		2
+#define RK3568_PHYREG33_PLL_KVCO_VALUE		2
+#define RK3576_PHYREG33_PLL_KVCO_VALUE		4
+
+/* RK3588 COMBO PHY registers */
+#define RK3588_PHYREG27				0x6C
+#define RK3588_PHYREG27_RX_TRIM			0x4C
+
+/* RK3576 COMBO PHY registers */
+#define RK3576_PHYREG10				0x24
+#define RK3576_PHYREG10_SSC_PCM_MASK		GENMASK(3, 0)
+#define RK3576_PHYREG10_SSC_PCM_3500PPM		7
+
+#define RK3576_PHYREG17				0x40
+
+#define RK3576_PHYREG21				0x50
+#define RK3576_PHYREG21_RX_SQUELCH_VAL		0x0D
+
+#define RK3576_PHYREG30				0x74
 
 struct rockchip_combphy_priv;
 
@@ -405,9 +407,8 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
 	switch (priv->type) {
 	case PHY_TYPE_PCIE:
 		/* Set SSC downward spread spectrum */
-		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
-					 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
-					 PHYREG32);
+		val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
+		rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
 
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
@@ -416,29 +417,30 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
 		break;
 	case PHY_TYPE_USB3:
 		/* Set SSC downward spread spectrum */
-		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
-					 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
-					 PHYREG32);
+		val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
+		rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
+					 RK3568_PHYREG32);
 
 		/* Enable adaptive CTLE for USB3.0 Rx */
-		rockchip_combphy_updatel(priv, PHYREG15_CTLE_EN,
-					 PHYREG15_CTLE_EN, PHYREG15);
+		rockchip_combphy_updatel(priv, RK3568_PHYREG15_CTLE_EN,
+					 RK3568_PHYREG15_CTLE_EN, RK3568_PHYREG15);
 
 		/* Set PLL KVCO fine tuning signals */
-		rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, BIT(3), PHYREG33);
+		rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
+					 BIT(3), RK3568_PHYREG33);
 
 		/* Set PLL LPF R1 to su_trim[10:7]=1001 */
-		writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
+		writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
 
 		/* Set PLL input clock divider 1/2 */
-		val = FIELD_PREP(PHYREG6_PLL_DIV_MASK, PHYREG6_PLL_DIV_2);
-		rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, val, PHYREG6);
+		val = FIELD_PREP(RK3568_PHYREG6_PLL_DIV_MASK, RK3568_PHYREG6_PLL_DIV_2);
+		rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, val, RK3568_PHYREG6);
 
 		/* Set PLL loop divider */
-		writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
+		writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
 
 		/* Set PLL KVCO to min and set PLL charge pump current to max */
-		writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
+		writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
 
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
@@ -456,11 +458,12 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
 	case REF_CLOCK_24MHz:
 		if (priv->type == PHY_TYPE_USB3) {
 			/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
-			val = FIELD_PREP(PHYREG15_SSC_CNT_MASK, PHYREG15_SSC_CNT_VALUE);
-			rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
-						 val, PHYREG15);
+			val = FIELD_PREP(RK3568_PHYREG15_SSC_CNT_MASK,
+					 RK3568_PHYREG15_SSC_CNT_VALUE);
+			rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK,
+						 val, RK3568_PHYREG15);
 
-			writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
+			writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
 		}
 		break;
 	case REF_CLOCK_25MHz:
@@ -470,19 +473,20 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
 		if (priv->type == PHY_TYPE_PCIE) {
 			/* PLL KVCO tuning fine */
-			val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE);
-			rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
-						 val, PHYREG33);
+			val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
+					 RK3568_PHYREG33_PLL_KVCO_VALUE);
+			rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
+						 val, RK3568_PHYREG33);
 
 			/* Enable controlling random jitter, aka RMJ */
-			writel(0x4, priv->mmio + PHYREG12);
+			writel(0x4, priv->mmio + RK3568_PHYREG12);
 
-			val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT;
-			rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
-						 val, PHYREG6);
+			val = RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT;
+			rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK,
+						 val, RK3568_PHYREG6);
 
-			writel(0x32, priv->mmio + PHYREG18);
-			writel(0xf0, priv->mmio + PHYREG11);
+			writel(0x32, priv->mmio + RK3568_PHYREG18);
+			writel(0xf0, priv->mmio + RK3568_PHYREG11);
 		}
 		break;
 	default:
@@ -493,20 +497,21 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
 	if (priv->ext_refclk) {
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
 		if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
-			val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
-			val |= PHYREG13_CKRCV_AMP0;
-			rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
-
-			val = readl(priv->mmio + PHYREG14);
-			val |= PHYREG14_CKRCV_AMP1;
-			writel(val, priv->mmio + PHYREG14);
+			val = RK3568_PHYREG13_RESISTER_HIGH_Z << RK3568_PHYREG13_RESISTER_SHIFT;
+			val |= RK3568_PHYREG13_CKRCV_AMP0;
+			rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val,
+						 RK3568_PHYREG13);
+
+			val = readl(priv->mmio + RK3568_PHYREG14);
+			val |= RK3568_PHYREG14_CKRCV_AMP1;
+			writel(val, priv->mmio + RK3568_PHYREG14);
 		}
 	}
 
 	if (priv->enable_ssc) {
-		val = readl(priv->mmio + PHYREG8);
-		val |= PHYREG8_SSC_EN;
-		writel(val, priv->mmio + PHYREG8);
+		val = readl(priv->mmio + RK3568_PHYREG8);
+		val |= RK3568_PHYREG8_SSC_EN;
+		writel(val, priv->mmio + RK3568_PHYREG8);
 	}
 
 	return 0;
@@ -553,9 +558,9 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
 	switch (priv->type) {
 	case PHY_TYPE_PCIE:
 		/* Set SSC downward spread spectrum. */
-		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
-					 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
-					 PHYREG32);
+		val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
+
+		rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
 
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
@@ -565,30 +570,28 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
 
 	case PHY_TYPE_USB3:
 		/* Set SSC downward spread spectrum. */
-		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
-					 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
-					 PHYREG32);
+		val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT,
+		rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
 
 		/* Enable adaptive CTLE for USB3.0 Rx. */
-		val = readl(priv->mmio + PHYREG15);
-		val |= PHYREG15_CTLE_EN;
-		writel(val, priv->mmio + PHYREG15);
+		val = readl(priv->mmio + RK3568_PHYREG15);
+		val |= RK3568_PHYREG15_CTLE_EN;
+		writel(val, priv->mmio + RK3568_PHYREG15);
 
 		/* Set PLL KVCO fine tuning signals. */
-		rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
-					 PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
-					 PHYREG33);
+		val = RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT;
+		rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, val, RK3568_PHYREG33);
 
 		/* Enable controlling random jitter. */
-		writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
+		writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
 
 		/* Set PLL input clock divider 1/2. */
-		rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
-					 PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
-					 PHYREG6);
+		rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK,
+					 RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT,
+					 RK3568_PHYREG6);
 
-		writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
-		writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
+		writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
+		writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
 
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
@@ -598,16 +601,16 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
 
 	case PHY_TYPE_SATA:
 		/* Enable adaptive CTLE for SATA Rx. */
-		val = readl(priv->mmio + PHYREG15);
-		val |= PHYREG15_CTLE_EN;
-		writel(val, priv->mmio + PHYREG15);
+		val = readl(priv->mmio + RK3568_PHYREG15);
+		val |= RK3568_PHYREG15_CTLE_EN;
+		writel(val, priv->mmio + RK3568_PHYREG15);
 		/*
 		 * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
 		 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
 		 */
-		val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
-		val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
-		writel(val, priv->mmio + PHYREG7);
+		val = RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT;
+		val |= RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT;
+		writel(val, priv->mmio + RK3568_PHYREG7);
 
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
@@ -642,11 +645,11 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
 	case REF_CLOCK_24MHz:
 		if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
 			/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
-			val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
-			rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
-						 val, PHYREG15);
+			val = RK3568_PHYREG15_SSC_CNT_VALUE << RK3568_PHYREG15_SSC_CNT_SHIFT;
+			rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK,
+						 val, RK3568_PHYREG15);
 
-			writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
+			writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
 		}
 		break;
 
@@ -658,24 +661,26 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
 		if (priv->type == PHY_TYPE_PCIE) {
 			/* PLL KVCO  fine tuning. */
-			val = PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT;
-			rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
-						 val, PHYREG33);
+			val = RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT;
+			rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
+						 val, RK3568_PHYREG33);
 
 			/* Enable controlling random jitter. */
-			writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
+			writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
 
-			val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT;
-			rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
-						 val, PHYREG6);
+			val = RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT;
+			rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK,
+						 val, RK3568_PHYREG6);
 
-			writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
-			writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
+			writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
+			writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
 		} else if (priv->type == PHY_TYPE_SATA) {
 			/* downward spread spectrum +500ppm */
-			val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
-			val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
-			rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
+			val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
+			val |= RK3568_PHYREG32_SSC_OFFSET_500PPM <<
+			       RK3568_PHYREG32_SSC_OFFSET_SHIFT;
+			rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
+						 RK3568_PHYREG32);
 		}
 		break;
 
@@ -687,20 +692,21 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
 	if (priv->ext_refclk) {
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
 		if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
-			val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
-			val |= PHYREG13_CKRCV_AMP0;
-			rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
-
-			val = readl(priv->mmio + PHYREG14);
-			val |= PHYREG14_CKRCV_AMP1;
-			writel(val, priv->mmio + PHYREG14);
+			val = RK3568_PHYREG13_RESISTER_HIGH_Z << RK3568_PHYREG13_RESISTER_SHIFT;
+			val |= RK3568_PHYREG13_CKRCV_AMP0;
+			rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val,
+						 RK3568_PHYREG13);
+
+			val = readl(priv->mmio + RK3568_PHYREG14);
+			val |= RK3568_PHYREG14_CKRCV_AMP1;
+			writel(val, priv->mmio + RK3568_PHYREG14);
 		}
 	}
 
 	if (priv->enable_ssc) {
-		val = readl(priv->mmio + PHYREG8);
-		val |= PHYREG8_SSC_EN;
-		writel(val, priv->mmio + PHYREG8);
+		val = readl(priv->mmio + RK3568_PHYREG8);
+		val |= RK3568_PHYREG8_SSC_EN;
+		writel(val, priv->mmio + RK3568_PHYREG8);
 	}
 
 	return 0;
@@ -759,8 +765,8 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
 	switch (priv->type) {
 	case PHY_TYPE_PCIE:
 		/* Set SSC downward spread spectrum */
-		val = FIELD_PREP(PHYREG32_SSC_MASK, PHYREG32_SSC_DOWNWARD);
-		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
+		val = FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWARD);
+		rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
 
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
@@ -770,32 +776,33 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
 
 	case PHY_TYPE_USB3:
 		/* Set SSC downward spread spectrum */
-		val = FIELD_PREP(PHYREG32_SSC_MASK, PHYREG32_SSC_DOWNWARD);
-		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
+		val = FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWARD);
+		rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
 
 		/* Enable adaptive CTLE for USB3.0 Rx */
-		val = readl(priv->mmio + PHYREG15);
-		val |= PHYREG15_CTLE_EN;
-		writel(val, priv->mmio + PHYREG15);
+		val = readl(priv->mmio + RK3568_PHYREG15);
+		val |= RK3568_PHYREG15_CTLE_EN;
+		writel(val, priv->mmio + RK3568_PHYREG15);
 
 		/* Set PLL KVCO fine tuning signals */
-		rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, BIT(3), PHYREG33);
+		rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, BIT(3),
+					 RK3568_PHYREG33);
 
 		/* Set PLL LPF R1 to su_trim[10:7]=1001 */
-		writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
+		writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
 
 		/* Set PLL input clock divider 1/2 */
-		val = FIELD_PREP(PHYREG6_PLL_DIV_MASK, PHYREG6_PLL_DIV_2);
-		rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, val, PHYREG6);
+		val = FIELD_PREP(RK3568_PHYREG6_PLL_DIV_MASK, RK3568_PHYREG6_PLL_DIV_2);
+		rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, val, RK3568_PHYREG6);
 
 		/* Set PLL loop divider */
-		writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
+		writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
 
 		/* Set PLL KVCO to min and set PLL charge pump current to max */
-		writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
+		writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
 
 		/* Set Rx squelch input filler bandwidth */
-		writel(PHYREG21_RX_SQUELCH_VAL, priv->mmio + PHYREG21);
+		writel(RK3576_PHYREG21_RX_SQUELCH_VAL, priv->mmio + RK3576_PHYREG21);
 
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
@@ -804,14 +811,14 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
 
 	case PHY_TYPE_SATA:
 		/* Enable adaptive CTLE for SATA Rx */
-		val = readl(priv->mmio + PHYREG15);
-		val |= PHYREG15_CTLE_EN;
-		writel(val, priv->mmio + PHYREG15);
+		val = readl(priv->mmio + RK3568_PHYREG15);
+		val |= RK3568_PHYREG15_CTLE_EN;
+		writel(val, priv->mmio + RK3568_PHYREG15);
 
 		/* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */
-		val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
-		val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
-		writel(val, priv->mmio + PHYREG7);
+		val = RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT;
+		val |= RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT;
+		writel(val, priv->mmio + RK3568_PHYREG7);
 
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
@@ -833,19 +840,21 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true);
 		if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
 			/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
-			val = FIELD_PREP(PHYREG15_SSC_CNT_MASK, PHYREG15_SSC_CNT_VALUE);
-			rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
-						 val, PHYREG15);
+			val = FIELD_PREP(RK3568_PHYREG15_SSC_CNT_MASK,
+					 RK3568_PHYREG15_SSC_CNT_VALUE);
+			rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK,
+						 val, RK3568_PHYREG15);
 
-			writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
+			writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
 		} else if (priv->type == PHY_TYPE_PCIE) {
 			/* PLL KVCO tuning fine */
-			val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576);
-			rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
-						 val, PHYREG33);
+			val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
+					 RK3576_PHYREG33_PLL_KVCO_VALUE);
+			rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
+						 val, RK3568_PHYREG33);
 
 			/* Set up rx_pck invert and rx msb to disable */
-			writel(0x00, priv->mmio + PHYREG27);
+			writel(0x00, priv->mmio + RK3588_PHYREG27);
 
 			/*
 			 * Set up SU adjust signal:
@@ -853,11 +862,11 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
 			 * su_trim[15:8],  PLL LPF R1 adujst bits[9:7]=3'b011
 			 * su_trim[31:24], CKDRV adjust
 			 */
-			writel(0x90, priv->mmio + PHYREG11);
-			writel(0x02, priv->mmio + PHYREG12);
-			writel(0x57, priv->mmio + PHYREG14);
+			writel(0x90, priv->mmio + RK3568_PHYREG11);
+			writel(0x02, priv->mmio + RK3568_PHYREG12);
+			writel(0x57, priv->mmio + RK3568_PHYREG14);
 
-			writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
+			writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
 		}
 		break;
 
@@ -869,15 +878,16 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
 		if (priv->type == PHY_TYPE_PCIE) {
 			/* gate_tx_pck_sel length select work for L1SS */
-			writel(0xc0, priv->mmio + PHYREG30);
+			writel(0xc0, priv->mmio + RK3576_PHYREG30);
 
 			/* PLL KVCO tuning fine */
-			val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576);
-			rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
-						 val, PHYREG33);
+			val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
+					 RK3576_PHYREG33_PLL_KVCO_VALUE);
+			rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
+						 val, RK3568_PHYREG33);
 
 			/* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
-			writel(0x4c, priv->mmio + PHYREG27);
+			writel(0x4c, priv->mmio + RK3588_PHYREG27);
 
 			/*
 			 * Set up SU adjust signal:
@@ -887,20 +897,23 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
 			 * su_trim[23:16], CKRCV adjust
 			 * su_trim[31:24], CKDRV adjust
 			 */
-			writel(0x90, priv->mmio + PHYREG11);
-			writel(0x43, priv->mmio + PHYREG12);
-			writel(0x88, priv->mmio + PHYREG13);
-			writel(0x56, priv->mmio + PHYREG14);
+			writel(0x90, priv->mmio + RK3568_PHYREG11);
+			writel(0x43, priv->mmio + RK3568_PHYREG12);
+			writel(0x88, priv->mmio + RK3568_PHYREG13);
+			writel(0x56, priv->mmio + RK3568_PHYREG14);
 		} else if (priv->type == PHY_TYPE_SATA) {
 			/* downward spread spectrum +500ppm */
-			val = FIELD_PREP(PHYREG32_SSC_DIR_MASK, PHYREG32_SSC_DOWNWARD);
-			val |= FIELD_PREP(PHYREG32_SSC_OFFSET_MASK, PHYREG32_SSC_OFFSET_500PPM);
-			rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
+			val = FIELD_PREP(RK3568_PHYREG32_SSC_DIR_MASK,
+					 RK3568_PHYREG32_SSC_DOWNWARD);
+			val |= FIELD_PREP(RK3568_PHYREG32_SSC_OFFSET_MASK,
+					  RK3568_PHYREG32_SSC_OFFSET_500PPM);
+			rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
+						 RK3568_PHYREG32);
 
 			/* ssc ppm adjust to 3500ppm */
-			rockchip_combphy_updatel(priv, PHYREG10_SSC_PCM_MASK,
-						 PHYREG10_SSC_PCM_3500PPM,
-						 PHYREG10);
+			rockchip_combphy_updatel(priv, RK3576_PHYREG10_SSC_PCM_MASK,
+						 RK3576_PHYREG10_SSC_PCM_3500PPM,
+						 RK3576_PHYREG10);
 		}
 		break;
 
@@ -912,12 +925,13 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
 	if (priv->ext_refclk) {
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
 		if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
-			val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576);
-			rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
-						 val, PHYREG33);
+			val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
+					 RK3576_PHYREG33_PLL_KVCO_VALUE);
+			rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
+						 val, RK3568_PHYREG33);
 
 			/* Set up rx_trim: PLL LPF C1 85pf R1 2.5kohm */
-			writel(0x0c, priv->mmio + PHYREG27);
+			writel(0x0c, priv->mmio + RK3588_PHYREG27);
 
 			/*
 			 * Set up SU adjust signal:
@@ -927,25 +941,25 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
 			 * su_trim[23:16], CKRCV adjust
 			 * su_trim[31:24], CKDRV adjust
 			 */
-			writel(0x90, priv->mmio + PHYREG11);
-			writel(0x43, priv->mmio + PHYREG12);
-			writel(0x88, priv->mmio + PHYREG13);
-			writel(0x56, priv->mmio + PHYREG14);
+			writel(0x90, priv->mmio + RK3568_PHYREG11);
+			writel(0x43, priv->mmio + RK3568_PHYREG12);
+			writel(0x88, priv->mmio + RK3568_PHYREG13);
+			writel(0x56, priv->mmio + RK3568_PHYREG14);
 		}
 	}
 
 	if (priv->enable_ssc) {
-		val = readl(priv->mmio + PHYREG8);
-		val |= PHYREG8_SSC_EN;
-		writel(val, priv->mmio + PHYREG8);
+		val = readl(priv->mmio + RK3568_PHYREG8);
+		val |= RK3568_PHYREG8_SSC_EN;
+		writel(val, priv->mmio + RK3568_PHYREG8);
 
 		if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_24MHz) {
 			/* Set PLL loop divider */
-			writel(0x00, priv->mmio + PHYREG17);
-			writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
+			writel(0x00, priv->mmio + RK3576_PHYREG17);
+			writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
 
 			/* Set up rx_pck invert and rx msb to disable */
-			writel(0x00, priv->mmio + PHYREG27);
+			writel(0x00, priv->mmio + RK3588_PHYREG27);
 
 			/*
 			 * Set up SU adjust signal:
@@ -954,16 +968,17 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
 			 * su_trim[23:16], CKRCV adjust
 			 * su_trim[31:24], CKDRV adjust
 			 */
-			writel(0x90, priv->mmio + PHYREG11);
-			writel(0x02, priv->mmio + PHYREG12);
-			writel(0x08, priv->mmio + PHYREG13);
-			writel(0x57, priv->mmio + PHYREG14);
-			writel(0x40, priv->mmio + PHYREG15);
+			writel(0x90, priv->mmio + RK3568_PHYREG11);
+			writel(0x02, priv->mmio + RK3568_PHYREG12);
+			writel(0x08, priv->mmio + RK3568_PHYREG13);
+			writel(0x57, priv->mmio + RK3568_PHYREG14);
+			writel(0x40, priv->mmio + RK3568_PHYREG15);
 
-			writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
+			writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
 
-			val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576);
-			writel(val, priv->mmio + PHYREG33);
+			val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
+					 RK3576_PHYREG33_PLL_KVCO_VALUE);
+			writel(val, priv->mmio + RK3568_PHYREG33);
 		}
 	}
 
@@ -1033,30 +1048,28 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
 		break;
 	case PHY_TYPE_USB3:
 		/* Set SSC downward spread spectrum */
-		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
-					 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
-					 PHYREG32);
+		val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
+		rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
 
 		/* Enable adaptive CTLE for USB3.0 Rx. */
-		val = readl(priv->mmio + PHYREG15);
-		val |= PHYREG15_CTLE_EN;
-		writel(val, priv->mmio + PHYREG15);
+		val = readl(priv->mmio + RK3568_PHYREG15);
+		val |= RK3568_PHYREG15_CTLE_EN;
+		writel(val, priv->mmio + RK3568_PHYREG15);
 
 		/* Set PLL KVCO fine tuning signals. */
-		rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
-					 PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
-					 PHYREG33);
+		val = RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT,
+		rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, val, RK3568_PHYREG33);
 
 		/* Enable controlling random jitter. */
-		writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
+		writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
 
 		/* Set PLL input clock divider 1/2. */
-		rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
-					 PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
-					 PHYREG6);
+		rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK,
+					 RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT,
+					 RK3568_PHYREG6);
 
-		writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
-		writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
+		writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
+		writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
 
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
@@ -1064,16 +1077,16 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
 		break;
 	case PHY_TYPE_SATA:
 		/* Enable adaptive CTLE for SATA Rx. */
-		val = readl(priv->mmio + PHYREG15);
-		val |= PHYREG15_CTLE_EN;
-		writel(val, priv->mmio + PHYREG15);
+		val = readl(priv->mmio + RK3568_PHYREG15);
+		val |= RK3568_PHYREG15_CTLE_EN;
+		writel(val, priv->mmio + RK3568_PHYREG15);
 		/*
 		 * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
 		 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
 		 */
-		val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
-		val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
-		writel(val, priv->mmio + PHYREG7);
+		val = RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT;
+		val |= RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT;
+		writel(val, priv->mmio + RK3568_PHYREG7);
 
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
@@ -1095,11 +1108,11 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
 	case REF_CLOCK_24MHz:
 		if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
 			/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
-			val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
-			rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
-						 val, PHYREG15);
+			val = RK3568_PHYREG15_SSC_CNT_VALUE << RK3568_PHYREG15_SSC_CNT_SHIFT;
+			rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK,
+						 val, RK3568_PHYREG15);
 
-			writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
+			writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
 		}
 		break;
 
@@ -1110,23 +1123,25 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
 		if (priv->type == PHY_TYPE_PCIE) {
 			/* PLL KVCO fine tuning. */
-			val = 4 << PHYREG33_PLL_KVCO_SHIFT;
-			rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
-						 val, PHYREG33);
+			val = 4 << RK3568_PHYREG33_PLL_KVCO_SHIFT;
+			rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
+						 val, RK3568_PHYREG33);
 
 			/* Enable controlling random jitter. */
-			writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
+			writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
 
 			/* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
-			writel(PHYREG27_RX_TRIM_RK3588, priv->mmio + PHYREG27);
+			writel(RK3588_PHYREG27_RX_TRIM, priv->mmio + RK3588_PHYREG27);
 
 			/* Set up su_trim:  */
-			writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
+			writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
 		} else if (priv->type == PHY_TYPE_SATA) {
 			/* downward spread spectrum +500ppm */
-			val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
-			val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
-			rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
+			val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
+			val |= RK3568_PHYREG32_SSC_OFFSET_500PPM <<
+			       RK3568_PHYREG32_SSC_OFFSET_SHIFT;
+			rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
+						 RK3568_PHYREG32);
 		}
 		break;
 	default:
@@ -1137,20 +1152,21 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
 	if (priv->ext_refclk) {
 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
 		if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
-			val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
-			val |= PHYREG13_CKRCV_AMP0;
-			rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
-
-			val = readl(priv->mmio + PHYREG14);
-			val |= PHYREG14_CKRCV_AMP1;
-			writel(val, priv->mmio + PHYREG14);
+			val = RK3568_PHYREG13_RESISTER_HIGH_Z << RK3568_PHYREG13_RESISTER_SHIFT;
+			val |= RK3568_PHYREG13_CKRCV_AMP0;
+			rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val,
+						 RK3568_PHYREG13);
+
+			val = readl(priv->mmio + RK3568_PHYREG14);
+			val |= RK3568_PHYREG14_CKRCV_AMP1;
+			writel(val, priv->mmio + RK3568_PHYREG14);
 		}
 	}
 
 	if (priv->enable_ssc) {
-		val = readl(priv->mmio + PHYREG8);
-		val |= PHYREG8_SSC_EN;
-		writel(val, priv->mmio + PHYREG8);
+		val = readl(priv->mmio + RK3568_PHYREG8);
+		val |= RK3568_PHYREG8_SSC_EN;
+		writel(val, priv->mmio + RK3568_PHYREG8);
 	}
 
 	return 0;
-- 
2.49.0



^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH 4/5] phy: rockchip: naneng-combphy: Add RK3528 support
  2025-05-08 13:43 [PATCH 0/5] Support RK3528 variant of Rockchip naneng-combphy Yao Zi
                   ` (2 preceding siblings ...)
  2025-05-08 13:52 ` [PATCH 3/5] phy: rockchip: naneng-combphy: Add SoC prefix to register definitions Yao Zi
@ 2025-05-08 13:53 ` Yao Zi
  2025-05-08 17:26   ` Heiko Stuebner
  2025-05-08 13:53 ` [PATCH 5/5] arm64: dts: rockchip: Add naneng-combphy for RK3528 Yao Zi
  4 siblings, 1 reply; 12+ messages in thread
From: Yao Zi @ 2025-05-08 13:53 UTC (permalink / raw)
  To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Yao Zi,
	Frank Wang, Andy Yan, Cristian Ciocaltea, Detlev Casanova,
	Shresth Prasad, Chukun Pan, Jonas Karlman
  Cc: linux-phy, devicetree, linux-arm-kernel, linux-rockchip,
	linux-kernel

Rockchip RK3528 integrates one naneng-combphy that is able to operate in
PCIe and USB3 mode. The control logic is similar to previous variants of
naneng-combphy but the register layout is apperantly different from the
RK3568 one.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 .../rockchip/phy-rockchip-naneng-combphy.c    | 180 +++++++++++++++++-
 1 file changed, 179 insertions(+), 1 deletion(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index 1d1c7723584b..7c92f7ac3c7f 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -20,7 +20,40 @@
 #define REF_CLOCK_25MHz			(25 * HZ_PER_MHZ)
 #define REF_CLOCK_100MHz		(100 * HZ_PER_MHZ)
 
-/* COMBO PHY REG */
+/* RK3528 COMBO PHY REG */
+#define RK3528_PHYREG6				0x18
+#define  RK3528_PHYREG6_PLL_KVCO		GENMASK(12, 10)
+#define   RK3528_PHYREG6_PLL_KVCO_VALUE		0x2
+#define  RK3528_PHYREG6_SSC_DIR			GENMASK(5, 4)
+#define   RK3528_PHYREG6_SSC_UPWARD		0
+#define   RK3528_PHYREG6_SSC_DOWNWARD		1
+#define RK3528_PHYREG40				0x100
+#define  RK3528_PHYREG40_SSC_EN			BIT(20)
+#define  RK3528_PHYREG40_SSC_CNT		GENMASK(10, 0)
+#define   RK3528_PHYREG40_SSC_CNT_VALUE		0x17d
+#define RK3528_PHYREG42				0x108
+#define  RK3528_PHYREG42_CKDRV_CLK_SEL		BIT(29)
+#define   RK3528_PHYREG42_CKDRV_CLK_PLL		0
+#define   RK3528_PHYREG42_CKDRV_CLK_CKRCV	1
+#define  RK3528_PHYREG42_PLL_LPF_R1_ADJ		GENMASK(10, 7)
+#define   RK3528_PHYREG42_PLL_LPF_R1_ADJ_VALUE	0x9
+#define  RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ	GENMASK(6, 4)
+#define   RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ_VALUE 0x7
+#define  RK3528_PHYREG42_PLL_KVCO_ADJ		GENMASK(2, 0)
+#define   RK3528_PHYREG42_PLL_KVCO_ADJ_VALUE	0x0
+#define RK3528_PHYREG80				0x200
+#define  RK3528_PHYREG80_CTLE_EN		BIT(17)
+#define RK3528_PHYREG81				0x204
+#define  RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X	BIT(5)
+#define  RK3528_PHYREG81_SLEW_RATE_CTRL		GENMASK(2, 0)
+#define   RK3528_PHYREG81_SLEW_RATE_CTRL_SLOW	0x7
+#define RK3528_PHYREG83				0x20c
+#define  RK3528_PHYREG83_RX_SQUELCH		GENMASK(2, 0)
+#define   RK3528_PHYREG83_RX_SQUELCH_VALUE	0x6
+#define RK3528_PHYREG86				0x218
+#define  RK3528_PHYREG86_RTERM_DET_CLK_EN	BIT(14)
+
+/* RK3568 COMBO PHY REG */
 #define RK3568_PHYREG6				0x14
 #define RK3568_PHYREG6_PLL_DIV_MASK		GENMASK(7, 6)
 #define RK3568_PHYREG6_PLL_DIV_SHIFT		6
@@ -398,6 +431,147 @@ static int rockchip_combphy_probe(struct platform_device *pdev)
 	return PTR_ERR_OR_ZERO(phy_provider);
 }
 
+static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
+{
+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+	unsigned long rate;
+	u32 val;
+
+	/* Set SSC downward spread spectrum */
+	val = FIELD_PREP(RK3528_PHYREG6_SSC_DIR, RK3528_PHYREG6_SSC_DOWNWARD);
+	rockchip_combphy_updatel(priv, RK3528_PHYREG6_SSC_DIR, val, RK3528_PHYREG6);
+
+	switch (priv->type) {
+	case PHY_TYPE_PCIE:
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
+		break;
+	case PHY_TYPE_USB3:
+		/* Enable adaptive CTLE for USB3.0 Rx */
+		rockchip_combphy_updatel(priv, RK3528_PHYREG80_CTLE_EN, RK3528_PHYREG80_CTLE_EN,
+					 RK3528_PHYREG80);
+
+		/* Set slow slew rate control for PI */
+		val = FIELD_PREP(RK3528_PHYREG81_SLEW_RATE_CTRL,
+				 RK3528_PHYREG81_SLEW_RATE_CTRL_SLOW);
+		rockchip_combphy_updatel(priv, RK3528_PHYREG81_SLEW_RATE_CTRL, val,
+					 RK3528_PHYREG81);
+
+		/* Set CDR phase path with 2x gain */
+		rockchip_combphy_updatel(priv, RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X,
+					 RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X, RK3528_PHYREG81);
+
+		/* Set Rx squelch input filler bandwidth */
+		val = FIELD_PREP(RK3528_PHYREG83_RX_SQUELCH, RK3528_PHYREG83_RX_SQUELCH_VALUE);
+		rockchip_combphy_updatel(priv, RK3528_PHYREG83_RX_SQUELCH, val, RK3528_PHYREG83);
+
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
+		break;
+	default:
+		dev_err(priv->dev, "incompatible PHY type\n");
+		return -EINVAL;
+	}
+
+	rate = clk_get_rate(priv->refclk);
+
+	switch (rate) {
+	case REF_CLOCK_24MHz:
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true);
+		if (priv->type == PHY_TYPE_USB3) {
+			/* Set ssc_cnt[10:0]=00101111101 & 31.5KHz */
+			val = FIELD_PREP(RK3528_PHYREG40_SSC_CNT, RK3528_PHYREG40_SSC_CNT_VALUE);
+			rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_CNT, val,
+						 RK3528_PHYREG40);
+		} else if (priv->type == PHY_TYPE_PCIE) {
+			/* tx_trim[14]=1, Enable the counting clock of the rterm detect */
+			rockchip_combphy_updatel(priv, RK3528_PHYREG86_RTERM_DET_CLK_EN,
+						 RK3528_PHYREG86_RTERM_DET_CLK_EN, RK3528_PHYREG86);
+		}
+		break;
+	case REF_CLOCK_100MHz:
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
+		if (priv->type == PHY_TYPE_PCIE) {
+			/* PLL KVCO tuning fine */
+			val = FIELD_PREP(RK3528_PHYREG6_PLL_KVCO, RK3528_PHYREG6_PLL_KVCO_VALUE);
+			rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val,
+						 RK3528_PHYREG6);
+
+			/* su_trim[6:4]=111, [10:7]=1001, [2:0]=000, swing 650mv */
+			writel(0x570804f0, priv->mmio + RK3528_PHYREG42);
+		}
+		break;
+	default:
+		dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
+		return -EINVAL;
+	}
+
+	if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
+		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
+
+		if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
+			val = FIELD_PREP(RK3528_PHYREG42_CKDRV_CLK_SEL,
+					 RK3528_PHYREG42_CKDRV_CLK_CKRCV);
+			val |= FIELD_PREP(RK3528_PHYREG42_PLL_LPF_R1_ADJ,
+					  RK3528_PHYREG42_PLL_LPF_R1_ADJ_VALUE);
+			val |= FIELD_PREP(RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ,
+					  RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ_VALUE);
+			val |= FIELD_PREP(RK3528_PHYREG42_PLL_KVCO_ADJ,
+					  RK3528_PHYREG42_PLL_KVCO_ADJ_VALUE);
+			rockchip_combphy_updatel(priv,
+						 RK3528_PHYREG42_CKDRV_CLK_SEL		|
+						 RK3528_PHYREG42_PLL_LPF_R1_ADJ		|
+						 RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ	|
+						 RK3528_PHYREG42_PLL_KVCO_ADJ,
+						 val, RK3528_PHYREG42);
+
+			val = FIELD_PREP(RK3528_PHYREG6_PLL_KVCO, RK3528_PHYREG6_PLL_KVCO_VALUE);
+			rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val,
+						 RK3528_PHYREG6);
+		}
+	}
+
+	if (priv->type == PHY_TYPE_PCIE) {
+		if (device_property_read_bool(priv->dev, "rockchip,enable-ssc"))
+			rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_EN,
+						 RK3528_PHYREG40_SSC_EN, RK3528_PHYREG40);
+	}
+
+	return 0;
+}
+
+static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = {
+	/* pipe-phy-grf */
+	.pcie_mode_set		= { 0x0000, 5, 0, 0x00, 0x11 },
+	.usb_mode_set		= { 0x0000, 5, 0, 0x00, 0x04 },
+	.pipe_rxterm_set	= { 0x0000, 12, 12, 0x00, 0x01 },
+	.pipe_txelec_set	= { 0x0004, 1, 1, 0x00, 0x01 },
+	.pipe_txcomp_set	= { 0x0004, 4, 4, 0x00, 0x01 },
+	.pipe_clk_24m		= { 0x0004, 14, 13, 0x00, 0x00 },
+	.pipe_clk_100m		= { 0x0004, 14, 13, 0x00, 0x02 },
+	.pipe_rxterm_sel	= { 0x0008, 8, 8, 0x00, 0x01 },
+	.pipe_txelec_sel	= { 0x0008, 12, 12, 0x00, 0x01 },
+	.pipe_txcomp_sel	= { 0x0008, 15, 15, 0x00, 0x01 },
+	.pipe_clk_ext		= { 0x000c, 9, 8, 0x02, 0x01 },
+	.pipe_phy_status	= { 0x0034, 6, 6, 0x01, 0x00 },
+	.con0_for_pcie		= { 0x0000, 15, 0, 0x00, 0x110 },
+	.con1_for_pcie		= { 0x0004, 15, 0, 0x00, 0x00 },
+	.con2_for_pcie		= { 0x0008, 15, 0, 0x00, 0x101 },
+	.con3_for_pcie		= { 0x000c, 15, 0, 0x00, 0x0200 },
+};
+
+static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {
+	.num_phys	= 1,
+	.phy_ids	= {
+		0xffdc0000,
+	},
+	.grfcfg		= &rk3528_combphy_grfcfgs,
+	.combphy_cfg	= rk3528_combphy_cfg,
+};
+
 static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
 {
 	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
@@ -1213,6 +1387,10 @@ static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
 };
 
 static const struct of_device_id rockchip_combphy_of_match[] = {
+	{
+		.compatible = "rockchip,rk3528-naneng-combphy",
+		.data = &rk3528_combphy_cfgs,
+	},
 	{
 		.compatible = "rockchip,rk3562-naneng-combphy",
 		.data = &rk3562_combphy_cfgs,
-- 
2.49.0



^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [PATCH 5/5] arm64: dts: rockchip: Add naneng-combphy for RK3528
  2025-05-08 13:43 [PATCH 0/5] Support RK3528 variant of Rockchip naneng-combphy Yao Zi
                   ` (3 preceding siblings ...)
  2025-05-08 13:53 ` [PATCH 4/5] phy: rockchip: naneng-combphy: Add RK3528 support Yao Zi
@ 2025-05-08 13:53 ` Yao Zi
  4 siblings, 0 replies; 12+ messages in thread
From: Yao Zi @ 2025-05-08 13:53 UTC (permalink / raw)
  To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Yao Zi,
	Frank Wang, Andy Yan, Cristian Ciocaltea, Detlev Casanova,
	Shresth Prasad, Chukun Pan, Jonas Karlman
  Cc: linux-phy, devicetree, linux-arm-kernel, linux-rockchip,
	linux-kernel

Rockchip RK3528 ships a naneng-combphy that is shared by PCIe and USB
3.0 controllers. Describe it and the pipe-phy grf which it depends on.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 arch/arm64/boot/dts/rockchip/rk3528.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
index 68059c7d7e80..cd6b9ddb3345 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/phy/phy.h>
 #include <dt-bindings/clock/rockchip,rk3528-cru.h>
 #include <dt-bindings/reset/rockchip,rk3528-cru.h>
 
@@ -334,6 +335,11 @@ vpu_grf: syscon@ff340000 {
 			reg = <0x0 0xff340000 0x0 0x8000>;
 		};
 
+		pipe_phy_grf: syscon@ff348000 {
+			compatible = "rockchip,rk3528-pipe-phy-grf", "syscon";
+			reg = <0x0 0xff348000 0x0 0x8000>;
+		};
+
 		vo_grf: syscon@ff360000 {
 			compatible = "rockchip,rk3528-vo-grf", "syscon";
 			reg = <0x0 0xff360000 0x0 0x10000>;
@@ -698,6 +704,23 @@ dmac: dma-controller@ffd60000 {
 			arm,pl330-periph-burst;
 		};
 
+		combphy: phy@ffdc0000 {
+			compatible = "rockchip,rk3528-naneng-combphy";
+			reg = <0x0 0xffdc0000 0x0 0x10000>;
+			#phy-cells = <1>;
+			clocks = <&cru CLK_REF_PCIE_INNER_PHY>, <&cru PCLK_PCIE_PHY>,
+				 <&cru PCLK_PIPE_GRF>;
+			clock-names = "ref", "apb",
+				      "pipe";
+			assigned-clocks = <&cru CLK_REF_PCIE_INNER_PHY>;
+			assigned-clock-rates = <100000000>;
+			resets = <&cru SRST_PCIE_PIPE_PHY>, <&cru SRST_P_PCIE_PHY>;
+			reset-names = "phy", "apb";
+			rockchip,pipe-grf = <&vpu_grf>;
+			rockchip,pipe-phy-grf = <&pipe_phy_grf>;
+			status = "disabled";
+		};
+
 		pinctrl: pinctrl {
 			compatible = "rockchip,rk3528-pinctrl";
 			rockchip,grf = <&ioc_grf>;
-- 
2.49.0



^ permalink raw reply related	[flat|nested] 12+ messages in thread

* Re: [PATCH 2/5] dt-bindings: phy: rockchip: naneng-combphy: Add RK3528 variant
  2025-05-08 13:43 ` [PATCH 2/5] dt-bindings: phy: rockchip: naneng-combphy: Add RK3528 variant Yao Zi
@ 2025-05-08 14:40   ` Conor Dooley
  2025-05-08 17:15   ` Heiko Stuebner
  1 sibling, 0 replies; 12+ messages in thread
From: Conor Dooley @ 2025-05-08 14:40 UTC (permalink / raw)
  To: Yao Zi
  Cc: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Frank Wang,
	Andy Yan, Cristian Ciocaltea, Detlev Casanova, Shresth Prasad,
	Chukun Pan, Jonas Karlman, linux-phy, devicetree,
	linux-arm-kernel, linux-rockchip, linux-kernel

[-- Attachment #1: Type: text/plain, Size: 285 bytes --]

On Thu, May 08, 2025 at 01:43:30PM +0000, Yao Zi wrote:
> Rockchip RK3528 ships one naneng-combphy which operates in either PCIe
> or USB 3 mode. Document its compatible string.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

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^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH 1/5] dt-bindings: soc: rockchip: Add RK3528 pipe-phy GRF syscon
  2025-05-08 13:43 ` [PATCH 1/5] dt-bindings: soc: rockchip: Add RK3528 pipe-phy GRF syscon Yao Zi
@ 2025-05-08 14:40   ` Conor Dooley
  0 siblings, 0 replies; 12+ messages in thread
From: Conor Dooley @ 2025-05-08 14:40 UTC (permalink / raw)
  To: Yao Zi
  Cc: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Frank Wang,
	Andy Yan, Cristian Ciocaltea, Detlev Casanova, Shresth Prasad,
	Chukun Pan, Jonas Karlman, linux-phy, devicetree,
	linux-arm-kernel, linux-rockchip, linux-kernel

[-- Attachment #1: Type: text/plain, Size: 1050 bytes --]

On Thu, May 08, 2025 at 01:43:29PM +0000, Yao Zi wrote:
> Add compatible string for pipe-phy GRF found on RK3528 SoC, which
> controls misc settings for the integrated naneng-combphy.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

> ---
>  Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> index 2f61c1b95fea..7e9321999435 100644
> --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> @@ -16,6 +16,7 @@ properties:
>            - enum:
>                - rockchip,rk3288-sgrf
>                - rockchip,rk3528-ioc-grf
> +              - rockchip,rk3528-pipe-phy-grf
>                - rockchip,rk3528-vo-grf
>                - rockchip,rk3528-vpu-grf
>                - rockchip,rk3566-pipe-grf
> -- 
> 2.49.0
> 

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^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH 2/5] dt-bindings: phy: rockchip: naneng-combphy: Add RK3528 variant
  2025-05-08 13:43 ` [PATCH 2/5] dt-bindings: phy: rockchip: naneng-combphy: Add RK3528 variant Yao Zi
  2025-05-08 14:40   ` Conor Dooley
@ 2025-05-08 17:15   ` Heiko Stuebner
  1 sibling, 0 replies; 12+ messages in thread
From: Heiko Stuebner @ 2025-05-08 17:15 UTC (permalink / raw)
  To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley, Yao Zi, Frank Wang, Andy Yan,
	Cristian Ciocaltea, Detlev Casanova, Shresth Prasad, Chukun Pan,
	Jonas Karlman, Yao Zi
  Cc: linux-phy, devicetree, linux-arm-kernel, linux-rockchip,
	linux-kernel

Am Donnerstag, 8. Mai 2025, 15:43:30 Mitteleuropäische Sommerzeit schrieb Yao Zi:
> Rockchip RK3528 ships one naneng-combphy which operates in either PCIe
> or USB 3 mode. Document its compatible string.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

> ---
>  .../devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
> index 888e6b2aac5a..bd064754e537 100644
> --- a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
> +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
> @@ -12,6 +12,7 @@ maintainers:
>  properties:
>    compatible:
>      enum:
> +      - rockchip,rk3528-naneng-combphy
>        - rockchip,rk3562-naneng-combphy
>        - rockchip,rk3568-naneng-combphy
>        - rockchip,rk3576-naneng-combphy
> @@ -102,7 +103,9 @@ allOf:
>        properties:
>          compatible:
>            contains:
> -            const: rockchip,rk3588-naneng-combphy
> +            enum:
> +             - rockchip,rk3528-naneng-combphy
> +             - rockchip,rk3588-naneng-combphy
>      then:
>        properties:
>          resets:
> 






^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH 3/5] phy: rockchip: naneng-combphy: Add SoC prefix to register definitions
  2025-05-08 13:52 ` [PATCH 3/5] phy: rockchip: naneng-combphy: Add SoC prefix to register definitions Yao Zi
@ 2025-05-08 17:22   ` Heiko Stuebner
  0 siblings, 0 replies; 12+ messages in thread
From: Heiko Stuebner @ 2025-05-08 17:22 UTC (permalink / raw)
  To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley, Yao Zi, Frank Wang, Andy Yan,
	Cristian Ciocaltea, Detlev Casanova, Shresth Prasad, Chukun Pan,
	Jonas Karlman, Yao Zi
  Cc: linux-phy, devicetree, linux-arm-kernel, linux-rockchip,
	linux-kernel

Am Donnerstag, 8. Mai 2025, 15:52:42 Mitteleuropäische Sommerzeit schrieb Yao Zi:
> All supported variants of naneng-combphy follow a register layout
> similar to the RK3568 variant with some exceptions of SoC-specific
> registers.
> 
> Add RK3568 prefix for the common set of registers and the corresponding
> SoC prefix for SoC-specific registers, making usage of definitions clear
> and preparing for future COMBPHY variants with a different register
> layout.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  .../rockchip/phy-rockchip-naneng-combphy.c    | 560 +++++++++---------
>  1 file changed, 288 insertions(+), 272 deletions(-)
> 
> diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> index ce91fb1d5167..1d1c7723584b 100644
> --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> @@ -21,78 +21,80 @@
>  #define REF_CLOCK_100MHz		(100 * HZ_PER_MHZ)
>  
>  /* COMBO PHY REG */
> -#define PHYREG6				0x14
> -#define PHYREG6_PLL_DIV_MASK		GENMASK(7, 6)
> -#define PHYREG6_PLL_DIV_SHIFT		6
> -#define PHYREG6_PLL_DIV_2		1
> -
> -#define PHYREG7				0x18
> -#define PHYREG7_TX_RTERM_MASK		GENMASK(7, 4)
> -#define PHYREG7_TX_RTERM_SHIFT		4
> -#define PHYREG7_TX_RTERM_50OHM		8
> -#define PHYREG7_RX_RTERM_MASK		GENMASK(3, 0)
> -#define PHYREG7_RX_RTERM_SHIFT		0
> -#define PHYREG7_RX_RTERM_44OHM		15
> -
> -#define PHYREG8				0x1C
> -#define PHYREG8_SSC_EN			BIT(4)
> -
> -#define PHYREG10			0x24
> -#define PHYREG10_SSC_PCM_MASK		GENMASK(3, 0)
> -#define PHYREG10_SSC_PCM_3500PPM	7
> -
> -#define PHYREG11			0x28
> -#define PHYREG11_SU_TRIM_0_7		0xF0
> -
> -#define PHYREG12			0x2C
> -#define PHYREG12_PLL_LPF_ADJ_VALUE	4
> -
> -#define PHYREG13			0x30
> -#define PHYREG13_RESISTER_MASK		GENMASK(5, 4)
> -#define PHYREG13_RESISTER_SHIFT		0x4
> -#define PHYREG13_RESISTER_HIGH_Z	3
> -#define PHYREG13_CKRCV_AMP0		BIT(7)
> -
> -#define PHYREG14			0x34
> -#define PHYREG14_CKRCV_AMP1		BIT(0)
> -
> -#define PHYREG15			0x38
> -#define PHYREG15_CTLE_EN		BIT(0)
> -#define PHYREG15_SSC_CNT_MASK		GENMASK(7, 6)
> -#define PHYREG15_SSC_CNT_SHIFT		6
> -#define PHYREG15_SSC_CNT_VALUE		1
> -
> -#define PHYREG16			0x3C
> -#define PHYREG16_SSC_CNT_VALUE		0x5f
> -
> -#define PHYREG17			0x40
> -
> -#define PHYREG18			0x44
> -#define PHYREG18_PLL_LOOP		0x32
> -
> -#define PHYREG21			0x50
> -#define PHYREG21_RX_SQUELCH_VAL		0x0D
> -
> -#define PHYREG27			0x6C
> -#define PHYREG27_RX_TRIM_RK3588		0x4C
> -
> -#define PHYREG30			0x74
> -
> -#define PHYREG32			0x7C
> -#define PHYREG32_SSC_MASK		GENMASK(7, 4)
> -#define PHYREG32_SSC_DIR_MASK		GENMASK(5, 4)
> -#define PHYREG32_SSC_DIR_SHIFT		4
> -#define PHYREG32_SSC_UPWARD		0
> -#define PHYREG32_SSC_DOWNWARD		1
> -#define PHYREG32_SSC_OFFSET_MASK	GENMASK(7, 6)
> -#define PHYREG32_SSC_OFFSET_SHIFT	6
> -#define PHYREG32_SSC_OFFSET_500PPM	1
> -
> -#define PHYREG33			0x80
> -#define PHYREG33_PLL_KVCO_MASK		GENMASK(4, 2)
> -#define PHYREG33_PLL_KVCO_SHIFT		2
> -#define PHYREG33_PLL_KVCO_VALUE		2
> -#define PHYREG33_PLL_KVCO_VALUE_RK3576	4
> +#define RK3568_PHYREG6				0x14
> +#define RK3568_PHYREG6_PLL_DIV_MASK		GENMASK(7, 6)
> +#define RK3568_PHYREG6_PLL_DIV_SHIFT		6
> +#define RK3568_PHYREG6_PLL_DIV_2		1
> +
> +#define RK3568_PHYREG7				0x18
> +#define RK3568_PHYREG7_TX_RTERM_MASK		GENMASK(7, 4)
> +#define RK3568_PHYREG7_TX_RTERM_SHIFT		4
> +#define RK3568_PHYREG7_TX_RTERM_50OHM		8
> +#define RK3568_PHYREG7_RX_RTERM_MASK		GENMASK(3, 0)
> +#define RK3568_PHYREG7_RX_RTERM_SHIFT		0
> +#define RK3568_PHYREG7_RX_RTERM_44OHM		15
> +
> +#define RK3568_PHYREG8				0x1C
> +#define RK3568_PHYREG8_SSC_EN			BIT(4)
> +
> +#define RK3568_PHYREG11				0x28
> +#define RK3568_PHYREG11_SU_TRIM_0_7		0xF0
> +
> +#define RK3568_PHYREG12				0x2C
> +#define RK3568_PHYREG12_PLL_LPF_ADJ_VALUE	4
> +
> +#define RK3568_PHYREG13				0x30
> +#define RK3568_PHYREG13_RESISTER_MASK		GENMASK(5, 4)
> +#define RK3568_PHYREG13_RESISTER_SHIFT		0x4
> +#define RK3568_PHYREG13_RESISTER_HIGH_Z		3
> +#define RK3568_PHYREG13_CKRCV_AMP0		BIT(7)
> +
> +#define RK3568_PHYREG14				0x34
> +#define RK3568_PHYREG14_CKRCV_AMP1		BIT(0)
> +
> +#define RK3568_PHYREG15				0x38
> +#define RK3568_PHYREG15_CTLE_EN			BIT(0)
> +#define RK3568_PHYREG15_SSC_CNT_MASK		GENMASK(7, 6)
> +#define RK3568_PHYREG15_SSC_CNT_SHIFT		6
> +#define RK3568_PHYREG15_SSC_CNT_VALUE		1
> +
> +#define RK3568_PHYREG16				0x3C
> +#define RK3568_PHYREG16_SSC_CNT_VALUE		0x5f
> +
> +#define RK3568_PHYREG18				0x44
> +#define RK3568_PHYREG18_PLL_LOOP		0x32
> +
> +#define RK3568_PHYREG32				0x7C
> +#define RK3568_PHYREG32_SSC_MASK		GENMASK(7, 4)
> +#define RK3568_PHYREG32_SSC_DIR_MASK		GENMASK(5, 4)
> +#define RK3568_PHYREG32_SSC_DIR_SHIFT		4
> +#define RK3568_PHYREG32_SSC_UPWARD		0
> +#define RK3568_PHYREG32_SSC_DOWNWARD		1
> +#define RK3568_PHYREG32_SSC_OFFSET_MASK	GENMASK(7, 6)
> +#define RK3568_PHYREG32_SSC_OFFSET_SHIFT	6
> +#define RK3568_PHYREG32_SSC_OFFSET_500PPM	1
> +
> +#define RK3568_PHYREG33				0x80
> +#define RK3568_PHYREG33_PLL_KVCO_MASK		GENMASK(4, 2)
> +#define RK3568_PHYREG33_PLL_KVCO_SHIFT		2
> +#define RK3568_PHYREG33_PLL_KVCO_VALUE		2
> +#define RK3576_PHYREG33_PLL_KVCO_VALUE		4
> +
> +/* RK3588 COMBO PHY registers */
> +#define RK3588_PHYREG27				0x6C
> +#define RK3588_PHYREG27_RX_TRIM			0x4C
> +
> +/* RK3576 COMBO PHY registers */
> +#define RK3576_PHYREG10				0x24
> +#define RK3576_PHYREG10_SSC_PCM_MASK		GENMASK(3, 0)
> +#define RK3576_PHYREG10_SSC_PCM_3500PPM		7
> +
> +#define RK3576_PHYREG17				0x40
> +
> +#define RK3576_PHYREG21				0x50
> +#define RK3576_PHYREG21_RX_SQUELCH_VAL		0x0D
> +
> +#define RK3576_PHYREG30				0x74
>  
>  struct rockchip_combphy_priv;
>  
> @@ -405,9 +407,8 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
>  	switch (priv->type) {
>  	case PHY_TYPE_PCIE:
>  		/* Set SSC downward spread spectrum */
> -		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
> -					 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
> -					 PHYREG32);
> +		val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
> +		rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
>  
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
> @@ -416,29 +417,30 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
>  		break;
>  	case PHY_TYPE_USB3:
>  		/* Set SSC downward spread spectrum */
> -		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
> -					 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
> -					 PHYREG32);
> +		val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
> +		rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
> +					 RK3568_PHYREG32);
>  
>  		/* Enable adaptive CTLE for USB3.0 Rx */
> -		rockchip_combphy_updatel(priv, PHYREG15_CTLE_EN,
> -					 PHYREG15_CTLE_EN, PHYREG15);
> +		rockchip_combphy_updatel(priv, RK3568_PHYREG15_CTLE_EN,
> +					 RK3568_PHYREG15_CTLE_EN, RK3568_PHYREG15);
>  
>  		/* Set PLL KVCO fine tuning signals */
> -		rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, BIT(3), PHYREG33);
> +		rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
> +					 BIT(3), RK3568_PHYREG33);
>  
>  		/* Set PLL LPF R1 to su_trim[10:7]=1001 */
> -		writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
> +		writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
>  
>  		/* Set PLL input clock divider 1/2 */
> -		val = FIELD_PREP(PHYREG6_PLL_DIV_MASK, PHYREG6_PLL_DIV_2);
> -		rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, val, PHYREG6);
> +		val = FIELD_PREP(RK3568_PHYREG6_PLL_DIV_MASK, RK3568_PHYREG6_PLL_DIV_2);
> +		rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, val, RK3568_PHYREG6);
>  
>  		/* Set PLL loop divider */
> -		writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
> +		writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
>  
>  		/* Set PLL KVCO to min and set PLL charge pump current to max */
> -		writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
> +		writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
>  
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
> @@ -456,11 +458,12 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
>  	case REF_CLOCK_24MHz:
>  		if (priv->type == PHY_TYPE_USB3) {
>  			/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
> -			val = FIELD_PREP(PHYREG15_SSC_CNT_MASK, PHYREG15_SSC_CNT_VALUE);
> -			rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
> -						 val, PHYREG15);
> +			val = FIELD_PREP(RK3568_PHYREG15_SSC_CNT_MASK,
> +					 RK3568_PHYREG15_SSC_CNT_VALUE);
> +			rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK,
> +						 val, RK3568_PHYREG15);
>  
> -			writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
> +			writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
>  		}
>  		break;
>  	case REF_CLOCK_25MHz:
> @@ -470,19 +473,20 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
>  		if (priv->type == PHY_TYPE_PCIE) {
>  			/* PLL KVCO tuning fine */
> -			val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE);
> -			rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
> -						 val, PHYREG33);
> +			val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
> +					 RK3568_PHYREG33_PLL_KVCO_VALUE);
> +			rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
> +						 val, RK3568_PHYREG33);
>  
>  			/* Enable controlling random jitter, aka RMJ */
> -			writel(0x4, priv->mmio + PHYREG12);
> +			writel(0x4, priv->mmio + RK3568_PHYREG12);
>  
> -			val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT;
> -			rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
> -						 val, PHYREG6);
> +			val = RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT;
> +			rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK,
> +						 val, RK3568_PHYREG6);
>  
> -			writel(0x32, priv->mmio + PHYREG18);
> -			writel(0xf0, priv->mmio + PHYREG11);
> +			writel(0x32, priv->mmio + RK3568_PHYREG18);
> +			writel(0xf0, priv->mmio + RK3568_PHYREG11);
>  		}
>  		break;
>  	default:
> @@ -493,20 +497,21 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
>  	if (priv->ext_refclk) {
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
>  		if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
> -			val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
> -			val |= PHYREG13_CKRCV_AMP0;
> -			rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
> -
> -			val = readl(priv->mmio + PHYREG14);
> -			val |= PHYREG14_CKRCV_AMP1;
> -			writel(val, priv->mmio + PHYREG14);
> +			val = RK3568_PHYREG13_RESISTER_HIGH_Z << RK3568_PHYREG13_RESISTER_SHIFT;
> +			val |= RK3568_PHYREG13_CKRCV_AMP0;
> +			rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val,
> +						 RK3568_PHYREG13);
> +
> +			val = readl(priv->mmio + RK3568_PHYREG14);
> +			val |= RK3568_PHYREG14_CKRCV_AMP1;
> +			writel(val, priv->mmio + RK3568_PHYREG14);
>  		}
>  	}
>  
>  	if (priv->enable_ssc) {
> -		val = readl(priv->mmio + PHYREG8);
> -		val |= PHYREG8_SSC_EN;
> -		writel(val, priv->mmio + PHYREG8);
> +		val = readl(priv->mmio + RK3568_PHYREG8);
> +		val |= RK3568_PHYREG8_SSC_EN;
> +		writel(val, priv->mmio + RK3568_PHYREG8);
>  	}
>  
>  	return 0;
> @@ -553,9 +558,9 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
>  	switch (priv->type) {
>  	case PHY_TYPE_PCIE:
>  		/* Set SSC downward spread spectrum. */
> -		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
> -					 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
> -					 PHYREG32);
> +		val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
> +
> +		rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
>  
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
> @@ -565,30 +570,28 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
>  
>  	case PHY_TYPE_USB3:
>  		/* Set SSC downward spread spectrum. */
> -		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
> -					 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
> -					 PHYREG32);
> +		val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT,
> +		rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
>  
>  		/* Enable adaptive CTLE for USB3.0 Rx. */
> -		val = readl(priv->mmio + PHYREG15);
> -		val |= PHYREG15_CTLE_EN;
> -		writel(val, priv->mmio + PHYREG15);
> +		val = readl(priv->mmio + RK3568_PHYREG15);
> +		val |= RK3568_PHYREG15_CTLE_EN;
> +		writel(val, priv->mmio + RK3568_PHYREG15);
>  
>  		/* Set PLL KVCO fine tuning signals. */
> -		rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
> -					 PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
> -					 PHYREG33);
> +		val = RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT;
> +		rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, val, RK3568_PHYREG33);
>  
>  		/* Enable controlling random jitter. */
> -		writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
> +		writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
>  
>  		/* Set PLL input clock divider 1/2. */
> -		rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
> -					 PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
> -					 PHYREG6);
> +		rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK,
> +					 RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT,
> +					 RK3568_PHYREG6);
>  
> -		writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
> -		writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
> +		writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
> +		writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
>  
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
> @@ -598,16 +601,16 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
>  
>  	case PHY_TYPE_SATA:
>  		/* Enable adaptive CTLE for SATA Rx. */
> -		val = readl(priv->mmio + PHYREG15);
> -		val |= PHYREG15_CTLE_EN;
> -		writel(val, priv->mmio + PHYREG15);
> +		val = readl(priv->mmio + RK3568_PHYREG15);
> +		val |= RK3568_PHYREG15_CTLE_EN;
> +		writel(val, priv->mmio + RK3568_PHYREG15);
>  		/*
>  		 * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
>  		 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
>  		 */
> -		val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
> -		val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
> -		writel(val, priv->mmio + PHYREG7);
> +		val = RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT;
> +		val |= RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT;
> +		writel(val, priv->mmio + RK3568_PHYREG7);
>  
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
> @@ -642,11 +645,11 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
>  	case REF_CLOCK_24MHz:
>  		if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
>  			/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
> -			val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
> -			rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
> -						 val, PHYREG15);
> +			val = RK3568_PHYREG15_SSC_CNT_VALUE << RK3568_PHYREG15_SSC_CNT_SHIFT;
> +			rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK,
> +						 val, RK3568_PHYREG15);
>  
> -			writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
> +			writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
>  		}
>  		break;
>  
> @@ -658,24 +661,26 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
>  		if (priv->type == PHY_TYPE_PCIE) {
>  			/* PLL KVCO  fine tuning. */
> -			val = PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT;
> -			rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
> -						 val, PHYREG33);
> +			val = RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT;
> +			rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
> +						 val, RK3568_PHYREG33);
>  
>  			/* Enable controlling random jitter. */
> -			writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
> +			writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
>  
> -			val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT;
> -			rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
> -						 val, PHYREG6);
> +			val = RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT;
> +			rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK,
> +						 val, RK3568_PHYREG6);
>  
> -			writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
> -			writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
> +			writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
> +			writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
>  		} else if (priv->type == PHY_TYPE_SATA) {
>  			/* downward spread spectrum +500ppm */
> -			val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
> -			val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
> -			rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
> +			val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
> +			val |= RK3568_PHYREG32_SSC_OFFSET_500PPM <<
> +			       RK3568_PHYREG32_SSC_OFFSET_SHIFT;
> +			rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
> +						 RK3568_PHYREG32);
>  		}
>  		break;
>  
> @@ -687,20 +692,21 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
>  	if (priv->ext_refclk) {
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
>  		if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
> -			val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
> -			val |= PHYREG13_CKRCV_AMP0;
> -			rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
> -
> -			val = readl(priv->mmio + PHYREG14);
> -			val |= PHYREG14_CKRCV_AMP1;
> -			writel(val, priv->mmio + PHYREG14);
> +			val = RK3568_PHYREG13_RESISTER_HIGH_Z << RK3568_PHYREG13_RESISTER_SHIFT;
> +			val |= RK3568_PHYREG13_CKRCV_AMP0;
> +			rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val,
> +						 RK3568_PHYREG13);
> +
> +			val = readl(priv->mmio + RK3568_PHYREG14);
> +			val |= RK3568_PHYREG14_CKRCV_AMP1;
> +			writel(val, priv->mmio + RK3568_PHYREG14);
>  		}
>  	}
>  
>  	if (priv->enable_ssc) {
> -		val = readl(priv->mmio + PHYREG8);
> -		val |= PHYREG8_SSC_EN;
> -		writel(val, priv->mmio + PHYREG8);
> +		val = readl(priv->mmio + RK3568_PHYREG8);
> +		val |= RK3568_PHYREG8_SSC_EN;
> +		writel(val, priv->mmio + RK3568_PHYREG8);
>  	}
>  
>  	return 0;
> @@ -759,8 +765,8 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
>  	switch (priv->type) {
>  	case PHY_TYPE_PCIE:
>  		/* Set SSC downward spread spectrum */
> -		val = FIELD_PREP(PHYREG32_SSC_MASK, PHYREG32_SSC_DOWNWARD);
> -		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
> +		val = FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWARD);
> +		rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
>  
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
> @@ -770,32 +776,33 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
>  
>  	case PHY_TYPE_USB3:
>  		/* Set SSC downward spread spectrum */
> -		val = FIELD_PREP(PHYREG32_SSC_MASK, PHYREG32_SSC_DOWNWARD);
> -		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
> +		val = FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWARD);
> +		rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
>  
>  		/* Enable adaptive CTLE for USB3.0 Rx */
> -		val = readl(priv->mmio + PHYREG15);
> -		val |= PHYREG15_CTLE_EN;
> -		writel(val, priv->mmio + PHYREG15);
> +		val = readl(priv->mmio + RK3568_PHYREG15);
> +		val |= RK3568_PHYREG15_CTLE_EN;
> +		writel(val, priv->mmio + RK3568_PHYREG15);
>  
>  		/* Set PLL KVCO fine tuning signals */
> -		rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, BIT(3), PHYREG33);
> +		rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, BIT(3),
> +					 RK3568_PHYREG33);
>  
>  		/* Set PLL LPF R1 to su_trim[10:7]=1001 */
> -		writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
> +		writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
>  
>  		/* Set PLL input clock divider 1/2 */
> -		val = FIELD_PREP(PHYREG6_PLL_DIV_MASK, PHYREG6_PLL_DIV_2);
> -		rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, val, PHYREG6);
> +		val = FIELD_PREP(RK3568_PHYREG6_PLL_DIV_MASK, RK3568_PHYREG6_PLL_DIV_2);
> +		rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, val, RK3568_PHYREG6);
>  
>  		/* Set PLL loop divider */
> -		writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
> +		writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
>  
>  		/* Set PLL KVCO to min and set PLL charge pump current to max */
> -		writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
> +		writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
>  
>  		/* Set Rx squelch input filler bandwidth */
> -		writel(PHYREG21_RX_SQUELCH_VAL, priv->mmio + PHYREG21);
> +		writel(RK3576_PHYREG21_RX_SQUELCH_VAL, priv->mmio + RK3576_PHYREG21);
>  
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
> @@ -804,14 +811,14 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
>  
>  	case PHY_TYPE_SATA:
>  		/* Enable adaptive CTLE for SATA Rx */
> -		val = readl(priv->mmio + PHYREG15);
> -		val |= PHYREG15_CTLE_EN;
> -		writel(val, priv->mmio + PHYREG15);
> +		val = readl(priv->mmio + RK3568_PHYREG15);
> +		val |= RK3568_PHYREG15_CTLE_EN;
> +		writel(val, priv->mmio + RK3568_PHYREG15);
>  
>  		/* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */
> -		val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
> -		val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
> -		writel(val, priv->mmio + PHYREG7);
> +		val = RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT;
> +		val |= RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT;
> +		writel(val, priv->mmio + RK3568_PHYREG7);
>  
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
> @@ -833,19 +840,21 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true);
>  		if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
>  			/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
> -			val = FIELD_PREP(PHYREG15_SSC_CNT_MASK, PHYREG15_SSC_CNT_VALUE);
> -			rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
> -						 val, PHYREG15);
> +			val = FIELD_PREP(RK3568_PHYREG15_SSC_CNT_MASK,
> +					 RK3568_PHYREG15_SSC_CNT_VALUE);
> +			rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK,
> +						 val, RK3568_PHYREG15);
>  
> -			writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
> +			writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
>  		} else if (priv->type == PHY_TYPE_PCIE) {
>  			/* PLL KVCO tuning fine */
> -			val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576);
> -			rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
> -						 val, PHYREG33);
> +			val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
> +					 RK3576_PHYREG33_PLL_KVCO_VALUE);
> +			rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
> +						 val, RK3568_PHYREG33);
>  
>  			/* Set up rx_pck invert and rx msb to disable */
> -			writel(0x00, priv->mmio + PHYREG27);
> +			writel(0x00, priv->mmio + RK3588_PHYREG27);
>  
>  			/*
>  			 * Set up SU adjust signal:
> @@ -853,11 +862,11 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
>  			 * su_trim[15:8],  PLL LPF R1 adujst bits[9:7]=3'b011
>  			 * su_trim[31:24], CKDRV adjust
>  			 */
> -			writel(0x90, priv->mmio + PHYREG11);
> -			writel(0x02, priv->mmio + PHYREG12);
> -			writel(0x57, priv->mmio + PHYREG14);
> +			writel(0x90, priv->mmio + RK3568_PHYREG11);
> +			writel(0x02, priv->mmio + RK3568_PHYREG12);
> +			writel(0x57, priv->mmio + RK3568_PHYREG14);
>  
> -			writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
> +			writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
>  		}
>  		break;
>  
> @@ -869,15 +878,16 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
>  		if (priv->type == PHY_TYPE_PCIE) {
>  			/* gate_tx_pck_sel length select work for L1SS */
> -			writel(0xc0, priv->mmio + PHYREG30);
> +			writel(0xc0, priv->mmio + RK3576_PHYREG30);
>  
>  			/* PLL KVCO tuning fine */
> -			val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576);
> -			rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
> -						 val, PHYREG33);
> +			val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
> +					 RK3576_PHYREG33_PLL_KVCO_VALUE);
> +			rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
> +						 val, RK3568_PHYREG33);
>  
>  			/* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
> -			writel(0x4c, priv->mmio + PHYREG27);
> +			writel(0x4c, priv->mmio + RK3588_PHYREG27);
>  
>  			/*
>  			 * Set up SU adjust signal:
> @@ -887,20 +897,23 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
>  			 * su_trim[23:16], CKRCV adjust
>  			 * su_trim[31:24], CKDRV adjust
>  			 */
> -			writel(0x90, priv->mmio + PHYREG11);
> -			writel(0x43, priv->mmio + PHYREG12);
> -			writel(0x88, priv->mmio + PHYREG13);
> -			writel(0x56, priv->mmio + PHYREG14);
> +			writel(0x90, priv->mmio + RK3568_PHYREG11);
> +			writel(0x43, priv->mmio + RK3568_PHYREG12);
> +			writel(0x88, priv->mmio + RK3568_PHYREG13);
> +			writel(0x56, priv->mmio + RK3568_PHYREG14);
>  		} else if (priv->type == PHY_TYPE_SATA) {
>  			/* downward spread spectrum +500ppm */
> -			val = FIELD_PREP(PHYREG32_SSC_DIR_MASK, PHYREG32_SSC_DOWNWARD);
> -			val |= FIELD_PREP(PHYREG32_SSC_OFFSET_MASK, PHYREG32_SSC_OFFSET_500PPM);
> -			rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
> +			val = FIELD_PREP(RK3568_PHYREG32_SSC_DIR_MASK,
> +					 RK3568_PHYREG32_SSC_DOWNWARD);
> +			val |= FIELD_PREP(RK3568_PHYREG32_SSC_OFFSET_MASK,
> +					  RK3568_PHYREG32_SSC_OFFSET_500PPM);
> +			rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
> +						 RK3568_PHYREG32);
>  
>  			/* ssc ppm adjust to 3500ppm */
> -			rockchip_combphy_updatel(priv, PHYREG10_SSC_PCM_MASK,
> -						 PHYREG10_SSC_PCM_3500PPM,
> -						 PHYREG10);
> +			rockchip_combphy_updatel(priv, RK3576_PHYREG10_SSC_PCM_MASK,
> +						 RK3576_PHYREG10_SSC_PCM_3500PPM,
> +						 RK3576_PHYREG10);
>  		}
>  		break;
>  
> @@ -912,12 +925,13 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
>  	if (priv->ext_refclk) {
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
>  		if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
> -			val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576);
> -			rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
> -						 val, PHYREG33);
> +			val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
> +					 RK3576_PHYREG33_PLL_KVCO_VALUE);
> +			rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
> +						 val, RK3568_PHYREG33);
>  
>  			/* Set up rx_trim: PLL LPF C1 85pf R1 2.5kohm */
> -			writel(0x0c, priv->mmio + PHYREG27);
> +			writel(0x0c, priv->mmio + RK3588_PHYREG27);
>  
>  			/*
>  			 * Set up SU adjust signal:
> @@ -927,25 +941,25 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
>  			 * su_trim[23:16], CKRCV adjust
>  			 * su_trim[31:24], CKDRV adjust
>  			 */
> -			writel(0x90, priv->mmio + PHYREG11);
> -			writel(0x43, priv->mmio + PHYREG12);
> -			writel(0x88, priv->mmio + PHYREG13);
> -			writel(0x56, priv->mmio + PHYREG14);
> +			writel(0x90, priv->mmio + RK3568_PHYREG11);
> +			writel(0x43, priv->mmio + RK3568_PHYREG12);
> +			writel(0x88, priv->mmio + RK3568_PHYREG13);
> +			writel(0x56, priv->mmio + RK3568_PHYREG14);
>  		}
>  	}
>  
>  	if (priv->enable_ssc) {
> -		val = readl(priv->mmio + PHYREG8);
> -		val |= PHYREG8_SSC_EN;
> -		writel(val, priv->mmio + PHYREG8);
> +		val = readl(priv->mmio + RK3568_PHYREG8);
> +		val |= RK3568_PHYREG8_SSC_EN;
> +		writel(val, priv->mmio + RK3568_PHYREG8);
>  
>  		if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_24MHz) {
>  			/* Set PLL loop divider */
> -			writel(0x00, priv->mmio + PHYREG17);
> -			writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
> +			writel(0x00, priv->mmio + RK3576_PHYREG17);
> +			writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
>  
>  			/* Set up rx_pck invert and rx msb to disable */
> -			writel(0x00, priv->mmio + PHYREG27);
> +			writel(0x00, priv->mmio + RK3588_PHYREG27);
>  
>  			/*
>  			 * Set up SU adjust signal:
> @@ -954,16 +968,17 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
>  			 * su_trim[23:16], CKRCV adjust
>  			 * su_trim[31:24], CKDRV adjust
>  			 */
> -			writel(0x90, priv->mmio + PHYREG11);
> -			writel(0x02, priv->mmio + PHYREG12);
> -			writel(0x08, priv->mmio + PHYREG13);
> -			writel(0x57, priv->mmio + PHYREG14);
> -			writel(0x40, priv->mmio + PHYREG15);
> +			writel(0x90, priv->mmio + RK3568_PHYREG11);
> +			writel(0x02, priv->mmio + RK3568_PHYREG12);
> +			writel(0x08, priv->mmio + RK3568_PHYREG13);
> +			writel(0x57, priv->mmio + RK3568_PHYREG14);
> +			writel(0x40, priv->mmio + RK3568_PHYREG15);
>  
> -			writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
> +			writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
>  
> -			val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576);
> -			writel(val, priv->mmio + PHYREG33);
> +			val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
> +					 RK3576_PHYREG33_PLL_KVCO_VALUE);
> +			writel(val, priv->mmio + RK3568_PHYREG33);
>  		}
>  	}
>  
> @@ -1033,30 +1048,28 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
>  		break;
>  	case PHY_TYPE_USB3:
>  		/* Set SSC downward spread spectrum */
> -		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
> -					 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
> -					 PHYREG32);
> +		val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
> +		rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
>  
>  		/* Enable adaptive CTLE for USB3.0 Rx. */
> -		val = readl(priv->mmio + PHYREG15);
> -		val |= PHYREG15_CTLE_EN;
> -		writel(val, priv->mmio + PHYREG15);
> +		val = readl(priv->mmio + RK3568_PHYREG15);
> +		val |= RK3568_PHYREG15_CTLE_EN;
> +		writel(val, priv->mmio + RK3568_PHYREG15);
>  
>  		/* Set PLL KVCO fine tuning signals. */
> -		rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
> -					 PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
> -					 PHYREG33);
> +		val = RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT,
> +		rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, val, RK3568_PHYREG33);
>  
>  		/* Enable controlling random jitter. */
> -		writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
> +		writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
>  
>  		/* Set PLL input clock divider 1/2. */
> -		rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
> -					 PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
> -					 PHYREG6);
> +		rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK,
> +					 RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT,
> +					 RK3568_PHYREG6);
>  
> -		writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
> -		writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
> +		writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
> +		writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
>  
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
> @@ -1064,16 +1077,16 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
>  		break;
>  	case PHY_TYPE_SATA:
>  		/* Enable adaptive CTLE for SATA Rx. */
> -		val = readl(priv->mmio + PHYREG15);
> -		val |= PHYREG15_CTLE_EN;
> -		writel(val, priv->mmio + PHYREG15);
> +		val = readl(priv->mmio + RK3568_PHYREG15);
> +		val |= RK3568_PHYREG15_CTLE_EN;
> +		writel(val, priv->mmio + RK3568_PHYREG15);
>  		/*
>  		 * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
>  		 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
>  		 */
> -		val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
> -		val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
> -		writel(val, priv->mmio + PHYREG7);
> +		val = RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT;
> +		val |= RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT;
> +		writel(val, priv->mmio + RK3568_PHYREG7);
>  
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
> @@ -1095,11 +1108,11 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
>  	case REF_CLOCK_24MHz:
>  		if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
>  			/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
> -			val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
> -			rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
> -						 val, PHYREG15);
> +			val = RK3568_PHYREG15_SSC_CNT_VALUE << RK3568_PHYREG15_SSC_CNT_SHIFT;
> +			rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK,
> +						 val, RK3568_PHYREG15);
>  
> -			writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
> +			writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
>  		}
>  		break;
>  
> @@ -1110,23 +1123,25 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
>  		if (priv->type == PHY_TYPE_PCIE) {
>  			/* PLL KVCO fine tuning. */
> -			val = 4 << PHYREG33_PLL_KVCO_SHIFT;
> -			rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
> -						 val, PHYREG33);
> +			val = 4 << RK3568_PHYREG33_PLL_KVCO_SHIFT;
> +			rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
> +						 val, RK3568_PHYREG33);
>  
>  			/* Enable controlling random jitter. */
> -			writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
> +			writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
>  
>  			/* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
> -			writel(PHYREG27_RX_TRIM_RK3588, priv->mmio + PHYREG27);
> +			writel(RK3588_PHYREG27_RX_TRIM, priv->mmio + RK3588_PHYREG27);
>  
>  			/* Set up su_trim:  */
> -			writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
> +			writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
>  		} else if (priv->type == PHY_TYPE_SATA) {
>  			/* downward spread spectrum +500ppm */
> -			val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
> -			val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
> -			rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
> +			val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
> +			val |= RK3568_PHYREG32_SSC_OFFSET_500PPM <<
> +			       RK3568_PHYREG32_SSC_OFFSET_SHIFT;
> +			rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
> +						 RK3568_PHYREG32);
>  		}
>  		break;
>  	default:
> @@ -1137,20 +1152,21 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
>  	if (priv->ext_refclk) {
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
>  		if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
> -			val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
> -			val |= PHYREG13_CKRCV_AMP0;
> -			rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
> -
> -			val = readl(priv->mmio + PHYREG14);
> -			val |= PHYREG14_CKRCV_AMP1;
> -			writel(val, priv->mmio + PHYREG14);
> +			val = RK3568_PHYREG13_RESISTER_HIGH_Z << RK3568_PHYREG13_RESISTER_SHIFT;
> +			val |= RK3568_PHYREG13_CKRCV_AMP0;
> +			rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val,
> +						 RK3568_PHYREG13);
> +
> +			val = readl(priv->mmio + RK3568_PHYREG14);
> +			val |= RK3568_PHYREG14_CKRCV_AMP1;
> +			writel(val, priv->mmio + RK3568_PHYREG14);
>  		}
>  	}
>  
>  	if (priv->enable_ssc) {
> -		val = readl(priv->mmio + PHYREG8);
> -		val |= PHYREG8_SSC_EN;
> -		writel(val, priv->mmio + PHYREG8);
> +		val = readl(priv->mmio + RK3568_PHYREG8);
> +		val |= RK3568_PHYREG8_SSC_EN;
> +		writel(val, priv->mmio + RK3568_PHYREG8);
>  	}
>  
>  	return 0;
> 






^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH 4/5] phy: rockchip: naneng-combphy: Add RK3528 support
  2025-05-08 13:53 ` [PATCH 4/5] phy: rockchip: naneng-combphy: Add RK3528 support Yao Zi
@ 2025-05-08 17:26   ` Heiko Stuebner
  2025-05-08 23:13     ` Yao Zi
  0 siblings, 1 reply; 12+ messages in thread
From: Heiko Stuebner @ 2025-05-08 17:26 UTC (permalink / raw)
  To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley, Yao Zi, Frank Wang, Andy Yan,
	Cristian Ciocaltea, Detlev Casanova, Shresth Prasad, Chukun Pan,
	Jonas Karlman, Yao Zi
  Cc: linux-phy, devicetree, linux-arm-kernel, linux-rockchip,
	linux-kernel

Am Donnerstag, 8. Mai 2025, 15:53:06 Mitteleuropäische Sommerzeit schrieb Yao Zi:
> Rockchip RK3528 integrates one naneng-combphy that is able to operate in
> PCIe and USB3 mode. The control logic is similar to previous variants of
> naneng-combphy but the register layout is apperantly different from the
> RK3568 one.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  .../rockchip/phy-rockchip-naneng-combphy.c    | 180 +++++++++++++++++-
>  1 file changed, 179 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> index 1d1c7723584b..7c92f7ac3c7f 100644
> --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> @@ -20,7 +20,40 @@
>  #define REF_CLOCK_25MHz			(25 * HZ_PER_MHZ)
>  #define REF_CLOCK_100MHz		(100 * HZ_PER_MHZ)
>  
> -/* COMBO PHY REG */
> +/* RK3528 COMBO PHY REG */
> +#define RK3528_PHYREG6				0x18
> +#define  RK3528_PHYREG6_PLL_KVCO		GENMASK(12, 10)
> +#define   RK3528_PHYREG6_PLL_KVCO_VALUE		0x2
> +#define  RK3528_PHYREG6_SSC_DIR			GENMASK(5, 4)
> +#define   RK3528_PHYREG6_SSC_UPWARD		0
> +#define   RK3528_PHYREG6_SSC_DOWNWARD		1
> +#define RK3528_PHYREG40				0x100
> +#define  RK3528_PHYREG40_SSC_EN			BIT(20)
> +#define  RK3528_PHYREG40_SSC_CNT		GENMASK(10, 0)
> +#define   RK3528_PHYREG40_SSC_CNT_VALUE		0x17d
> +#define RK3528_PHYREG42				0x108
> +#define  RK3528_PHYREG42_CKDRV_CLK_SEL		BIT(29)
> +#define   RK3528_PHYREG42_CKDRV_CLK_PLL		0
> +#define   RK3528_PHYREG42_CKDRV_CLK_CKRCV	1
> +#define  RK3528_PHYREG42_PLL_LPF_R1_ADJ		GENMASK(10, 7)
> +#define   RK3528_PHYREG42_PLL_LPF_R1_ADJ_VALUE	0x9
> +#define  RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ	GENMASK(6, 4)
> +#define   RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ_VALUE 0x7
> +#define  RK3528_PHYREG42_PLL_KVCO_ADJ		GENMASK(2, 0)
> +#define   RK3528_PHYREG42_PLL_KVCO_ADJ_VALUE	0x0
> +#define RK3528_PHYREG80				0x200
> +#define  RK3528_PHYREG80_CTLE_EN		BIT(17)
> +#define RK3528_PHYREG81				0x204
> +#define  RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X	BIT(5)
> +#define  RK3528_PHYREG81_SLEW_RATE_CTRL		GENMASK(2, 0)
> +#define   RK3528_PHYREG81_SLEW_RATE_CTRL_SLOW	0x7
> +#define RK3528_PHYREG83				0x20c
> +#define  RK3528_PHYREG83_RX_SQUELCH		GENMASK(2, 0)
> +#define   RK3528_PHYREG83_RX_SQUELCH_VALUE	0x6
> +#define RK3528_PHYREG86				0x218
> +#define  RK3528_PHYREG86_RTERM_DET_CLK_EN	BIT(14)

I'd think staying with one layout would be best, so not doing this
indentation here. Instead maybe follow the other ones like

#define RK3528_PHYREG6				0x18
#define RK3528_PHYREG6_PLL_KVCO		GENMASK(12, 10)
#define RK3528_PHYREG6_PLL_KVCO_VALUE		0x2
#define RK3528_PHYREG6_SSC_DIR			GENMASK(5, 4)
#define RK3528_PHYREG6_SSC_UPWARD		0
#define RK3528_PHYREG6_SSC_DOWNWARD		1

#define RK3528_PHYREG40				0x100
#define RK3528_PHYREG40_SSC_EN			BIT(20)
#define RK3528_PHYREG40_SSC_CNT		GENMASK(10, 0)
#define RK3528_PHYREG40_SSC_CNT_VALUE		0x17d

...

i.e. register + bits + blank line

other than that

Reviewed-by: Heiko Stuebner <heiko@sntech.de>




^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH 4/5] phy: rockchip: naneng-combphy: Add RK3528 support
  2025-05-08 17:26   ` Heiko Stuebner
@ 2025-05-08 23:13     ` Yao Zi
  0 siblings, 0 replies; 12+ messages in thread
From: Yao Zi @ 2025-05-08 23:13 UTC (permalink / raw)
  To: Heiko Stuebner, Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley, Frank Wang, Andy Yan,
	Cristian Ciocaltea, Detlev Casanova, Shresth Prasad, Chukun Pan,
	Jonas Karlman
  Cc: linux-phy, devicetree, linux-arm-kernel, linux-rockchip,
	linux-kernel

On Thu, May 08, 2025 at 07:26:13PM +0200, Heiko Stuebner wrote:
> Am Donnerstag, 8. Mai 2025, 15:53:06 Mitteleuropäische Sommerzeit schrieb Yao Zi:
> > Rockchip RK3528 integrates one naneng-combphy that is able to operate in
> > PCIe and USB3 mode. The control logic is similar to previous variants of
> > naneng-combphy but the register layout is apperantly different from the
> > RK3568 one.
> > 
> > Signed-off-by: Yao Zi <ziyao@disroot.org>
> > ---
> >  .../rockchip/phy-rockchip-naneng-combphy.c    | 180 +++++++++++++++++-
> >  1 file changed, 179 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> > index 1d1c7723584b..7c92f7ac3c7f 100644
> > --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> > +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> > @@ -20,7 +20,40 @@
> >  #define REF_CLOCK_25MHz			(25 * HZ_PER_MHZ)
> >  #define REF_CLOCK_100MHz		(100 * HZ_PER_MHZ)
> >  
> > -/* COMBO PHY REG */
> > +/* RK3528 COMBO PHY REG */
> > +#define RK3528_PHYREG6				0x18
> > +#define  RK3528_PHYREG6_PLL_KVCO		GENMASK(12, 10)
> > +#define   RK3528_PHYREG6_PLL_KVCO_VALUE		0x2
> > +#define  RK3528_PHYREG6_SSC_DIR			GENMASK(5, 4)
> > +#define   RK3528_PHYREG6_SSC_UPWARD		0
> > +#define   RK3528_PHYREG6_SSC_DOWNWARD		1
> > +#define RK3528_PHYREG40				0x100
> > +#define  RK3528_PHYREG40_SSC_EN			BIT(20)
> > +#define  RK3528_PHYREG40_SSC_CNT		GENMASK(10, 0)
> > +#define   RK3528_PHYREG40_SSC_CNT_VALUE		0x17d
> > +#define RK3528_PHYREG42				0x108
> > +#define  RK3528_PHYREG42_CKDRV_CLK_SEL		BIT(29)
> > +#define   RK3528_PHYREG42_CKDRV_CLK_PLL		0
> > +#define   RK3528_PHYREG42_CKDRV_CLK_CKRCV	1
> > +#define  RK3528_PHYREG42_PLL_LPF_R1_ADJ		GENMASK(10, 7)
> > +#define   RK3528_PHYREG42_PLL_LPF_R1_ADJ_VALUE	0x9
> > +#define  RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ	GENMASK(6, 4)
> > +#define   RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ_VALUE 0x7
> > +#define  RK3528_PHYREG42_PLL_KVCO_ADJ		GENMASK(2, 0)
> > +#define   RK3528_PHYREG42_PLL_KVCO_ADJ_VALUE	0x0
> > +#define RK3528_PHYREG80				0x200
> > +#define  RK3528_PHYREG80_CTLE_EN		BIT(17)
> > +#define RK3528_PHYREG81				0x204
> > +#define  RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X	BIT(5)
> > +#define  RK3528_PHYREG81_SLEW_RATE_CTRL		GENMASK(2, 0)
> > +#define   RK3528_PHYREG81_SLEW_RATE_CTRL_SLOW	0x7
> > +#define RK3528_PHYREG83				0x20c
> > +#define  RK3528_PHYREG83_RX_SQUELCH		GENMASK(2, 0)
> > +#define   RK3528_PHYREG83_RX_SQUELCH_VALUE	0x6
> > +#define RK3528_PHYREG86				0x218
> > +#define  RK3528_PHYREG86_RTERM_DET_CLK_EN	BIT(14)
> 
> I'd think staying with one layout would be best, so not doing this
> indentation here. Instead maybe follow the other ones like

Though seems more clear, it's reasonable to keep the style consistent.

Will change it in v2, thanks.

> #define RK3528_PHYREG6				0x18
> #define RK3528_PHYREG6_PLL_KVCO		GENMASK(12, 10)
> #define RK3528_PHYREG6_PLL_KVCO_VALUE		0x2
> #define RK3528_PHYREG6_SSC_DIR			GENMASK(5, 4)
> #define RK3528_PHYREG6_SSC_UPWARD		0
> #define RK3528_PHYREG6_SSC_DOWNWARD		1
> 
> #define RK3528_PHYREG40				0x100
> #define RK3528_PHYREG40_SSC_EN			BIT(20)
> #define RK3528_PHYREG40_SSC_CNT		GENMASK(10, 0)
> #define RK3528_PHYREG40_SSC_CNT_VALUE		0x17d
> 
> ...
> 
> i.e. register + bits + blank line
> 
> other than that
> 
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> 
> 

Best regards,
Yao Zi


^ permalink raw reply	[flat|nested] 12+ messages in thread

end of thread, other threads:[~2025-05-08 23:15 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-05-08 13:43 [PATCH 0/5] Support RK3528 variant of Rockchip naneng-combphy Yao Zi
2025-05-08 13:43 ` [PATCH 1/5] dt-bindings: soc: rockchip: Add RK3528 pipe-phy GRF syscon Yao Zi
2025-05-08 14:40   ` Conor Dooley
2025-05-08 13:43 ` [PATCH 2/5] dt-bindings: phy: rockchip: naneng-combphy: Add RK3528 variant Yao Zi
2025-05-08 14:40   ` Conor Dooley
2025-05-08 17:15   ` Heiko Stuebner
2025-05-08 13:52 ` [PATCH 3/5] phy: rockchip: naneng-combphy: Add SoC prefix to register definitions Yao Zi
2025-05-08 17:22   ` Heiko Stuebner
2025-05-08 13:53 ` [PATCH 4/5] phy: rockchip: naneng-combphy: Add RK3528 support Yao Zi
2025-05-08 17:26   ` Heiko Stuebner
2025-05-08 23:13     ` Yao Zi
2025-05-08 13:53 ` [PATCH 5/5] arm64: dts: rockchip: Add naneng-combphy for RK3528 Yao Zi

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