[BOOT-WRAPPER PATCH 3/3] aarch64: Enable use of ZT0

[Mark Rutland <mark.rutland@arm.com>]

FEAT_SME2 adds the ZT0 register. Accesses to ZT0 trap to EL3 unless
SMCR_EL3.EZT0 is set, and so boot-wrapper support is necessary.

Support for FEAT_SME2 was added to Linux in v6.3 without any
boot-wrapper support. Consequently when SME2 is enabled in a model, any
attempt to access ZT0 (whether in userspace, kernel, or hypervisor) will
result in a hang. Linux will (only) access ZT0 during a context switch
when PSTATE.ZA==1, and so this hang is seen long after boot, when
applications first set PSTATE.ZA.

Add boot-wrapper support for ZT0, as described in the latest ARM ARM
(ARM DDI 0487 L.a), which can be found at:

  https://developer.arm.com/documentation/ddi0487/la/?lang=en

All we need to do at EL3 is set SMCR_EL3.EZT0; it's up to lower ELs to
configure their SMCR_ELx register appropriately.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Mark Brown <broonie@kernel.org>
---
 arch/aarch64/include/asm/cpu.h | 1 +
 arch/aarch64/init.c            | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index aab7657..2b3a659 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -175,6 +175,7 @@
 #define ZCR_EL3_LEN_MAX		0xf
 
 #define SMCR_EL3		s3_6_c1_c2_6
+#define SMCR_EL3_EZT0		BIT(30)
 #define SMCR_EL3_FA64		BIT(31)
 #define SMCR_EL3_LEN_MAX	0xf
 
diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
index bb19848..e1640a9 100644
--- a/arch/aarch64/init.c
+++ b/arch/aarch64/init.c
@@ -189,6 +189,9 @@ static void cpu_init_el3(void)
 		if (mrs_field(ID_AA64SMFR0_EL1, FA64))
 			smcr |= SMCR_EL3_FA64;
 
+		if (mrs_field(ID_AA64PFR1_EL1, SME) >= 2)
+			smcr |= SMCR_EL3_EZT0;
+
 		msr(SMCR_EL3, smcr);
 	}
 }
-- 
2.30.2