From: Bjorn Helgaas <helgaas@kernel.org>
To: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Cc: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be,
magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org,
saravanak@google.com, p.zabel@pengutronix.de,
linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: Re: [PATCH 5/8] PCI: rzg3s-host: Add Initial PCIe Host Driver for Renesas RZ/G3S SoC
Date: Mon, 12 May 2025 15:38:51 -0500 [thread overview]
Message-ID: <20250512203851.GA1127434@bhelgaas> (raw)
In-Reply-To: <869269a7-8267-45f3-9e4d-678de18c0888@tuxon.dev>
On Fri, May 09, 2025 at 01:29:40PM +0300, Claudiu Beznea wrote:
> On 05.05.2025 14:26, Claudiu Beznea wrote:
> > On 01.05.2025 23:12, Bjorn Helgaas wrote:
> >> On Wed, Apr 30, 2025 at 01:32:33PM +0300, Claudiu wrote:
> >>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>>
> >>> The Renesas RZ/G3S features a PCIe IP that complies with the PCI Express
> >>> Base Specification 4.0 and supports speeds of up to 5 GT/s. It functions
> >>> only as a root complex, with a single-lane (x1) configuration. The
> >>> controller includes Type 1 configuration registers, as well as IP
> >>> specific registers (called AXI registers) required for various adjustments.
> >>>
> >>> Other Renesas RZ SoCs (e.g., RZ/G3E, RZ/V2H) share the same AXI registers
> >>> but have both Root Complex and Endpoint capabilities. As a result, the PCIe
> >>> host driver can be reused for these variants with minimal adjustments.
> ...
> >>> +static void rzg3s_pcie_update_bits(void __iomem *base, u32 offset, u32 mask, u32 val)
> >>> +{
> >>> + u32 tmp;
> >>> +
> >>> + tmp = readl(base + offset);
> >>> + tmp &= ~mask;
> >>> + tmp |= val & mask;
> >>> + writel(tmp, base + offset);
> >>> +}
> >>
> >> Nothing rzg3s-specific here.
> >>
> >> I think u32p_replace_bits() (include/linux/bitfield.h) is basically this.
> >
> > I wasn't aware of it. I'll use it in the next version. Thank for pointing it.
>
> I look into changing to u32p_replace_bits() but this one needs a mask that
> can be verified at build time. It cannot be used directly in this function.
> Would you prefer me to replace all the calls to rzg3s_pcie_update_bits() with:
>
> tmp = readl();
> u32p_replace_bits(&tmp, ...)
> writel(tmp);
It seems like this is the prevailing way it's used.
You have ~20 calls, so it seems like it might be excessive to replace
each with readl/u32p_replace_bits/writel.
But maybe you could use u32p_replace_bits() inside
rzg3s_pcie_update_bits().
Bjorn
next prev parent reply other threads:[~2025-05-12 20:41 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-30 10:32 [PATCH 0/8] PCI: rzg3s-host: Add PCIe driver for Renesas RZ/G3S SoC Claudiu
2025-04-30 10:32 ` [PATCH 1/8] soc: renesas: r9a08g045-sysc: Add max reg offset Claudiu
2025-05-01 9:26 ` kernel test robot
2025-05-01 10:32 ` kernel test robot
2025-05-01 16:12 ` kernel test robot
2025-04-30 10:32 ` [PATCH 2/8] clk: renesas: r9a08g045: Add clocks, resets and power domain support for the PCIe Claudiu
2025-04-30 10:32 ` [PATCH 3/8] of/irq: Export of_irq_count() Claudiu
2025-05-09 19:36 ` Rob Herring
2025-04-30 10:32 ` [PATCH 4/8] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Add documentation for the PCIe IP on Renesas RZ/G3S Claudiu
2025-05-01 20:16 ` Bjorn Helgaas
2025-05-05 11:28 ` Claudiu Beznea
2025-05-09 21:08 ` Rob Herring
2025-05-14 11:41 ` Claudiu Beznea
2025-04-30 10:32 ` [PATCH 5/8] PCI: rzg3s-host: Add Initial PCIe Host Driver for Renesas RZ/G3S SoC Claudiu
2025-05-01 20:12 ` Bjorn Helgaas
2025-05-05 11:26 ` Claudiu Beznea
2025-05-09 10:29 ` Claudiu Beznea
2025-05-12 20:38 ` Bjorn Helgaas [this message]
2025-05-14 10:29 ` Claudiu Beznea
2025-05-12 20:25 ` Bjorn Helgaas
2025-05-14 9:37 ` Claudiu Beznea
2025-05-09 10:51 ` Philipp Zabel
2025-05-09 11:41 ` Claudiu Beznea
2025-05-09 20:49 ` Rob Herring
2025-05-14 11:39 ` Claudiu Beznea
2025-04-30 10:32 ` [PATCH 6/8] arm64: dts: renesas: r9a08g045s33: Add PCIe node Claudiu
2025-04-30 10:32 ` [PATCH 7/8] arm64: dts: renesas: rzg3s-smarc: Enable PCIe Claudiu
2025-04-30 10:32 ` [PATCH 8/8] arm64: defconfig: Enable PCIe for the Renesas RZ/G3S SoC Claudiu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250512203851.GA1127434@bhelgaas \
--to=helgaas@kernel.org \
--cc=bhelgaas@google.com \
--cc=claudiu.beznea.uj@bp.renesas.com \
--cc=claudiu.beznea@tuxon.dev \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=geert+renesas@glider.be \
--cc=krzk+dt@kernel.org \
--cc=kw@linux.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-renesas-soc@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=magnus.damm@gmail.com \
--cc=manivannan.sadhasivam@linaro.org \
--cc=mturquette@baylibre.com \
--cc=p.zabel@pengutronix.de \
--cc=robh@kernel.org \
--cc=saravanak@google.com \
--cc=sboyd@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox