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Howlett" , Mark Rutland , Jiri Slaby , , , Subject: Re: [PATCH v4 18/26] arm64: smp: Support non-SGIs for IPIs Message-ID: <20250528131744.00001544@huawei.com> In-Reply-To: <20250513-gicv5-host-v4-18-b36e9b15a6c3@kernel.org> References: <20250513-gicv5-host-v4-0-b36e9b15a6c3@kernel.org> <20250513-gicv5-host-v4-18-b36e9b15a6c3@kernel.org> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.203.177.66] X-ClientProxiedBy: lhrpeml500002.china.huawei.com (7.191.160.78) To frapeml500008.china.huawei.com (7.182.85.71) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250528_051757_403574_F7CBEB2D X-CRM114-Status: GOOD ( 16.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 13 May 2025 19:48:11 +0200 Lorenzo Pieralisi wrote: > From: Marc Zyngier > > The arm64 arch has relied so far on GIC architectural software > generated interrupt (SGIs) to handle IPIs. Those are per-cpu > software generated interrupts. > > arm64 architecture code that allocates the IPIs virtual IRQs and > IRQ descriptors was written accordingly. > > On GICv5 systems, IPIs are implemented using LPIs that are not > per-cpu interrupts - they are just normal routable IRQs. > > Add arch code to set-up IPIs on systems where they are handled > using normal routable IRQs. > > For those systems, force the IRQ affinity (and make it immutable) > to the cpu a given IRQ was assigned to. > > Signed-off-by: Marc Zyngier > [timothy.hayes@arm.com: fixed ipi/irq conversion, irq flags] > Signed-off-by: Timothy Hayes > [lpieralisi: changed affinity set-up, log] > Signed-off-by: Lorenzo Pieralisi > Cc: Will Deacon > Cc: Catalin Marinas Hi Lorenzo, A few trivial comments inline. > + > +static int ipi_to_irq(int ipi, int cpu) Maybe this naming needs a breadcrumb to indicate this only applies only to lpi case as it's directly computed in the old ppi code? A comment might do the job. > +{ > + return ipi_irq_base + (cpu * nr_ipi) + ipi; > +} > + > +static int irq_to_ipi(int irq) > +{ > + return (irq - ipi_irq_base) % nr_ipi; > +} > +static void ipi_setup_lpi(int ipi, int ncpus) > +{ > + for (int cpu = 0; cpu < ncpus; cpu++) { > + int err, irq; > + > + irq = ipi_to_irq(ipi, cpu); > + > + err = irq_force_affinity(irq, cpumask_of(cpu)); > + Trivial local consistency thing but maybe no blank line here or... > + WARN(err, "Could not force affinity IRQ %d, err=%d\n", irq, err); > + > + err = request_irq(irq, ipi_handler, IRQF_NO_AUTOEN, "IPI", > + &irq_stat); > + here to match the style in ipi_setup_ppi() > + WARN(err, "Could not request IRQ %d, err=%d\n", irq, err); > + > + irq_set_status_flags(irq, (IRQ_HIDDEN | IRQ_NO_BALANCING_MASK)); > + > + get_ipi_desc(cpu, ipi) = irq_to_desc(irq); > + } > +}