From: Leo Yan <leo.yan@arm.com>
To: Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
James Clark <james.clark@linaro.org>,
linux-arm-kernel@lists.infradead.org,
linux-perf-users@vger.kernel.org
Subject: Re: [PATCH v2] perf: arm_spe: Relax period restriction
Date: Wed, 11 Jun 2025 10:03:37 +0100 [thread overview]
Message-ID: <20250611090337.GS8020@e132581.arm.com> (raw)
In-Reply-To: <20250528132501.129586-1-leo.yan@arm.com>
On Wed, May 28, 2025 at 02:25:01PM +0100, Leo Yan wrote:
> The minimum interval specified the PMSIDR_EL1.Interval field is a
> hardware recommendation. However, this value is set by hardware designer
> before the production. It may not accurately reflects actual hardware
> limitations, and tools currently have no way to test shorter periods.
>
> This change relaxes the limitation by allowing any non-zero periods.
> This gives chance for experimenting smaller periods.
>
> The downside is that small periods may increase the risk of AUX ring
> buffer overruns. When an overrun occurs, the perf core layer will
> trigger an irq work to disable the event and wake up the tool in user
> space to read the trace data. After the tool finishes reading, it will
> re-enable the AUX event.
>
> Signed-off-by: Leo Yan <leo.yan@arm.com>
Gentle ping. thanks!
> ---
>
> Changes from v1:
> - Shifted bits with FIELD_PREP().
> - Removed warning log which is not quite useful. (James Clark)
>
> drivers/perf/arm_spe_pmu.c | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c
> index 3efed8839a4e..e40e5daa838d 100644
> --- a/drivers/perf/arm_spe_pmu.c
> +++ b/drivers/perf/arm_spe_pmu.c
> @@ -308,12 +308,16 @@ static u64 arm_spe_event_to_pmscr(struct perf_event *event)
>
> static void arm_spe_event_sanitise_period(struct perf_event *event)
> {
> - struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu);
> u64 period = event->hw.sample_period;
> u64 max_period = PMSIRR_EL1_INTERVAL_MASK;
>
> - if (period < spe_pmu->min_period)
> - period = spe_pmu->min_period;
> + /*
> + * As per the Arm ARM (DDI 0487 L.a), section D24.7.12 PMSIRR_EL1,
> + * Sampling Interval Reload Register, the INTERVAL field (bits [31:8])
> + * states: "Software must set this to a nonzero value."
> + */
> + if (period < FIELD_PREP(PMSIRR_EL1_INTERVAL_MASK, 1))
> + period = FIELD_PREP(PMSIRR_EL1_INTERVAL_MASK, 1);
> else if (period > max_period)
> period = max_period;
> else
> --
> 2.34.1
>
next prev parent reply other threads:[~2025-06-11 9:09 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-28 13:25 [PATCH v2] perf: arm_spe: Relax period restriction Leo Yan
2025-06-11 9:03 ` Leo Yan [this message]
2025-06-11 15:12 ` James Clark
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